LXR linux/drivers/net/sunbmac.h

   1/* $Id: sunbmac.h,v 1.7 2000/07/11 22:35:22 davem Exp $
   2 * sunbmac.h: Defines for the Sun "Big MAC" 100baseT ethernet cards.
   3 *
   4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
   5 */
   6
   7#ifndef _SUNBMAC_H
   8#define _SUNBMAC_H
   9
  10/* QEC global registers. */
  11#define GLOB_CTRL       0x00UL  /* Control                  */
  12#define GLOB_STAT       0x04UL  /* Status                   */
  13#define GLOB_PSIZE      0x08UL  /* Packet Size              */
  14#define GLOB_MSIZE      0x0cUL  /* Local-mem size (64K)     */
  15#define GLOB_RSIZE      0x10UL  /* Receive partition size   */
  16#define GLOB_TSIZE      0x14UL  /* Transmit partition size  */
  17#define GLOB_REG_SIZE   0x18UL
  18
  19#define GLOB_CTRL_MMODE       0x40000000 /* MACE qec mode            */
  20#define GLOB_CTRL_BMODE       0x10000000 /* BigMAC qec mode          */
  21#define GLOB_CTRL_EPAR        0x00000020 /* Enable parity            */
  22#define GLOB_CTRL_ACNTRL      0x00000018 /* SBUS arbitration control */
  23#define GLOB_CTRL_B64         0x00000004 /* 64 byte dvma bursts      */
  24#define GLOB_CTRL_B32         0x00000002 /* 32 byte dvma bursts      */
  25#define GLOB_CTRL_B16         0x00000000 /* 16 byte dvma bursts      */
  26#define GLOB_CTRL_RESET       0x00000001 /* Reset the QEC            */
  27
  28#define GLOB_STAT_TX          0x00000008 /* BigMAC Transmit IRQ      */
  29#define GLOB_STAT_RX          0x00000004 /* BigMAC Receive IRQ       */
  30#define GLOB_STAT_BM          0x00000002 /* BigMAC Global IRQ        */
  31#define GLOB_STAT_ER          0x00000001 /* BigMAC Error IRQ         */
  32
  33#define GLOB_PSIZE_2048       0x00       /* 2k packet size           */
  34#define GLOB_PSIZE_4096       0x01       /* 4k packet size           */
  35#define GLOB_PSIZE_6144       0x10       /* 6k packet size           */
  36#define GLOB_PSIZE_8192       0x11       /* 8k packet size           */
  37
  38/* QEC BigMAC channel registers. */
  39#define CREG_CTRL       0x00UL  /* Control                   */
  40#define CREG_STAT       0x04UL  /* Status                    */
  41#define CREG_RXDS       0x08UL  /* RX descriptor ring ptr    */
  42#define CREG_TXDS       0x0cUL  /* TX descriptor ring ptr    */
  43#define CREG_RIMASK     0x10UL  /* RX Interrupt Mask         */
  44#define CREG_TIMASK     0x14UL  /* TX Interrupt Mask         */
  45#define CREG_QMASK      0x18UL  /* QEC Error Interrupt Mask  */
  46#define CREG_BMASK      0x1cUL  /* BigMAC Error Interrupt Mask*/
  47#define CREG_RXWBUFPTR  0x20UL  /* Local memory rx write ptr */
  48#define CREG_RXRBUFPTR  0x24UL  /* Local memory rx read ptr  */
  49#define CREG_TXWBUFPTR  0x28UL  /* Local memory tx write ptr */
  50#define CREG_TXRBUFPTR  0x2cUL  /* Local memory tx read ptr  */
  51#define CREG_CCNT       0x30UL  /* Collision Counter         */
  52#define CREG_REG_SIZE   0x34UL
  53
  54#define CREG_CTRL_TWAKEUP     0x00000001  /* Transmitter Wakeup, 'go'. */
  55
  56#define CREG_STAT_BERROR      0x80000000  /* BigMAC error              */
  57#define CREG_STAT_TXIRQ       0x00200000  /* Transmit Interrupt        */
  58#define CREG_STAT_TXDERROR    0x00080000  /* TX Descriptor is bogus    */
  59#define CREG_STAT_TXLERR      0x00040000  /* Late Transmit Error       */
  60#define CREG_STAT_TXPERR      0x00020000  /* Transmit Parity Error     */
  61#define CREG_STAT_TXSERR      0x00010000  /* Transmit SBUS error ack   */
  62#define CREG_STAT_RXIRQ       0x00000020  /* Receive Interrupt         */
  63#define CREG_STAT_RXDROP      0x00000010  /* Dropped a RX'd packet     */
  64#define CREG_STAT_RXSMALL     0x00000008  /* Receive buffer too small  */
  65#define CREG_STAT_RXLERR      0x00000004  /* Receive Late Error        */
  66#define CREG_STAT_RXPERR      0x00000002  /* Receive Parity Error      */
  67#define CREG_STAT_RXSERR      0x00000001  /* Receive SBUS Error ACK    */
  68
  69#define CREG_STAT_ERRORS      (CREG_STAT_BERROR|CREG_STAT_TXDERROR|CREG_STAT_TXLERR|   \
  70                               CREG_STAT_TXPERR|CREG_STAT_TXSERR|CREG_STAT_RXDROP|     \
  71                               CREG_STAT_RXSMALL|CREG_STAT_RXLERR|CREG_STAT_RXPERR|    \
  72                               CREG_STAT_RXSERR)
  73
  74#define CREG_QMASK_TXDERROR   0x00080000  /* TXD error                 */
  75#define CREG_QMASK_TXLERR     0x00040000  /* TX late error             */
  76#define CREG_QMASK_TXPERR     0x00020000  /* TX parity error           */
  77#define CREG_QMASK_TXSERR     0x00010000  /* TX sbus error ack         */
  78#define CREG_QMASK_RXDROP     0x00000010  /* RX drop                   */
  79#define CREG_QMASK_RXBERROR   0x00000008  /* RX buffer error           */
  80#define CREG_QMASK_RXLEERR    0x00000004  /* RX late error             */
  81#define CREG_QMASK_RXPERR     0x00000002  /* RX parity error           */
  82#define CREG_QMASK_RXSERR     0x00000001  /* RX sbus error ack         */
  83
  84/* BIGMAC core registers */
  85#define BMAC_XIFCFG     0x000UL /* XIF config register                */
  86        /* 0x004-->0x0fc, reserved */
  87#define BMAC_STATUS     0x100UL /* Status register, clear on read     */
  88#define BMAC_IMASK      0x104UL /* Interrupt mask register            */
  89        /* 0x108-->0x204, reserved */
  90#define BMAC_TXSWRESET  0x208UL /* Transmitter software reset         */
  91#define BMAC_TXCFG      0x20cUL /* Transmitter config register        */
  92#define BMAC_IGAP1      0x210UL /* Inter-packet gap 1                 */
  93#define BMAC_IGAP2      0x214UL /* Inter-packet gap 2                 */
  94#define BMAC_ALIMIT     0x218UL /* Transmit attempt limit             */
  95#define BMAC_STIME      0x21cUL /* Transmit slot time                 */
  96#define BMAC_PLEN       0x220UL /* Size of transmit preamble          */
  97#define BMAC_PPAT       0x224UL /* Pattern for transmit preamble      */
  98#define BMAC_TXDELIM    0x228UL /* Transmit delimiter                 */
  99#define BMAC_JSIZE      0x22cUL /* Toe jam...                         */
 100#define BMAC_TXPMAX     0x230UL /* Transmit max pkt size              */
 101#define BMAC_TXPMIN     0x234UL /* Transmit min pkt size              */
 102#define BMAC_PATTEMPT   0x238UL /* Count of transmit peak attempts    */
 103#define BMAC_DTCTR      0x23cUL /* Transmit defer timer               */
 104#define BMAC_NCCTR      0x240UL /* Transmit normal-collision counter  */
 105#define BMAC_FCCTR      0x244UL /* Transmit first-collision counter   */
 106#define BMAC_EXCTR      0x248UL /* Transmit excess-collision counter  */
 107#define BMAC_LTCTR      0x24cUL /* Transmit late-collision counter    */
 108#define BMAC_RSEED      0x250UL /* Transmit random number seed        */
 109#define BMAC_TXSMACHINE 0x254UL /* Transmit state machine             */
 110        /* 0x258-->0x304, reserved */
 111#define BMAC_RXSWRESET  0x308UL /* Receiver software reset            */
 112#define BMAC_RXCFG      0x30cUL /* Receiver config register           */
 113#define BMAC_RXPMAX     0x310UL /* Receive max pkt size               */
 114#define BMAC_RXPMIN     0x314UL /* Receive min pkt size               */
 115#define BMAC_MACADDR2   0x318UL /* Ether address register 2           */
 116#define BMAC_MACADDR1   0x31cUL /* Ether address register 1           */
 117#define BMAC_MACADDR0   0x320UL /* Ether address register 0           */
 118#define BMAC_FRCTR      0x324UL /* Receive frame receive counter      */
 119#define BMAC_GLECTR     0x328UL /* Receive giant-length error counter */
 120#define BMAC_UNALECTR   0x32cUL /* Receive unaligned error counter    */
 121#define BMAC_RCRCECTR   0x330UL /* Receive CRC error counter          */
 122#define BMAC_RXSMACHINE 0x334UL /* Receiver state machine             */
 123#define BMAC_RXCVALID   0x338UL /* Receiver code violation            */
 124        /* 0x33c, reserved */
 125#define BMAC_HTABLE3    0x340UL /* Hash table 3                       */
 126#define BMAC_HTABLE2    0x344UL /* Hash table 2                       */
 127#define BMAC_HTABLE1    0x348UL /* Hash table 1                       */
 128#define BMAC_HTABLE0    0x34cUL /* Hash table 0                       */
 129#define BMAC_AFILTER2   0x350UL /* Address filter 2                   */
 130#define BMAC_AFILTER1   0x354UL /* Address filter 1                   */
 131#define BMAC_AFILTER0   0x358UL /* Address filter 0                   */
 132#define BMAC_AFMASK     0x35cUL /* Address filter mask                */
 133#define BMAC_REG_SIZE   0x360UL
 134
 135/* BigMac XIF config register. */
 136#define BIGMAC_XCFG_ODENABLE   0x00000001 /* Output driver enable                     */
 137#define BIGMAC_XCFG_RESV       0x00000002 /* Reserved, write always as 1              */
 138#define BIGMAC_XCFG_MLBACK     0x00000004 /* Loopback-mode MII enable                 */
 139#define BIGMAC_XCFG_SMODE      0x00000008 /* Enable serial mode                       */
 140
 141/* BigMAC status register. */
 142#define BIGMAC_STAT_GOTFRAME   0x00000001 /* Received a frame                         */
 143#define BIGMAC_STAT_RCNTEXP    0x00000002 /* Receive frame counter expired            */
 144#define BIGMAC_STAT_ACNTEXP    0x00000004 /* Align-error counter expired              */
 145#define BIGMAC_STAT_CCNTEXP    0x00000008 /* CRC-error counter expired                */
 146#define BIGMAC_STAT_LCNTEXP    0x00000010 /* Length-error counter expired             */
 147#define BIGMAC_STAT_RFIFOVF    0x00000020 /* Receive FIFO overflow                    */
 148#define BIGMAC_STAT_CVCNTEXP   0x00000040 /* Code-violation counter expired           */
 149#define BIGMAC_STAT_SENTFRAME  0x00000100 /* Transmitted a frame                      */
 150#define BIGMAC_STAT_TFIFO_UND  0x00000200 /* Transmit FIFO underrun                   */
 151#define BIGMAC_STAT_MAXPKTERR  0x00000400 /* Max-packet size error                    */
 152#define BIGMAC_STAT_NCNTEXP    0x00000800 /* Normal-collision counter expired         */
 153#define BIGMAC_STAT_ECNTEXP    0x00001000 /* Excess-collision counter expired         */
 154#define BIGMAC_STAT_LCCNTEXP   0x00002000 /* Late-collision counter expired           */
 155#define BIGMAC_STAT_FCNTEXP    0x00004000 /* First-collision counter expired          */
 156#define BIGMAC_STAT_DTIMEXP    0x00008000 /* Defer-timer expired                      */
 157
 158/* BigMAC interrupt mask register. */
 159#define BIGMAC_IMASK_GOTFRAME  0x00000001 /* Received a frame                         */
 160#define BIGMAC_IMASK_RCNTEXP   0x00000002 /* Receive frame counter expired            */
 161#define BIGMAC_IMASK_ACNTEXP   0x00000004 /* Align-error counter expired              */
 162#define BIGMAC_IMASK_CCNTEXP   0x00000008 /* CRC-error counter expired                */
 163#define BIGMAC_IMASK_LCNTEXP   0x00000010 /* Length-error counter expired             */
 164#define BIGMAC_IMASK_RFIFOVF   0x00000020 /* Receive FIFO overflow                    */
 165#define BIGMAC_IMASK_CVCNTEXP  0x00000040 /* Code-violation counter expired           */
 166#define BIGMAC_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame                      */
 167#define BIGMAC_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun                   */
 168#define BIGMAC_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error                    */
 169#define BIGMAC_IMASK_NCNTEXP   0x00000800 /* Normal-collision counter expired         */
 170#define BIGMAC_IMASK_ECNTEXP   0x00001000 /* Excess-collision counter expired         */
 171#define BIGMAC_IMASK_LCCNTEXP  0x00002000 /* Late-collision counter expired           */
 172#define BIGMAC_IMASK_FCNTEXP   0x00004000 /* First-collision counter expired          */
 173#define BIGMAC_IMASK_DTIMEXP   0x00008000 /* Defer-timer expired                      */
 174
 175/* BigMac transmit config register. */
 176#define BIGMAC_TXCFG_ENABLE    0x00000001 /* Enable the transmitter                   */
 177#define BIGMAC_TXCFG_FIFO      0x00000010 /* Default tx fthresh...                    */
 178#define BIGMAC_TXCFG_SMODE     0x00000020 /* Enable slow transmit mode                */
 179#define BIGMAC_TXCFG_CIGN      0x00000040 /* Ignore transmit collisions               */
 180#define BIGMAC_TXCFG_FCSOFF    0x00000080 /* Do not emit FCS                          */
 181#define BIGMAC_TXCFG_DBACKOFF  0x00000100 /* Disable backoff                          */
 182#define BIGMAC_TXCFG_FULLDPLX  0x00000200 /* Enable full-duplex                       */
 183
 184/* BigMac receive config register. */
 185#define BIGMAC_RXCFG_ENABLE    0x00000001 /* Enable the receiver                      */
 186#define BIGMAC_RXCFG_FIFO      0x0000000e /* Default rx fthresh...                    */
 187#define BIGMAC_RXCFG_PSTRIP    0x00000020 /* Pad byte strip enable                    */
 188#define BIGMAC_RXCFG_PMISC     0x00000040 /* Enable promiscous mode                   */
 189#define BIGMAC_RXCFG_DERR      0x00000080 /* Disable error checking                   */
 190#define BIGMAC_RXCFG_DCRCS     0x00000100 /* Disable CRC stripping                    */
 191#define BIGMAC_RXCFG_ME        0x00000200 /* Receive packets addressed to me          */
 192#define BIGMAC_RXCFG_PGRP      0x00000400 /* Enable promisc group mode                */
 193#define BIGMAC_RXCFG_HENABLE   0x00000800 /* Enable the hash filter                   */
 194#define BIGMAC_RXCFG_AENABLE   0x00001000 /* Enable the address filter                */
 195
 196/* The BigMAC PHY transceiver.  Not nearly as sophisticated as the happy meal
 197 * one.  But it does have the "bit banger", oh baby.
 198 */
 199#define TCVR_TPAL       0x00UL
 200#define TCVR_MPAL       0x04UL
 201#define TCVR_REG_SIZE   0x08UL
 202
 203/* Frame commands. */
 204#define FRAME_WRITE           0x50020000
 205#define FRAME_READ            0x60020000
 206
 207/* Tranceiver registers. */
 208#define TCVR_PAL_SERIAL       0x00000001 /* Enable serial mode              */
 209#define TCVR_PAL_EXTLBACK     0x00000002 /* Enable external loopback        */
 210#define TCVR_PAL_MSENSE       0x00000004 /* Media sense                     */
 211#define TCVR_PAL_LTENABLE     0x00000008 /* Link test enable                */
 212#define TCVR_PAL_LTSTATUS     0x00000010 /* Link test status  (P1 only)     */
 213
 214/* Management PAL. */
 215#define MGMT_PAL_DCLOCK       0x00000001 /* Data clock                      */
 216#define MGMT_PAL_OENAB        0x00000002 /* Output enabler                  */
 217#define MGMT_PAL_MDIO         0x00000004 /* MDIO Data/attached              */
 218#define MGMT_PAL_TIMEO        0x00000008 /* Transmit enable timeout error   */
 219#define MGMT_PAL_EXT_MDIO     MGMT_PAL_MDIO
 220#define MGMT_PAL_INT_MDIO     MGMT_PAL_TIMEO
 221
 222/* Here are some PHY addresses. */
 223#define BIGMAC_PHY_EXTERNAL   0 /* External transceiver */
 224#define BIGMAC_PHY_INTERNAL   1 /* Internal transceiver */
 225
 226/* PHY registers */
 227#define BIGMAC_BMCR           0x00 /* Basic mode control register       */
 228#define BIGMAC_BMSR           0x01 /* Basic mode status register        */
 229
 230/* BMCR bits */
 231#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
 232#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
 233#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
 234#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
 235#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
 236#define BMCR_RESET              0x8000  /* Reset the DP83840           */
 237
 238/* BMSR bits */
 239#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
 240#define BMSR_JCD                0x0002  /* Jabber detected             */
 241#define BMSR_LSTATUS            0x0004  /* Link status                 */
 242
 243/* Ring descriptors and such, same as Quad Ethernet. */
 244struct be_rxd {
 245        u32 rx_flags;
 246        u32 rx_addr;
 247};
 248
 249#define RXD_OWN      0x80000000 /* Ownership.      */
 250#define RXD_UPDATE   0x10000000 /* Being Updated?  */
 251#define RXD_LENGTH   0x000007ff /* Packet Length.  */
 252
 253struct be_txd {
 254        u32 tx_flags;
 255        u32 tx_addr;
 256};
 257
 258#define TXD_OWN      0x80000000 /* Ownership.      */
 259#define TXD_SOP      0x40000000 /* Start Of Packet */
 260#define TXD_EOP      0x20000000 /* End Of Packet   */
 261#define TXD_UPDATE   0x10000000 /* Being Updated?  */
 262#define TXD_LENGTH   0x000007ff /* Packet Length.  */
 263
 264#define TX_RING_MAXSIZE   256
 265#define RX_RING_MAXSIZE   256
 266
 267#define TX_RING_SIZE      256
 268#define RX_RING_SIZE      256
 269
 270#define NEXT_RX(num)       (((num) + 1) & (RX_RING_SIZE - 1))
 271#define NEXT_TX(num)       (((num) + 1) & (TX_RING_SIZE - 1))
 272#define PREV_RX(num)       (((num) - 1) & (RX_RING_SIZE - 1))
 273#define PREV_TX(num)       (((num) - 1) & (TX_RING_SIZE - 1))
 274
 275#define TX_BUFFS_AVAIL(bp)                                    \
 276        (((bp)->tx_old <= (bp)->tx_new) ?                     \
 277          (bp)->tx_old + (TX_RING_SIZE - 1) - (bp)->tx_new :  \
 278                            (bp)->tx_old - (bp)->tx_new - 1)
 279
 280
 281#define RX_COPY_THRESHOLD  256
 282#define RX_BUF_ALLOC_SIZE  (ETH_FRAME_LEN + (64 * 3))
 283
 284struct bmac_init_block {
 285        struct be_rxd be_rxd[RX_RING_MAXSIZE];
 286        struct be_txd be_txd[TX_RING_MAXSIZE];
 287};
 288
 289#define bib_offset(mem, elem) \
 290((__u32)((unsigned long)(&(((struct bmac_init_block *)0)->mem[elem]))))
 291
 292/* Now software state stuff. */
 293enum bigmac_transceiver {
 294        external = 0,
 295        internal = 1,
 296        none     = 2,
 297};
 298
 299/* Timer state engine. */
 300enum bigmac_timer_state {
 301        ltrywait = 1,  /* Forcing try of all modes, from fastest to slowest. */
 302        asleep   = 2,  /* Timer inactive.                                    */
 303};
 304
 305struct bigmac {
 306        void __iomem    *gregs; /* QEC Global Registers               */
 307        void __iomem    *creg;  /* QEC BigMAC Channel Registers       */
 308        void __iomem    *bregs; /* BigMAC Registers                   */
 309        void __iomem    *tregs; /* BigMAC Transceiver                 */
 310        struct bmac_init_block  *bmac_block;    /* RX and TX descriptors */
 311        __u32                    bblock_dvma;   /* RX and TX descriptors */
 312
 313        spinlock_t              lock;
 314
 315        struct sk_buff          *rx_skbs[RX_RING_SIZE];
 316        struct sk_buff          *tx_skbs[TX_RING_SIZE];
 317
 318        int rx_new, tx_new, rx_old, tx_old;
 319
 320        int board_rev;                          /* BigMAC board revision.             */
 321
 322        enum bigmac_transceiver tcvr_type;
 323        unsigned int            bigmac_bursts;
 324        unsigned int            paddr;
 325        unsigned short          sw_bmsr;         /* SW copy of PHY BMSR               */
 326        unsigned short          sw_bmcr;         /* SW copy of PHY BMCR               */
 327        struct timer_list       bigmac_timer;
 328        enum bigmac_timer_state timer_state;
 329        unsigned int            timer_ticks;
 330
 331        struct net_device_stats enet_stats;
 332        struct platform_device  *qec_op;
 333        struct platform_device  *bigmac_op;
 334        struct net_device       *dev;
 335};
 336
 337/* We use this to acquire receive skb's that we can DMA directly into. */
 338#define ALIGNED_RX_SKB_ADDR(addr) \
 339        ((((unsigned long)(addr) + (64 - 1)) & ~(64 - 1)) - (unsigned long)(addr))
 340
 341static inline struct sk_buff *big_mac_alloc_skb(unsigned int length, gfp_t gfp_flags)
 342{
 343        struct sk_buff *skb;
 344
 345        skb = alloc_skb(length + 64, gfp_flags);
 346        if(skb) {
 347                int offset = ALIGNED_RX_SKB_ADDR(skb->data);
 348
 349                if(offset)
 350                        skb_reserve(skb, offset);
 351        }
 352        return skb;
 353}
 354
 355#endif /* !(_SUNBMAC_H) */
 356