1/* smctr.h: SMC Token Ring driver header for Linux 2 * 3 * Authors: 4 * - Jay Schulist <jschlst@samba.org> 5 */ 6 7#ifndef __LINUX_SMCTR_H 8#define __LINUX_SMCTR_H 9 10#ifdef __KERNEL__ 11 12#define MAX_TX_QUEUE 10 13 14#define SMC_HEADER_SIZE 14 15 16#define SMC_PAGE_OFFSET(X) (((unsigned long)(X) - tp->ram_access) & tp->page_offset_mask) 17 18#define INIT 0x0D 19#define RQ_ATTCH 0x10 20#define RQ_STATE 0x0F 21#define RQ_ADDR 0x0E 22#define CHG_PARM 0x0C 23#define RSP 0x00 24#define TX_FORWARD 0x09 25 26#define AC_FC_DAT ((3<<13) | 1) 27#define DAT 0x07 28 29#define RPT_NEW_MON 0x25 30#define RPT_SUA_CHG 0x26 31#define RPT_ACTIVE_ERR 0x28 32#define RPT_NN_INCMP 0x27 33#define RPT_ERROR 0x29 34 35#define RQ_INIT 0x20 36#define RPT_ATTCH 0x24 37#define RPT_STATE 0x23 38#define RPT_ADDR 0x22 39 40#define POSITIVE_ACK 0x0001 41#define A_FRAME_WAS_FORWARDED 0x8888 42 43#define GROUP_ADDRESS 0x2B 44#define PHYSICAL_DROP 0x0B 45#define AUTHORIZED_ACCESS_PRIORITY 0x07 46#define AUTHORIZED_FUNCTION_CLASS 0x06 47#define FUNCTIONAL_ADDRESS 0x2C 48#define RING_STATION_STATUS 0x29 49#define TRANSMIT_STATUS_CODE 0x2A 50#define IBM_PASS_SOURCE_ADDR 0x01 51#define AC_FC_RPT_TX_FORWARD ((0<<13) | 0) 52#define AC_FC_RPT_STATE ((0<<13) | 0) 53#define AC_FC_RPT_ADDR ((0<<13) | 0) 54#define CORRELATOR 0x09 55 56#define POSITIVE_ACK 0x0001 /* */ 57#define E_MAC_DATA_INCOMPLETE 0x8001 /* not used */ 58#define E_VECTOR_LENGTH_ERROR 0x8002 /* */ 59#define E_UNRECOGNIZED_VECTOR_ID 0x8003 /* */ 60#define E_INAPPROPRIATE_SOURCE_CLASS 0x8004 /* */ 61#define E_SUB_VECTOR_LENGTH_ERROR 0x8005 /* */ 62#define E_TRANSMIT_FORWARD_INVALID 0x8006 /* def. by IBM */ 63#define E_MISSING_SUB_VECTOR 0x8007 /* */ 64#define E_SUB_VECTOR_UNKNOWN 0x8008 /* */ 65#define E_MAC_HEADER_TOO_LONG 0x8009 /* */ 66#define E_FUNCTION_DISABLED 0x800A /* not used */ 67 68#define A_FRAME_WAS_FORWARDED 0x8888 /* used by send_TX_FORWARD */ 69 70#define UPSTREAM_NEIGHBOR_ADDRESS 0x02 71#define LOCAL_RING_NUMBER 0x03 72#define ASSIGN_PHYSICAL_DROP 0x04 73#define ERROR_TIMER_VALUE 0x05 74#define AUTHORIZED_FUNCTION_CLASS 0x06 75#define AUTHORIZED_ACCESS_PRIORITY 0x07 76#define CORRELATOR 0x09 77#define PHYSICAL_DROP 0x0B 78#define RESPONSE_CODE 0x20 79#define ADDRESS_MODIFER 0x21 80#define PRODUCT_INSTANCE_ID 0x22 81#define RING_STATION_VERSION_NUMBER 0x23 82#define WRAP_DATA 0x26 83#define FRAME_FORWARD 0x27 84#define STATION_IDENTIFER 0x28 85#define RING_STATION_STATUS 0x29 86#define TRANSMIT_STATUS_CODE 0x2A 87#define GROUP_ADDRESS 0x2B 88#define FUNCTIONAL_ADDRESS 0x2C 89 90#define F_NO_SUB_VECTORS_FOUND 0x0000 91#define F_UPSTREAM_NEIGHBOR_ADDRESS 0x0001 92#define F_LOCAL_RING_NUMBER 0x0002 93#define F_ASSIGN_PHYSICAL_DROP 0x0004 94#define F_ERROR_TIMER_VALUE 0x0008 95#define F_AUTHORIZED_FUNCTION_CLASS 0x0010 96#define F_AUTHORIZED_ACCESS_PRIORITY 0x0020 97#define F_CORRELATOR 0x0040 98#define F_PHYSICAL_DROP 0x0080 99#define F_RESPONSE_CODE 0x0100 100#define F_PRODUCT_INSTANCE_ID 0x0200 101#define F_RING_STATION_VERSION_NUMBER 0x0400 102#define F_STATION_IDENTIFER 0x0800 103#define F_RING_STATION_STATUS 0x1000 104#define F_GROUP_ADDRESS 0x2000 105#define F_FUNCTIONAL_ADDRESS 0x4000 106#define F_FRAME_FORWARD 0x8000 107 108#define R_INIT 0x00 109#define R_RQ_ATTCH_STATE_ADDR 0x00 110#define R_CHG_PARM 0x00 111#define R_TX_FORWARD F_FRAME_FORWARD 112 113 114#define UPSTREAM_NEIGHBOR_ADDRESS 0x02 115#define ADDRESS_MODIFER 0x21 116#define RING_STATION_VERSION_NUMBER 0x23 117#define PRODUCT_INSTANCE_ID 0x22 118 119#define RPT_TX_FORWARD 0x2A 120 121#define AC_FC_INIT (3<<13) | 0 /* */ 122#define AC_FC_RQ_INIT ((3<<13) | 0) /* */ 123#define AC_FC_RQ_ATTCH (3<<13) | 0 /* DC = SC of rx frame */ 124#define AC_FC_RQ_STATE (3<<13) | 0 /* DC = SC of rx frame */ 125#define AC_FC_RQ_ADDR (3<<13) | 0 /* DC = SC of rx frame */ 126#define AC_FC_CHG_PARM (3<<13) | 0 /* */ 127#define AC_FC_RSP (0<<13) | 0 /* DC = SC of rx frame */ 128#define AC_FC_RPT_ATTCH (0<<13) | 0 129 130#define S_UPSTREAM_NEIGHBOR_ADDRESS 6 + 2 131#define S_LOCAL_RING_NUMBER 2 + 2 132#define S_ASSIGN_PHYSICAL_DROP 4 + 2 133#define S_ERROR_TIMER_VALUE 2 + 2 134#define S_AUTHORIZED_FUNCTION_CLASS 2 + 2 135#define S_AUTHORIZED_ACCESS_PRIORITY 2 + 2 136#define S_CORRELATOR 2 + 2 137#define S_PHYSICAL_DROP 4 + 2 138#define S_RESPONSE_CODE 4 + 2 139#define S_ADDRESS_MODIFER 2 + 2 140#define S_PRODUCT_INSTANCE_ID 18 + 2 141#define S_RING_STATION_VERSION_NUMBER 10 + 2 142#define S_STATION_IDENTIFER 6 + 2 143#define S_RING_STATION_STATUS 6 + 2 144#define S_GROUP_ADDRESS 4 + 2 145#define S_FUNCTIONAL_ADDRESS 4 + 2 146#define S_FRAME_FORWARD 252 + 2 147#define S_TRANSMIT_STATUS_CODE 2 + 2 148 149#define ISB_IMC_RES0 0x0000 /* */ 150#define ISB_IMC_MAC_TYPE_3 0x0001 /* MAC_ARC_INDICATE */ 151#define ISB_IMC_MAC_ERROR_COUNTERS 0x0002 /* */ 152#define ISB_IMC_RES1 0x0003 /* */ 153#define ISB_IMC_MAC_TYPE_2 0x0004 /* QUE_MAC_INDICATE */ 154#define ISB_IMC_TX_FRAME 0x0005 /* */ 155#define ISB_IMC_END_OF_TX_QUEUE 0x0006 /* */ 156#define ISB_IMC_NON_MAC_RX_RESOURCE 0x0007 /* */ 157#define ISB_IMC_MAC_RX_RESOURCE 0x0008 /* */ 158#define ISB_IMC_NON_MAC_RX_FRAME 0x0009 /* */ 159#define ISB_IMC_MAC_RX_FRAME 0x000A /* */ 160#define ISB_IMC_TRC_FIFO_STATUS 0x000B /* */ 161#define ISB_IMC_COMMAND_STATUS 0x000C /* */ 162#define ISB_IMC_MAC_TYPE_1 0x000D /* Self Removed */ 163#define ISB_IMC_TRC_INTRNL_TST_STATUS 0x000E /* */ 164#define ISB_IMC_RES2 0x000F /* */ 165 166#define NON_MAC_RX_RESOURCE_BW 0x10 /* shifted right 8 bits */ 167#define NON_MAC_RX_RESOURCE_FW 0x20 /* shifted right 8 bits */ 168#define NON_MAC_RX_RESOURCE_BE 0x40 /* shifted right 8 bits */ 169#define NON_MAC_RX_RESOURCE_FE 0x80 /* shifted right 8 bits */ 170#define RAW_NON_MAC_RX_RESOURCE_BW 0x1000 /* */ 171#define RAW_NON_MAC_RX_RESOURCE_FW 0x2000 /* */ 172#define RAW_NON_MAC_RX_RESOURCE_BE 0x4000 /* */ 173#define RAW_NON_MAC_RX_RESOURCE_FE 0x8000 /* */ 174 175#define MAC_RX_RESOURCE_BW 0x10 /* shifted right 8 bits */ 176#define MAC_RX_RESOURCE_FW 0x20 /* shifted right 8 bits */ 177#define MAC_RX_RESOURCE_BE 0x40 /* shifted right 8 bits */ 178#define MAC_RX_RESOURCE_FE 0x80 /* shifted right 8 bits */ 179#define RAW_MAC_RX_RESOURCE_BW 0x1000 /* */ 180#define RAW_MAC_RX_RESOURCE_FW 0x2000 /* */ 181#define RAW_MAC_RX_RESOURCE_BE 0x4000 /* */ 182#define RAW_MAC_RX_RESOURCE_FE 0x8000 /* */ 183 184#define TRC_FIFO_STATUS_TX_UNDERRUN 0x40 /* shifted right 8 bits */ 185#define TRC_FIFO_STATUS_RX_OVERRUN 0x80 /* shifted right 8 bits */ 186#define RAW_TRC_FIFO_STATUS_TX_UNDERRUN 0x4000 /* */ 187#define RAW_TRC_FIFO_STATUS_RX_OVERRUN 0x8000 /* */ 188 189#define CSR_CLRTINT 0x08 190 191#define MSB(X) ((__u8)((__u16) X >> 8)) 192#define LSB(X) ((__u8)((__u16) X & 0xff)) 193 194#define AC_FC_LOBE_MEDIA_TEST ((3<<13) | 0) 195#define S_WRAP_DATA 248 + 2 /* 500 + 2 */ 196#define WRAP_DATA 0x26 197#define LOBE_MEDIA_TEST 0x08 198 199/* Destination Class (dc) */ 200 201#define DC_MASK 0xF0 202#define DC_RS 0x00 203#define DC_CRS 0x40 204#define DC_RPS 0x50 205#define DC_REM 0x60 206 207/* Source Classes (sc) */ 208 209#define SC_MASK 0x0F 210#define SC_RS 0x00 211#define SC_CRS 0x04 212#define SC_RPS 0x05 213#define SC_REM 0x06 214 215#define PR 0x11 216#define PR_PAGE_MASK 0x0C000 217 218#define MICROCHANNEL 0x0008 219#define INTERFACE_CHIP 0x0010 220#define BOARD_16BIT 0x0040 221#define PAGED_RAM 0x0080 222#define WD8115TA (TOKEN_MEDIA | MICROCHANNEL | INTERFACE_CHIP | PAGED_RAM) 223#define WD8115T (TOKEN_MEDIA | INTERFACE_CHIP | BOARD_16BIT | PAGED_RAM) 224 225#define BRD_ID_8316 0x50 226 227#define r587_SER 0x001 228#define SER_DIN 0x80 229#define SER_DOUT 0x40 230#define SER_CLK 0x20 231#define SER_ECS 0x10 232#define SER_E806 0x08 233#define SER_PNP 0x04 234#define SER_BIO 0x02 235#define SER_16B 0x01 236 237#define r587_IDR 0x004 238#define IDR_IRQ_MASK 0x0F0 239#define IDR_DCS_MASK 0x007 240#define IDR_RWS 0x008 241 242 243#define r587_BIO 0x003 244#define BIO_ENB 0x080 245#define BIO_MASK 0x03F 246 247#define r587_PCR 0x005 248#define PCR_RAMS 0x040 249 250 251 252#define NUM_ADDR_BITS 8 253 254#define ISA_MAX_ADDRESS 0x00ffffff 255 256#define SMCTR_MAX_ADAPTERS 7 257 258#define MC_TABLE_ENTRIES 16 259 260#define MAXFRAGMENTS 32 261 262#define CHIP_REV_MASK 0x3000 263 264#define MAX_TX_QS 8 265#define NUM_TX_QS_USED 3 266 267#define MAX_RX_QS 2 268#define NUM_RX_QS_USED 2 269 270#define INTEL_DATA_FORMAT 0x4000 271#define INTEL_ADDRESS_POINTER_FORMAT 0x8000 272#define PAGE_POINTER(X) ((((unsigned long)(X) - tp->ram_access) & tp->page_offset_mask) + tp->ram_access) 273#define SWAP_WORDS(X) (((X & 0xFFFF) << 16) | (X >> 16)) 274 275#define INTERFACE_CHIP 0x0010 /* Soft Config Adapter */ 276#define ADVANCED_FEATURES 0x0020 /* Adv. netw. interface features */ 277#define BOARD_16BIT 0x0040 /* 16 bit capability */ 278#define PAGED_RAM 0x0080 /* Adapter has paged RAM */ 279 280#define PAGED_ROM 0x0100 /* Adapter has paged ROM */ 281 282#define RAM_SIZE_UNKNOWN 0x0000 /* Unknown RAM size */ 283#define RAM_SIZE_0K 0x0001 /* 0K RAM */ 284#define RAM_SIZE_8K 0x0002 /* 8k RAM */ 285#define RAM_SIZE_16K 0x0003 /* 16k RAM */ 286#define RAM_SIZE_32K 0x0004 /* 32k RAM */ 287#define RAM_SIZE_64K 0x0005 /* 64k RAM */ 288#define RAM_SIZE_RESERVED_6 0x0006 /* Reserved RAM size */ 289#define RAM_SIZE_RESERVED_7 0x0007 /* Reserved RAM size */ 290#define RAM_SIZE_MASK 0x0007 /* Isolates RAM Size */ 291 292#define TOKEN_MEDIA 0x0005 293 294#define BID_REG_0 0x00 295#define BID_REG_1 0x01 296#define BID_REG_2 0x02 297#define BID_REG_3 0x03 298#define BID_REG_4 0x04 299#define BID_REG_5 0x05 300#define BID_REG_6 0x06 301#define BID_REG_7 0x07 302#define BID_LAR_0 0x08 303#define BID_LAR_1 0x09 304#define BID_LAR_2 0x0A 305#define BID_LAR_3 0x0B 306#define BID_LAR_4 0x0C 307#define BID_LAR_5 0x0D 308 309#define BID_BOARD_ID_BYTE 0x0E 310#define BID_CHCKSM_BYTE 0x0F 311#define BID_LAR_OFFSET 0x08 312 313#define BID_MSZ_583_BIT 0x08 314#define BID_SIXTEEN_BIT_BIT 0x01 315 316#define BID_BOARD_REV_MASK 0x1E 317 318#define BID_MEDIA_TYPE_BIT 0x01 319#define BID_SOFT_CONFIG_BIT 0x20 320#define BID_RAM_SIZE_BIT 0x40 321#define BID_BUS_TYPE_BIT 0x80 322 323#define BID_CR 0x10 324 325#define BID_TXP 0x04 /* Transmit Packet Command */ 326 327#define BID_TCR_DIFF 0x0D /* Transmit Configuration Register */ 328 329#define BID_TCR_VAL 0x18 /* Value to Test 8390 or 690 */ 330#define BID_PS0 0x00 /* Register Page Select 0 */ 331#define BID_PS1 0x40 /* Register Page Select 1 */ 332#define BID_PS2 0x80 /* Register Page Select 2 */ 333#define BID_PS_MASK 0x3F /* For Masking Off Page Select Bits */ 334 335#define BID_EEPROM_0 0x08 336#define BID_EEPROM_1 0x09 337#define BID_EEPROM_2 0x0A 338#define BID_EEPROM_3 0x0B 339#define BID_EEPROM_4 0x0C 340#define BID_EEPROM_5 0x0D 341#define BID_EEPROM_6 0x0E 342#define BID_EEPROM_7 0x0F 343 344#define BID_OTHER_BIT 0x02 345#define BID_ICR_MASK 0x0C 346#define BID_EAR_MASK 0x0F 347#define BID_ENGR_PAGE 0x0A0 348#define BID_RLA 0x10 349#define BID_EA6 0x80 350#define BID_RECALL_DONE_MASK 0x10 351#define BID_BID_EEPROM_OVERRIDE 0xFFB0 352#define BID_EXTRA_EEPROM_OVERRIDE 0xFFD0 353#define BID_EEPROM_MEDIA_MASK 0x07 354#define BID_STARLAN_TYPE 0x00 355#define BID_ETHERNET_TYPE 0x01 356#define BID_TP_TYPE 0x02 357#define BID_EW_TYPE 0x03 358#define BID_TOKEN_RING_TYPE 0x04 359#define BID_UTP2_TYPE 0x05 360#define BID_EEPROM_IRQ_MASK 0x18 361#define BID_PRIMARY_IRQ 0x00 362#define BID_ALTERNATE_IRQ_1 0x08 363#define BID_ALTERNATE_IRQ_2 0x10 364#define BID_ALTERNATE_IRQ_3 0x18 365#define BID_EEPROM_RAM_SIZE_MASK 0xE0 366#define BID_EEPROM_RAM_SIZE_RES1 0x00 367#define BID_EEPROM_RAM_SIZE_RES2 0x20 368#define BID_EEPROM_RAM_SIZE_8K 0x40 369#define BID_EEPROM_RAM_SIZE_16K 0x60 370#define BID_EEPROM_RAM_SIZE_32K 0x80 371#define BID_EEPROM_RAM_SIZE_64K 0xA0 372#define BID_EEPROM_RAM_SIZE_RES3 0xC0 373#define BID_EEPROM_RAM_SIZE_RES4 0xE0 374#define BID_EEPROM_BUS_TYPE_MASK 0x07 375#define BID_EEPROM_BUS_TYPE_AT 0x00 376#define BID_EEPROM_BUS_TYPE_MCA 0x01 377#define BID_EEPROM_BUS_TYPE_EISA 0x02 378#define BID_EEPROM_BUS_TYPE_NEC 0x03 379#define BID_EEPROM_BUS_SIZE_MASK 0x18 380#define BID_EEPROM_BUS_SIZE_8BIT 0x00 381#define BID_EEPROM_BUS_SIZE_16BIT 0x08 382#define BID_EEPROM_BUS_SIZE_32BIT 0x10 383#define BID_EEPROM_BUS_SIZE_64BIT 0x18 384#define BID_EEPROM_BUS_MASTER 0x20 385#define BID_EEPROM_RAM_PAGING 0x40 386#define BID_EEPROM_ROM_PAGING 0x80 387#define BID_EEPROM_PAGING_MASK 0xC0 388#define BID_EEPROM_LOW_COST 0x08 389#define BID_EEPROM_IO_MAPPED 0x10 390#define BID_EEPROM_HMI 0x01 391#define BID_EEPROM_AUTO_MEDIA_DETECT 0x01 392#define BID_EEPROM_CHIP_REV_MASK 0x0C 393 394#define BID_EEPROM_LAN_ADDR 0x30 395 396#define BID_EEPROM_MEDIA_OPTION 0x54 397#define BID_EEPROM_MEDIA_UTP 0x01 398#define BID_EEPROM_4MB_RING 0x08 399#define BID_EEPROM_16MB_RING 0x10 400#define BID_EEPROM_MEDIA_STP 0x40 401 402#define BID_EEPROM_MISC_DATA 0x56 403#define BID_EEPROM_EARLY_TOKEN_RELEASE 0x02 404 405#define CNFG_ID_8003E 0x6fc0 406#define CNFG_ID_8003S 0x6fc1 407#define CNFG_ID_8003W 0x6fc2 408#define CNFG_ID_8115TRA 0x6ec6 409#define CNFG_ID_8013E 0x61C8 410#define CNFG_ID_8013W 0x61C9 411#define CNFG_ID_BISTRO03E 0xEFE5 412#define CNFG_ID_BISTRO13E 0xEFD5 413#define CNFG_ID_BISTRO13W 0xEFD4 414#define CNFG_MSR_583 0x0 415#define CNFG_ICR_583 0x1 416#define CNFG_IAR_583 0x2 417#define CNFG_BIO_583 0x3 418#define CNFG_EAR_583 0x3 419#define CNFG_IRR_583 0x4 420#define CNFG_LAAR_584 0x5 421#define CNFG_GP2 0x7 422#define CNFG_LAAR_MASK 0x1F 423#define CNFG_LAAR_ZWS 0x20 424#define CNFG_LAAR_L16E 0x40 425#define CNFG_ICR_IR2_584 0x04 426#define CNFG_ICR_MASK 0x08 427#define CNFG_ICR_MSZ 0x08 428#define CNFG_ICR_RLA 0x10 429#define CNFG_ICR_STO 0x80 430#define CNFG_IRR_IRQS 0x60 431#define CNFG_IRR_IEN 0x80 432#define CNFG_IRR_ZWS 0x01 433#define CNFG_GP2_BOOT_NIBBLE 0x0F 434#define CNFG_IRR_OUT2 0x04 435#define CNFG_IRR_OUT1 0x02 436 437#define CNFG_SIZE_8KB 8 438#define CNFG_SIZE_16KB 16 439#define CNFG_SIZE_32KB 32 440#define CNFG_SIZE_64KB 64 441#define CNFG_SIZE_128KB 128 442#define CNFG_SIZE_256KB 256 443#define ROM_DISABLE 0x0 444 445#define CNFG_SLOT_ENABLE_BIT 0x08 446 447#define CNFG_POS_CONTROL_REG 0x096 448#define CNFG_POS_REG0 0x100 449#define CNFG_POS_REG1 0x101 450#define CNFG_POS_REG2 0x102 451#define CNFG_POS_REG3 0x103 452#define CNFG_POS_REG4 0x104 453#define CNFG_POS_REG5 0x105 454 455#define CNFG_ADAPTER_TYPE_MASK 0x0e 456 457#define SLOT_16BIT 0x0008 458#define INTERFACE_5X3_CHIP 0x0000 /* 0000 = 583 or 593 chips */ 459#define NIC_690_BIT 0x0010 /* NIC is 690 */ 460#define ALTERNATE_IRQ_BIT 0x0020 /* Alternate IRQ is used */ 461#define INTERFACE_584_CHIP 0x0040 /* 0001 = 584 chip */ 462#define INTERFACE_594_CHIP 0x0080 /* 0010 = 594 chip */ 463#define INTERFACE_585_CHIP 0x0100 /* 0100 = 585/790 chip */ 464#define INTERFACE_CHIP_MASK 0x03C0 /* Isolates Intfc Chip Type */ 465 466#define BOARD_16BIT 0x0040 467#define NODE_ADDR_CKSUM 0xEE 468#define BRD_ID_8115T 0x04 469 470#define NIC_825_BIT 0x0400 /* TRC 83C825 NIC */ 471#define NIC_790_BIT 0x0800 /* NIC is 83C790 Ethernet */ 472 473#define CHIP_REV_MASK 0x3000 474 475#define HWR_CBUSY 0x02 476#define HWR_CA 0x01 477 478#define MAC_QUEUE 0 479#define NON_MAC_QUEUE 1 480#define BUG_QUEUE 2 /* NO RECEIVE QUEUE, ONLY TX */ 481 482#define NUM_MAC_TX_FCBS 8 483#define NUM_MAC_TX_BDBS NUM_MAC_TX_FCBS 484#define NUM_MAC_RX_FCBS 7 485#define NUM_MAC_RX_BDBS 8 486 487#define NUM_NON_MAC_TX_FCBS 6 488#define NUM_NON_MAC_TX_BDBS NUM_NON_MAC_TX_FCBS 489 490#define NUM_NON_MAC_RX_BDBS 0 /* CALCULATED DYNAMICALLY */ 491 492#define NUM_BUG_TX_FCBS 8 493#define NUM_BUG_TX_BDBS NUM_BUG_TX_FCBS 494 495#define MAC_TX_BUFFER_MEMORY 1024 496#define NON_MAC_TX_BUFFER_MEMORY (20 * 1024) 497#define BUG_TX_BUFFER_MEMORY (NUM_BUG_TX_FCBS * 32) 498 499#define RX_BUFFER_MEMORY 0 /* CALCULATED DYNAMICALLY */ 500#define RX_DATA_BUFFER_SIZE 256 501#define RX_BDB_SIZE_SHIFT 3 /* log2(RX_DATA_BUFFER_SIZE)-log2(sizeof(BDBlock)) */ 502#define RX_BDB_SIZE_MASK (sizeof(BDBlock) - 1) 503#define RX_DATA_BUFFER_SIZE_MASK (RX_DATA_BUFFER_SIZE-1) 504 505#define NUM_OF_INTERRUPTS 0x20 506 507#define NOT_TRANSMITING 0 508#define TRANSMITING 1 509 510#define TRC_INTERRUPT_ENABLE_MASK 0x7FF6 511 512#define UCODE_VERSION 0x58 513 514#define UCODE_SIZE_OFFSET 0x0000 /* WORD */ 515#define UCODE_CHECKSUM_OFFSET 0x0002 /* WORD */ 516#define UCODE_VERSION_OFFSET 0x0004 /* BYTE */ 517 518#define CS_RAM_SIZE 0X2000 519#define CS_RAM_CHECKSUM_OFFSET 0x1FFE /* WORD 1FFE(MSB)-1FFF(LSB)*/ 520#define CS_RAM_VERSION_OFFSET 0x1FFC /* WORD 1FFC(MSB)-1FFD(LSB)*/ 521 522#define MISC_DATA_SIZE 128 523#define NUM_OF_ACBS 1 524 525#define ACB_COMMAND_NOT_DONE 0x0000 /* Init, command not done */ 526#define ACB_COMMAND_DONE 0x8000 /* TRC says command done */ 527#define ACB_COMMAND_STATUS_MASK 0x00FF /* low byte is status */ 528#define ACB_COMMAND_SUCCESSFUL 0x0000 /* means cmd was successful */ 529#define ACB_NOT_CHAIN_END 0x0000 /* tell TRC more CBs in chain */ 530#define ACB_CHAIN_END 0x8000 /* tell TRC last CB in chain */ 531#define ACB_COMMAND_NO_INTERRUPT 0x0000 /* tell TRC no INT after CB */ 532#define ACB_COMMAND_INTERRUPT 0x2000 /* tell TRC to INT after CB */ 533#define ACB_SUB_CMD_NOP 0x0000 534#define ACB_CMD_HIC_NOP 0x0080 535#define ACB_CMD_MCT_NOP 0x0000 536#define ACB_CMD_MCT_TEST 0x0001 537#define ACB_CMD_HIC_TEST 0x0081 538#define ACB_CMD_INSERT 0x0002 539#define ACB_CMD_REMOVE 0x0003 540#define ACB_CMD_MCT_WRITE_VALUE 0x0004 541#define ACB_CMD_HIC_WRITE_VALUE 0x0084 542#define ACB_CMD_MCT_READ_VALUE 0x0005 543#define ACB_CMD_HIC_READ_VALUE 0x0085 544#define ACB_CMD_INIT_TX_RX 0x0086 545#define ACB_CMD_INIT_TRC_TIMERS 0x0006 546#define ACB_CMD_READ_TRC_STATUS 0x0007 547#define ACB_CMD_CHANGE_JOIN_STATE 0x0008 548#define ACB_CMD_RESERVED_9 0x0009 549#define ACB_CMD_RESERVED_A 0x000A 550#define ACB_CMD_RESERVED_B 0x000B 551#define ACB_CMD_RESERVED_C 0x000C 552#define ACB_CMD_RESERVED_D 0x000D 553#define ACB_CMD_RESERVED_E 0x000E 554#define ACB_CMD_RESERVED_F 0x000F 555 556#define TRC_MAC_REGISTERS_TEST 0x0000 557#define TRC_INTERNAL_LOOPBACK 0x0001 558#define TRC_TRI_LOOPBACK 0x0002 559#define TRC_INTERNAL_ROM_TEST 0x0003 560#define TRC_LOBE_MEDIA_TEST 0x0004 561#define TRC_ANALOG_TEST 0x0005 562#define TRC_HOST_INTERFACE_REG_TEST 0x0003 563 564#define TEST_DMA_1 0x0000 565#define TEST_DMA_2 0x0001 566#define TEST_MCT_ROM 0x0002 567#define HIC_INTERNAL_DIAG 0x0003 568 569#define ABORT_TRANSMIT_PRIORITY_0 0x0001 570#define ABORT_TRANSMIT_PRIORITY_1 0x0002 571#define ABORT_TRANSMIT_PRIORITY_2 0x0004 572#define ABORT_TRANSMIT_PRIORITY_3 0x0008 573#define ABORT_TRANSMIT_PRIORITY_4 0x0010 574#define ABORT_TRANSMIT_PRIORITY_5 0x0020 575#define ABORT_TRANSMIT_PRIORITY_6 0x0040 576#define ABORT_TRANSMIT_PRIORITY_7 0x0080 577 578#define TX_PENDING_PRIORITY_0 0x0001 579#define TX_PENDING_PRIORITY_1 0x0002 580#define TX_PENDING_PRIORITY_2 0x0004 581#define TX_PENDING_PRIORITY_3 0x0008 582#define TX_PENDING_PRIORITY_4 0x0010 583#define TX_PENDING_PRIORITY_5 0x0020 584#define TX_PENDING_PRIORITY_6 0x0040 585#define TX_PENDING_PRIORITY_7 0x0080 586 587#define FCB_FRAME_LENGTH 0x100 588#define FCB_COMMAND_DONE 0x8000 /* FCB Word 0 */ 589#define FCB_NOT_CHAIN_END 0x0000 /* FCB Word 1 */ 590#define FCB_CHAIN_END 0x8000 591#define FCB_NO_WARNING 0x0000 592#define FCB_WARNING 0x4000 593#define FCB_INTERRUPT_DISABLE 0x0000 594#define FCB_INTERRUPT_ENABLE 0x2000 595 596#define FCB_ENABLE_IMA 0x0008 597#define FCB_ENABLE_TES 0x0004 /* Guarantee Tx before Int */ 598#define FCB_ENABLE_TFS 0x0002 /* Post Tx Frame Status */ 599#define FCB_ENABLE_NTC 0x0001 /* No Tx CRC */ 600 601#define FCB_TX_STATUS_CR2 0x0004 602#define FCB_TX_STATUS_AR2 0x0008 603#define FCB_TX_STATUS_CR1 0x0040 604#define FCB_TX_STATUS_AR1 0x0080 605#define FCB_TX_AC_BITS (FCB_TX_STATUS_AR1+FCB_TX_STATUS_AR2+FCB_TX_STATUS_CR1+FCB_TX_STATUS_CR2) 606#define FCB_TX_STATUS_E 0x0100 607 608#define FCB_RX_STATUS_ANY_ERROR 0x0001 609#define FCB_RX_STATUS_FCS_ERROR 0x0002 610 611#define FCB_RX_STATUS_IA_MATCHED 0x0400 612#define FCB_RX_STATUS_IGA_BSGA_MATCHED 0x0500 613#define FCB_RX_STATUS_FA_MATCHED 0x0600 614#define FCB_RX_STATUS_BA_MATCHED 0x0700 615#define FCB_RX_STATUS_DA_MATCHED 0x0400 616#define FCB_RX_STATUS_SOURCE_ROUTING 0x0800 617 618#define BDB_BUFFER_SIZE 0x100 619#define BDB_NOT_CHAIN_END 0x0000 620#define BDB_CHAIN_END 0x8000 621#define BDB_NO_WARNING 0x0000 622#define BDB_WARNING 0x4000 623 624#define ERROR_COUNTERS_CHANGED 0x0001 625#define TI_NDIS_RING_STATUS_CHANGED 0x0002 626#define UNA_CHANGED 0x0004 627#define READY_TO_SEND_RQ_INIT 0x0008 628 629#define SCGB_ADDRESS_POINTER_FORMAT INTEL_ADDRESS_POINTER_FORMAT 630#define SCGB_DATA_FORMAT INTEL_DATA_FORMAT 631#define SCGB_MULTI_WORD_CONTROL 0 632#define SCGB_BURST_LENGTH 0x000E /* DMA Burst Length */ 633 634#define SCGB_CONFIG (INTEL_ADDRESS_POINTER_FORMAT+INTEL_DATA_FORMAT+SCGB_BURST_LENGTH) 635 636#define ISCP_BLOCK_SIZE 0x0A 637#define RAM_SIZE 0x10000 638#define INIT_SYS_CONFIG_PTR_OFFSET (RAM_SIZE-ISCP_BLOCK_SIZE) 639#define SCGP_BLOCK_OFFSET 0 640 641#define SCLB_NOT_VALID 0x0000 /* Initially, SCLB not valid */ 642#define SCLB_VALID 0x8000 /* Host tells TRC SCLB valid */ 643#define SCLB_PROCESSED 0x0000 /* TRC says SCLB processed */ 644#define SCLB_RESUME_CONTROL_NOT_VALID 0x0000 /* Initially, RC not valid */ 645#define SCLB_RESUME_CONTROL_VALID 0x4000 /* Host tells TRC RC valid */ 646#define SCLB_IACK_CODE_NOT_VALID 0x0000 /* Initially, IACK not valid */ 647#define SCLB_IACK_CODE_VALID 0x2000 /* Host tells TRC IACK valid */ 648#define SCLB_CMD_NOP 0x0000 649#define SCLB_CMD_REMOVE 0x0001 650#define SCLB_CMD_SUSPEND_ACB_CHAIN 0x0002 651#define SCLB_CMD_SET_INTERRUPT_MASK 0x0003 652#define SCLB_CMD_CLEAR_INTERRUPT_MASK 0x0004 653#define SCLB_CMD_RESERVED_5 0x0005 654#define SCLB_CMD_RESERVED_6 0x0006 655#define SCLB_CMD_RESERVED_7 0x0007 656#define SCLB_CMD_RESERVED_8 0x0008 657#define SCLB_CMD_RESERVED_9 0x0009 658#define SCLB_CMD_RESERVED_A 0x000A 659#define SCLB_CMD_RESERVED_B 0x000B 660#define SCLB_CMD_RESERVED_C 0x000C 661#define SCLB_CMD_RESERVED_D 0x000D 662#define SCLB_CMD_RESERVED_E 0x000E 663#define SCLB_CMD_RESERVED_F 0x000F 664 665#define SCLB_RC_ACB 0x0001 /* Action Command Block Chain */ 666#define SCLB_RC_RES0 0x0002 /* Always Zero */ 667#define SCLB_RC_RES1 0x0004 /* Always Zero */ 668#define SCLB_RC_RES2 0x0008 /* Always Zero */ 669#define SCLB_RC_RX_MAC_FCB 0x0010 /* RX_MAC_FCB Chain */ 670#define SCLB_RC_RX_MAC_BDB 0x0020 /* RX_MAC_BDB Chain */ 671#define SCLB_RC_RX_NON_MAC_FCB 0x0040 /* RX_NON_MAC_FCB Chain */ 672#define SCLB_RC_RX_NON_MAC_BDB 0x0080 /* RX_NON_MAC_BDB Chain */ 673#define SCLB_RC_TFCB0 0x0100 /* TX Priority 0 FCB Chain */ 674#define SCLB_RC_TFCB1 0x0200 /* TX Priority 1 FCB Chain */ 675#define SCLB_RC_TFCB2 0x0400 /* TX Priority 2 FCB Chain */ 676#define SCLB_RC_TFCB3 0x0800 /* TX Priority 3 FCB Chain */ 677#define SCLB_RC_TFCB4 0x1000 /* TX Priority 4 FCB Chain */ 678#define SCLB_RC_TFCB5 0x2000 /* TX Priority 5 FCB Chain */ 679#define SCLB_RC_TFCB6 0x4000 /* TX Priority 6 FCB Chain */ 680#define SCLB_RC_TFCB7 0x8000 /* TX Priority 7 FCB Chain */ 681 682#define SCLB_IMC_RES0 0x0001 /* */ 683#define SCLB_IMC_MAC_TYPE_3 0x0002 /* MAC_ARC_INDICATE */ 684#define SCLB_IMC_MAC_ERROR_COUNTERS 0x0004 /* */ 685#define SCLB_IMC_RES1 0x0008 /* */ 686#define SCLB_IMC_MAC_TYPE_2 0x0010 /* QUE_MAC_INDICATE */ 687#define SCLB_IMC_TX_FRAME 0x0020 /* */ 688#define SCLB_IMC_END_OF_TX_QUEUE 0x0040 /* */ 689#define SCLB_IMC_NON_MAC_RX_RESOURCE 0x0080 /* */ 690#define SCLB_IMC_MAC_RX_RESOURCE 0x0100 /* */ 691#define SCLB_IMC_NON_MAC_RX_FRAME 0x0200 /* */ 692#define SCLB_IMC_MAC_RX_FRAME 0x0400 /* */ 693#define SCLB_IMC_TRC_FIFO_STATUS 0x0800 /* */ 694#define SCLB_IMC_COMMAND_STATUS 0x1000 /* */ 695#define SCLB_IMC_MAC_TYPE_1 0x2000 /* Self Removed */ 696#define SCLB_IMC_TRC_INTRNL_TST_STATUS 0x4000 /* */ 697#define SCLB_IMC_RES2 0x8000 /* */ 698 699#define DMA_TRIGGER 0x0004 700#define FREQ_16MB_BIT 0x0010 701#define THDREN 0x0020 702#define CFG0_RSV1 0x0040 703#define CFG0_RSV2 0x0080 704#define ETREN 0x0100 705#define RX_OWN_BIT 0x0200 706#define RXATMAC 0x0400 707#define PROMISCUOUS_BIT 0x0800 708#define USETPT 0x1000 709#define SAVBAD_BIT 0x2000 710#define ONEQUE 0x4000 711#define NO_AUTOREMOVE 0x8000 712 713#define RX_FCB_AREA_8316 0x00000000 714#define RX_BUFF_AREA_8316 0x00000000 715 716#define TRC_POINTER(X) ((unsigned long)(X) - tp->ram_access) 717#define RX_FCB_TRC_POINTER(X) ((unsigned long)(X) - tp->ram_access + RX_FCB_AREA_8316) 718#define RX_BUFF_TRC_POINTER(X) ((unsigned long)(X) - tp->ram_access + RX_BUFF_AREA_8316) 719 720// Offset 0: MSR - Memory Select Register 721// 722#define r587_MSR 0x000 // Register Offset 723//#define MSR_RST 0x080 // LAN Controller Reset 724#define MSR_MENB 0x040 // Shared Memory Enable 725#define MSR_RA18 0x020 // Ram Address bit 18 (583, 584, 587) 726#define MSR_RA17 0x010 // Ram Address bit 17 (583, 584, 585/790) 727#define MSR_RA16 0x008 // Ram Address bit 16 (583, 584, 585/790) 728#define MSR_RA15 0x004 // Ram Address bit 15 (583, 584, 585/790) 729#define MSR_RA14 0x002 // Ram Address bit 14 (583, 584, 585/790) 730#define MSR_RA13 0x001 // Ram Address bit 13 (583, 584, 585/790) 731 732#define MSR_MASK 0x03F // Mask for Address bits RA18-RA13 (583, 584, 587) 733 734#define MSR 0x00 735#define IRR 0x04 736#define HWR 0x04 737#define LAAR 0x05 738#define IMCCR 0x05 739#define LAR0 0x08 740#define BDID 0x0E // Adapter ID byte register offset 741#define CSR 0x10 742#define PR 0x11 743 744#define MSR_RST 0x80 745#define MSR_MEMB 0x40 746#define MSR_0WS 0x20 747 748#define FORCED_16BIT_MODE 0x0002 749 750#define INTERFRAME_SPACING_16 0x0003 /* 6 bytes */ 751#define INTERFRAME_SPACING_4 0x0001 /* 2 bytes */ 752#define MULTICAST_ADDRESS_BIT 0x0010 753#define NON_SRC_ROUTING_BIT 0x0020 754 755#define LOOPING_MODE_MASK 0x0007 756 757/* 758 * Decode firmware defines. 759 */ 760#define SWAP_BYTES(X) ((X & 0xff) << 8) | (X >> 8) 761#define WEIGHT_OFFSET 5 762#define TREE_SIZE_OFFSET 9 763#define TREE_OFFSET 11 764 765/* The Huffman Encoding Tree is constructed of these nodes. */ 766typedef struct { 767 __u8 llink; /* Short version of above node. */ 768 __u8 tag; 769 __u8 info; /* This node is used on decodes. */ 770 __u8 rlink; 771} DECODE_TREE_NODE; 772 773#define ROOT 0 /* Branch value. */ 774#define LEAF 0 /* Tag field value. */ 775#define BRANCH 1 /* Tag field value. */ 776 777/* 778 * Multicast Table Structure 779 */ 780typedef struct { 781 __u8 address[6]; 782 __u8 instance_count; 783} McTable; 784 785/* 786 * Fragment Descriptor Definition 787 */ 788typedef struct { 789 __u8 *fragment_ptr; 790 __u32 fragment_length; 791} FragmentStructure; 792 793/* 794 * Data Buffer Structure Definition 795 */ 796typedef struct { 797 __u32 fragment_count; 798 FragmentStructure fragment_list[MAXFRAGMENTS]; 799} DataBufferStructure; 800 801#pragma pack(1) 802typedef struct { 803 __u8 IType; 804 __u8 ISubtype; 805} Interrupt_Status_Word; 806 807#pragma pack(1) 808typedef struct BDBlockType { 809 __u16 info; /* 02 */ 810 __u32 trc_next_ptr; /* 06 */ 811 __u32 trc_data_block_ptr; /* 10 */ 812 __u16 buffer_length; /* 12 */ 813 814 __u16 *data_block_ptr; /* 16 */ 815 struct BDBlockType *next_ptr; /* 20 */ 816 struct BDBlockType *back_ptr; /* 24 */ 817 __u8 filler[8]; /* 32 */ 818} BDBlock; 819 820#pragma pack(1) 821typedef struct FCBlockType { 822 __u16 frame_status; /* 02 */ 823 __u16 info; /* 04 */ 824 __u32 trc_next_ptr; /* 08 */ 825 __u32 trc_bdb_ptr; /* 12 */ 826 __u16 frame_length; /* 14 */ 827 828 BDBlock *bdb_ptr; /* 18 */ 829 struct FCBlockType *next_ptr; /* 22 */ 830 struct FCBlockType *back_ptr; /* 26 */ 831 __u16 memory_alloc; /* 28 */ 832 __u8 filler[4]; /* 32 */ 833 834} FCBlock; 835 836#pragma pack(1) 837typedef struct SBlockType{ 838 __u8 Internal_Error_Count; 839 __u8 Line_Error_Count; 840 __u8 AC_Error_Count; 841 __u8 Burst_Error_Count; 842 __u8 RESERVED_COUNTER_0; 843 __u8 AD_TRANS_Count; 844 __u8 RCV_Congestion_Count; 845 __u8 Lost_FR_Error_Count; 846 __u8 FREQ_Error_Count; 847 __u8 FR_Copied_Error_Count; 848 __u8 RESERVED_COUNTER_1; 849 __u8 Token_Error_Count; 850 851 __u16 TI_NDIS_Ring_Status; 852 __u16 BCN_Type; 853 __u16 Error_Code; 854 __u16 SA_of_Last_AMP_SMP[3]; 855 __u16 UNA[3]; 856 __u16 Ucode_Version_Number; 857 __u16 Status_CHG_Indicate; 858 __u16 RESERVED_STATUS_0; 859} SBlock; 860 861#pragma pack(1) 862typedef struct ACBlockType { 863 __u16 cmd_done_status; /* 02 */ 864 __u16 cmd_info; /* 04 */ 865 __u32 trc_next_ptr; /* 08 */ 866 __u16 cmd; /* 10 */ 867 __u16 subcmd; /* 12 */ 868 __u16 data_offset_lo; /* 14 */ 869 __u16 data_offset_hi; /* 16 */ 870 871 struct ACBlockType *next_ptr; /* 20 */ 872 873 __u8 filler[12]; /* 32 */ 874} ACBlock; 875 876#define NUM_OF_INTERRUPTS 0x20 877 878#pragma pack(1) 879typedef struct { 880 Interrupt_Status_Word IStatus[NUM_OF_INTERRUPTS]; 881} ISBlock; 882 883#pragma pack(1) 884typedef struct { 885 __u16 valid_command; /* 02 */ 886 __u16 iack_code; /* 04 */ 887 __u16 resume_control; /* 06 */ 888 __u16 int_mask_control; /* 08 */ 889 __u16 int_mask_state; /* 10 */ 890 891 __u8 filler[6]; /* 16 */ 892} SCLBlock; 893 894#pragma pack(1) 895typedef struct 896{ 897 __u16 config; /* 02 */ 898 __u32 trc_sclb_ptr; /* 06 */ 899 __u32 trc_acb_ptr; /* 10 */ 900 __u32 trc_isb_ptr; /* 14 */ 901 __u16 isbsiz; /* 16 */ 902 903 SCLBlock *sclb_ptr; /* 20 */ 904 ACBlock *acb_ptr; /* 24 */ 905 ISBlock *isb_ptr; /* 28 */ 906 907 __u16 Non_Mac_Rx_Bdbs; /* 30 DEBUG */ 908 __u8 filler[2]; /* 32 */ 909 910} SCGBlock; 911 912#pragma pack(1) 913typedef struct 914{ 915 __u32 trc_scgb_ptr; 916 SCGBlock *scgb_ptr; 917} ISCPBlock; 918#pragma pack() 919 920typedef struct net_local { 921 ISCPBlock *iscpb_ptr; 922 SCGBlock *scgb_ptr; 923 SCLBlock *sclb_ptr; 924 ISBlock *isb_ptr; 925 926 ACBlock *acb_head; 927 ACBlock *acb_curr; 928 ACBlock *acb_next; 929 930 __u8 adapter_name[12]; 931 932 __u16 num_rx_bdbs [NUM_RX_QS_USED]; 933 __u16 num_rx_fcbs [NUM_RX_QS_USED]; 934 935 __u16 num_tx_bdbs [NUM_TX_QS_USED]; 936 __u16 num_tx_fcbs [NUM_TX_QS_USED]; 937 938 __u16 num_of_tx_buffs; 939 940 __u16 tx_buff_size [NUM_TX_QS_USED]; 941 __u16 tx_buff_used [NUM_TX_QS_USED]; 942 __u16 tx_queue_status [NUM_TX_QS_USED]; 943 944 FCBlock *tx_fcb_head[NUM_TX_QS_USED]; 945 FCBlock *tx_fcb_curr[NUM_TX_QS_USED]; 946 FCBlock *tx_fcb_end[NUM_TX_QS_USED]; 947 BDBlock *tx_bdb_head[NUM_TX_QS_USED]; 948 __u16 *tx_buff_head[NUM_TX_QS_USED]; 949 __u16 *tx_buff_end[NUM_TX_QS_USED]; 950 __u16 *tx_buff_curr[NUM_TX_QS_USED]; 951 __u16 num_tx_fcbs_used[NUM_TX_QS_USED]; 952 953 FCBlock *rx_fcb_head[NUM_RX_QS_USED]; 954 FCBlock *rx_fcb_curr[NUM_RX_QS_USED]; 955 BDBlock *rx_bdb_head[NUM_RX_QS_USED]; 956 BDBlock *rx_bdb_curr[NUM_RX_QS_USED]; 957 BDBlock *rx_bdb_end[NUM_RX_QS_USED]; 958 __u16 *rx_buff_head[NUM_RX_QS_USED]; 959 __u16 *rx_buff_end[NUM_RX_QS_USED]; 960 961 __u32 *ptr_local_ring_num; 962 963 __u32 sh_mem_used; 964 965 __u16 page_offset_mask; 966 967 __u16 authorized_function_classes; 968 __u16 authorized_access_priority; 969 970 __u16 num_acbs; 971 __u16 num_acbs_used; 972 __u16 acb_pending; 973 974 __u16 current_isb_index; 975 976 __u8 monitor_state; 977 __u8 monitor_state_ready; 978 __u16 ring_status; 979 __u8 ring_status_flags; 980 __u8 state; 981 982 __u8 join_state; 983 984 __u8 slot_num; 985 __u16 pos_id; 986 987 __u32 *ptr_una; 988 __u32 *ptr_bcn_type; 989 __u32 *ptr_tx_fifo_underruns; 990 __u32 *ptr_rx_fifo_underruns; 991 __u32 *ptr_rx_fifo_overruns; 992 __u32 *ptr_tx_fifo_overruns; 993 __u32 *ptr_tx_fcb_overruns; 994 __u32 *ptr_rx_fcb_overruns; 995 __u32 *ptr_tx_bdb_overruns; 996 __u32 *ptr_rx_bdb_overruns; 997 998 __u16 receive_queue_number; 999 1000 __u8 rx_fifo_overrun_count;
1001 __u8 tx_fifo_overrun_count; 1002 1003 __u16 adapter_flags; 1004 __u16 adapter_flags1; 1005 __u16 *misc_command_data; 1006 __u16 max_packet_size; 1007 1008 __u16 config_word0; 1009 __u16 config_word1; 1010 1011 __u8 trc_mask; 1012 1013 __u16 source_ring_number; 1014 __u16 target_ring_number; 1015 1016 __u16 microcode_version; 1017 1018 __u16 bic_type; 1019 __u16 nic_type; 1020 __u16 board_id; 1021 1022 __u16 rom_size; 1023 __u32 rom_base; 1024 __u16 ram_size; 1025 __u16 ram_usable; 1026 __u32 ram_base; 1027 __u32 ram_access; 1028 1029 __u16 extra_info; 1030 __u16 mode_bits; 1031 __u16 media_menu; 1032 __u16 media_type; 1033 __u16 adapter_bus; 1034 1035 __u16 status; 1036 __u16 receive_mask; 1037 1038 __u16 group_address_0; 1039 __u16 group_address[2]; 1040 __u16 functional_address_0; 1041 __u16 functional_address[2]; 1042 __u16 bitwise_group_address[2]; 1043 1044 __u8 cleanup; 1045 1046 struct sk_buff_head SendSkbQueue; 1047 __u16 QueueSkb; 1048 1049 struct tr_statistics MacStat; /* MAC statistics structure */ 1050 1051 spinlock_t lock; 1052} NET_LOCAL; 1053 1054/************************************ 1055 * SNMP-ON-BOARD Agent Link Structure 1056 ************************************/ 1057 1058typedef struct { 1059 __u8 LnkSigStr[12]; /* signature string "SmcLinkTable" */ 1060 __u8 LnkDrvTyp; /* 1=Redbox ODI, 2=ODI DOS, 3=ODI OS/2, 4=NDIS DOS */ 1061 __u8 LnkFlg; /* 0 if no agent linked, 1 if agent linked */ 1062 void *LnkNfo; /* routine which returns pointer to NIC info */ 1063 void *LnkAgtRcv; /* pointer to agent receive trap entry */ 1064 void *LnkAgtXmt; /* pointer to agent transmit trap 1065entry */ 1066void *LnkGet; /* pointer to NIC receive data 1067copy routine */ 1068 void *LnkSnd; /* pointer to NIC send routine 1069*/ 1070 void *LnkRst; /* pointer to NIC driver reset 1071routine */ 1072 void *LnkMib; /* pointer to MIB data base */ 1073 void *LnkMibAct; /* pointer to MIB action routine list */ 1074 __u16 LnkCntOffset; /* offset to error counters */ 1075 __u16 LnkCntNum; /* number of error counters */ 1076 __u16 LnkCntSize; /* size of error counters i.e. 32 = 32 bits */ 1077 void *LnkISR; /* pointer to interrupt vector */ 1078 __u8 LnkFrmTyp; /* 1=Ethernet, 2=Token Ring */ 1079 __u8 LnkDrvVer1 ; /* driver major version */ 1080 __u8 LnkDrvVer2 ; /* driver minor version */ 1081} AgentLink; 1082 1083/* 1084 * Definitions for pcm_card_flags(bit_mapped) 1085 */ 1086#define REG_COMPLETE 0x0001 1087#define INSERTED 0x0002 1088#define PCC_INSERTED 0x0004 /* 1=currently inserted, 0=cur removed */ 1089 1090/* 1091 * Adapter RAM test patterns 1092 */ 1093#define RAM_PATTERN_1 0x55AA 1094#define RAM_PATTERN_2 0x9249 1095#define RAM_PATTERN_3 0xDB6D 1096 1097/* 1098 * definitions for RAM test 1099 */ 1100#define ROM_SIGNATURE 0xAA55 1101#define MIN_ROM_SIZE 0x2000 1102 1103/* 1104 * Return Codes 1105 */ 1106#define SUCCESS 0x0000 1107#define ADAPTER_AND_CONFIG 0x0001 1108#define ADAPTER_NO_CONFIG 0x0002 1109#define NOT_MY_INTERRUPT 0x0003 1110#define FRAME_REJECTED 0x0004 1111#define EVENTS_DISABLED 0x0005 1112#define OUT_OF_RESOURCES 0x0006 1113#define INVALID_PARAMETER 0x0007 1114#define INVALID_FUNCTION 0x0008 1115#define INITIALIZE_FAILED 0x0009 1116#define CLOSE_FAILED 0x000A 1117#define MAX_COLLISIONS 0x000B 1118#define NO_SUCH_DESTINATION 0x000C 1119#define BUFFER_TOO_SMALL_ERROR 0x000D 1120#define ADAPTER_CLOSED 0x000E 1121#define UCODE_NOT_PRESENT 0x000F 1122#define FIFO_UNDERRUN 0x0010 1123#define DEST_OUT_OF_RESOURCES 0x0011 1124#define ADAPTER_NOT_INITIALIZED 0x0012 1125#define PENDING 0x0013 1126#define UCODE_PRESENT 0x0014 1127#define NOT_INIT_BY_BRIDGE 0x0015 1128 1129#define OPEN_FAILED 0x0080 1130#define HARDWARE_FAILED 0x0081 1131#define SELF_TEST_FAILED 0x0082 1132#define RAM_TEST_FAILED 0x0083 1133#define RAM_CONFLICT 0x0084 1134#define ROM_CONFLICT 0x0085 1135#define UNKNOWN_ADAPTER 0x0086 1136#define CONFIG_ERROR 0x0087 1137#define CONFIG_WARNING 0x0088 1138#define NO_FIXED_CNFG 0x0089 1139#define EEROM_CKSUM_ERROR 0x008A 1140#define ROM_SIGNATURE_ERROR 0x008B 1141#define ROM_CHECKSUM_ERROR 0x008C 1142#define ROM_SIZE_ERROR 0x008D 1143#define UNSUPPORTED_NIC_CHIP 0x008E 1144#define NIC_REG_ERROR 0x008F 1145#define BIC_REG_ERROR 0x0090 1146#define MICROCODE_TEST_ERROR 0x0091 1147#define LOBE_MEDIA_TEST_FAILED 0x0092 1148 1149#define ADAPTER_FOUND_LAN_CORRUPT 0x009B 1150 1151#define ADAPTER_NOT_FOUND 0xFFFF 1152 1153#define ILLEGAL_FUNCTION INVALID_FUNCTION 1154 1155/* Errors */ 1156#define IO_BASE_INVALID 0x0001 1157#define IO_BASE_RANGE 0x0002 1158#define IRQ_INVALID 0x0004 1159#define IRQ_RANGE 0x0008 1160#define RAM_BASE_INVALID 0x0010 1161#define RAM_BASE_RANGE 0x0020 1162#define RAM_SIZE_RANGE 0x0040 1163#define MEDIA_INVALID 0x0800 1164 1165/* Warnings */ 1166#define IRQ_MISMATCH 0x0080 1167#define RAM_BASE_MISMATCH 0x0100 1168#define RAM_SIZE_MISMATCH 0x0200 1169#define BUS_MODE_MISMATCH 0x0400 1170 1171#define RX_CRC_ERROR 0x01 1172#define RX_ALIGNMENT_ERROR 0x02 1173#define RX_HW_FAILED 0x80 1174 1175/* 1176 * Definitions for the field RING_STATUS_FLAGS 1177 */ 1178#define RING_STATUS_CHANGED 0X01 1179#define MONITOR_STATE_CHANGED 0X02 1180#define JOIN_STATE_CHANGED 0X04 1181 1182/* 1183 * Definitions for the field JOIN_STATE 1184 */ 1185#define JS_BYPASS_STATE 0x00 1186#define JS_LOBE_TEST_STATE 0x01 1187#define JS_DETECT_MONITOR_PRESENT_STATE 0x02 1188#define JS_AWAIT_NEW_MONITOR_STATE 0x03 1189#define JS_DUPLICATE_ADDRESS_TEST_STATE 0x04 1190#define JS_NEIGHBOR_NOTIFICATION_STATE 0x05 1191#define JS_REQUEST_INITIALIZATION_STATE 0x06 1192#define JS_JOIN_COMPLETE_STATE 0x07 1193#define JS_BYPASS_WAIT_STATE 0x08 1194 1195/* 1196 * Definitions for the field MONITOR_STATE 1197 */ 1198#define MS_MONITOR_FSM_INACTIVE 0x00 1199#define MS_REPEAT_BEACON_STATE 0x01 1200#define MS_REPEAT_CLAIM_TOKEN_STATE 0x02 1201#define MS_TRANSMIT_CLAIM_TOKEN_STATE 0x03 1202#define MS_STANDBY_MONITOR_STATE 0x04 1203#define MS_TRANSMIT_BEACON_STATE 0x05 1204#define MS_ACTIVE_MONITOR_STATE 0x06 1205#define MS_TRANSMIT_RING_PURGE_STATE 0x07 1206#define MS_BEACON_TEST_STATE 0x09 1207 1208/* 1209 * Definitions for the bit-field RING_STATUS 1210 */ 1211#define SIGNAL_LOSS 0x8000 1212#define HARD_ERROR 0x4000 1213#define SOFT_ERROR 0x2000 1214#define TRANSMIT_BEACON 0x1000 1215#define LOBE_WIRE_FAULT 0x0800 1216#define AUTO_REMOVAL_ERROR 0x0400 1217#define REMOVE_RECEIVED 0x0100 1218#define COUNTER_OVERFLOW 0x0080 1219#define SINGLE_STATION 0x0040 1220#define RING_RECOVERY 0x0020 1221 1222/* 1223 * Definitions for the field BUS_TYPE 1224 */ 1225#define AT_BUS 0x00 1226#define MCA_BUS 0x01 1227#define EISA_BUS 0x02 1228#define PCI_BUS 0x03 1229#define PCMCIA_BUS 0x04 1230 1231/* 1232 * Definitions for adapter_flags 1233 */ 1234#define RX_VALID_LOOKAHEAD 0x0001 1235#define FORCED_16BIT_MODE 0x0002 1236#define ADAPTER_DISABLED 0x0004 1237#define TRANSMIT_CHAIN_INT 0x0008 1238#define EARLY_RX_FRAME 0x0010 1239#define EARLY_TX 0x0020 1240#define EARLY_RX_COPY 0x0040 1241#define USES_PHYSICAL_ADDR 0x0080 /* Rsvd for DEC PCI and 9232 */ 1242#define NEEDS_PHYSICAL_ADDR 0x0100 /* Reserved*/ 1243#define RX_STATUS_PENDING 0x0200 1244#define ERX_DISABLED 0x0400 /* EARLY_RX_ENABLE rcv_mask */ 1245#define ENABLE_TX_PENDING 0x0800 1246#define ENABLE_RX_PENDING 0x1000 1247#define PERM_CLOSE 0x2000 1248#define IO_MAPPED 0x4000 /* IOmapped bus interface 795 */ 1249#define ETX_DISABLED 0x8000 1250 1251 1252/* 1253 * Definitions for adapter_flags1 1254 */ 1255#define TX_PHY_RX_VIRT 0x0001 1256#define NEEDS_HOST_RAM 0x0002 1257#define NEEDS_MEDIA_TYPE 0x0004 1258#define EARLY_RX_DONE 0x0008 1259#define PNP_BOOT_BIT 0x0010 /* activates PnP & config on power-up */ 1260 /* clear => regular PnP operation */ 1261#define PNP_ENABLE 0x0020 /* regular PnP operation clear => */ 1262 /* no PnP, overrides PNP_BOOT_BIT */ 1263#define SATURN_ENABLE 0x0040 1264 1265#define ADAPTER_REMOVABLE 0x0080 /* adapter is hot swappable */ 1266#define TX_PHY 0x0100 /* Uses physical address for tx bufs */ 1267#define RX_PHY 0x0200 /* Uses physical address for rx bufs */ 1268#define TX_VIRT 0x0400 /* Uses virtual addr for tx bufs */ 1269#define RX_VIRT 0x0800 1270#define NEEDS_SERVICE 0x1000 1271 1272/* 1273 * Adapter Status Codes 1274 */ 1275#define OPEN 0x0001 1276#define INITIALIZED 0x0002 1277#define CLOSED 0x0003 1278#define FAILED 0x0005 1279#define NOT_INITIALIZED 0x0006 1280#define IO_CONFLICT 0x0007 1281#define CARD_REMOVED 0x0008 1282#define CARD_INSERTED 0x0009 1283 1284/* 1285 * Mode Bit Definitions 1286 */ 1287#define INTERRUPT_STATUS_BIT 0x8000 /* PC Interrupt Line: 0 = Not Enabled */ 1288#define BOOT_STATUS_MASK 0x6000 /* Mask to isolate BOOT_STATUS */ 1289#define BOOT_INHIBIT 0x0000 /* BOOT_STATUS is 'inhibited' */ 1290#define BOOT_TYPE_1 0x2000 /* Unused BOOT_STATUS value */ 1291#define BOOT_TYPE_2 0x4000 /* Unused BOOT_STATUS value */ 1292#define BOOT_TYPE_3 0x6000 /* Unused BOOT_STATUS value */ 1293#define ZERO_WAIT_STATE_MASK 0x1800 /* Mask to isolate Wait State flags */ 1294#define ZERO_WAIT_STATE_8_BIT 0x1000 /* 0 = Disabled (Inserts Wait States) */ 1295#define ZERO_WAIT_STATE_16_BIT 0x0800 /* 0 = Disabled (Inserts Wait States) */ 1296#define LOOPING_MODE_MASK 0x0007 1297#define LOOPBACK_MODE_0 0x0000 1298#define LOOPBACK_MODE_1 0x0001 1299#define LOOPBACK_MODE_2 0x0002 1300#define LOOPBACK_MODE_3 0x0003 1301#define LOOPBACK_MODE_4 0x0004 1302#define LOOPBACK_MODE_5 0x0005 1303#define LOOPBACK_MODE_6 0x0006 1304#define LOOPBACK_MODE_7 0x0007 1305#define AUTO_MEDIA_DETECT 0x0008 1306#define MANUAL_CRC 0x0010 1307#define EARLY_TOKEN_REL 0x0020 /* Early Token Release for Token Ring */ 1308#define UMAC 0x0040 1309#define UTP2_PORT 0x0080 /* For 8216T2, 0=port A, 1=Port B. */ 1310#define BNC_10BT_INTERFACE 0x0600 /* BNC and UTP current media set */ 1311#define UTP_INTERFACE 0x0500 /* Ethernet UTP Only. */ 1312#define BNC_INTERFACE 0x0400 1313#define AUI_INTERFACE 0x0300 1314#define AUI_10BT_INTERFACE 0x0200 1315#define STARLAN_10_INTERFACE 0x0100 1316#define INTERFACE_TYPE_MASK 0x0700 1317 1318/* 1319 * Media Type Bit Definitions 1320 * 1321 * legend: TP = Twisted Pair 1322 * STP = Shielded twisted pair 1323 * UTP = Unshielded twisted pair 1324 */ 1325 1326#define CNFG_MEDIA_TYPE_MASK 0x001e /* POS Register 3 Mask */ 1327 1328#define MEDIA_S10 0x0000 /* Ethernet adapter, TP. */ 1329#define MEDIA_AUI_UTP 0x0001 /* Ethernet adapter, AUI/UTP media */ 1330#define MEDIA_BNC 0x0002 /* Ethernet adapter, BNC media. */ 1331#define MEDIA_AUI 0x0003 /* Ethernet Adapter, AUI media. */ 1332#define MEDIA_STP_16 0x0004 /* TokenRing adap, 16Mbit STP. */ 1333#define MEDIA_STP_4 0x0005 /* TokenRing adap, 4Mbit STP. */ 1334#define MEDIA_UTP_16 0x0006 /* TokenRing adap, 16Mbit UTP. */ 1335#define MEDIA_UTP_4 0x0007 /* TokenRing adap, 4Mbit UTP. */ 1336#define MEDIA_UTP 0x0008 /* Ethernet adapter, UTP media (no AUI) 1337*/ 1338#define MEDIA_BNC_UTP 0x0010 /* Ethernet adapter, BNC/UTP media */ 1339#define MEDIA_UTPFD 0x0011 /* Ethernet adapter, TP full duplex */ 1340#define MEDIA_UTPNL 0x0012 /* Ethernet adapter, TP with link integrity test disabled */ 1341#define MEDIA_AUI_BNC 0x0013 /* Ethernet adapter, AUI/BNC media */ 1342#define MEDIA_AUI_BNC_UTP 0x0014 /* Ethernet adapter, AUI_BNC/UTP */ 1343#define MEDIA_UTPA 0x0015 /* Ethernet UTP-10Mbps Ports A */ 1344#define MEDIA_UTPB 0x0016 /* Ethernet UTP-10Mbps Ports B */ 1345#define MEDIA_STP_16_UTP_16 0x0017 /* Token Ring STP-16Mbps/UTP-16Mbps */ 1346#define MEDIA_STP_4_UTP_4 0x0018 /* Token Ring STP-4Mbps/UTP-4Mbps */ 1347 1348#define MEDIA_STP100_UTP100 0x0020 /* Ethernet STP-100Mbps/UTP-100Mbps */ 1349#define MEDIA_UTP100FD 0x0021 /* Ethernet UTP-100Mbps, full duplex */ 1350#define MEDIA_UTP100 0x0022 /* Ethernet UTP-100Mbps */ 1351 1352 1353#define MEDIA_UNKNOWN 0xFFFF /* Unknown adapter/media type */ 1354 1355/* 1356 * Definitions for the field: 1357 * media_type2 1358 */ 1359#define MEDIA_TYPE_MII 0x0001 1360#define MEDIA_TYPE_UTP 0x0002 1361#define MEDIA_TYPE_BNC 0x0004 1362#define MEDIA_TYPE_AUI 0x0008 1363#define MEDIA_TYPE_S10 0x0010 1364#define MEDIA_TYPE_AUTO_SENSE 0x1000 1365#define MEDIA_TYPE_AUTO_DETECT 0x4000 1366#define MEDIA_TYPE_AUTO_NEGOTIATE 0x8000 1367 1368/* 1369 * Definitions for the field: 1370 * line_speed 1371 */ 1372#define LINE_SPEED_UNKNOWN 0x0000 1373#define LINE_SPEED_4 0x0001 1374#define LINE_SPEED_10 0x0002 1375#define LINE_SPEED_16 0x0004 1376#define LINE_SPEED_100 0x0008 1377#define LINE_SPEED_T4 0x0008 /* 100BaseT4 aliased for 9332BVT */ 1378#define LINE_SPEED_FULL_DUPLEX 0x8000 1379 1380/* 1381 * Definitions for the field: 1382 * bic_type (Bus interface chip type) 1383 */ 1384#define BIC_NO_CHIP 0x0000 /* Bus interface chip not implemented */ 1385#define BIC_583_CHIP 0x0001 /* 83C583 bus interface chip */ 1386#define BIC_584_CHIP 0x0002 /* 83C584 bus interface chip */ 1387#define BIC_585_CHIP 0x0003 /* 83C585 bus interface chip */ 1388#define BIC_593_CHIP 0x0004 /* 83C593 bus interface chip */ 1389#define BIC_594_CHIP 0x0005 /* 83C594 bus interface chip */ 1390#define BIC_564_CHIP 0x0006 /* PCMCIA Bus interface chip */ 1391#define BIC_790_CHIP 0x0007 /* 83C790 bus i-face/Ethernet NIC chip */ 1392#define BIC_571_CHIP 0x0008 /* 83C571 EISA bus master i-face */ 1393#define BIC_587_CHIP 0x0009 /* Token Ring AT bus master i-face */ 1394#define BIC_574_CHIP 0x0010 /* FEAST bus interface chip */ 1395#define BIC_8432_CHIP 0x0011 /* 8432 bus i-face/Ethernet NIC(DEC PCI) */ 1396#define BIC_9332_CHIP 0x0012 /* 9332 bus i-face/100Mbps Ether NIC(DEC PCI) */ 1397#define BIC_8432E_CHIP 0x0013 /* 8432 Enhanced bus iface/Ethernet NIC(DEC) */ 1398#define BIC_EPIC100_CHIP 0x0014 /* EPIC/100 10/100 Mbps Ethernet BIC/NIC */ 1399#define BIC_C94_CHIP 0x0015 /* 91C94 bus i-face in PCMCIA mode */ 1400#define BIC_X8020_CHIP 0x0016 /* Xilinx PCMCIA multi-func i-face */ 1401 1402/* 1403 * Definitions for the field: 1404 * nic_type (Bus interface chip type) 1405 */ 1406#define NIC_UNK_CHIP 0x0000 /* Unknown NIC chip */ 1407#define NIC_8390_CHIP 0x0001 /* DP8390 Ethernet NIC */ 1408#define NIC_690_CHIP 0x0002 /* 83C690 Ethernet NIC */ 1409#define NIC_825_CHIP 0x0003 /* 83C825 Token Ring NIC */ 1410/* #define NIC_???_CHIP 0x0004 */ /* Not used */ 1411/* #define NIC_???_CHIP 0x0005 */ /* Not used */ 1412/* #define NIC_???_CHIP 0x0006 */ /* Not used */ 1413#define NIC_790_CHIP 0x0007 /* 83C790 bus i-face/Ethernet NIC chip */ 1414#define NIC_C100_CHIP 0x0010 /* FEAST 100Mbps Ethernet NIC */ 1415#define NIC_8432_CHIP 0x0011 /* 8432 bus i-face/Ethernet NIC(DEC PCI) */ 1416#define NIC_9332_CHIP 0x0012 /* 9332 bus i-face/100Mbps Ether NIC(DEC PCI) */ 1417#define NIC_8432E_CHIP 0x0013 /* 8432 enhanced bus iface/Ethernet NIC(DEC) */ 1418#define NIC_EPIC100_CHIP 0x0014 /* EPIC/100 10/100 Mbps Ethernet BIC/NIC */ 1419#define NIC_C94_CHIP 0x0015 /* 91C94 PC Card with multi func */ 1420 1421/* 1422 * Definitions for the field: 1423 * adapter_type The adapter_type field describes the adapter/bus 1424 * configuration. 1425 */ 1426#define BUS_ISA16_TYPE 0x0001 /* 16 bit adap in 16 bit (E)ISA slot */ 1427#define BUS_ISA8_TYPE 0x0002 /* 8/16b adap in 8 bit XT/(E)ISA slot */ 1428#define BUS_MCA_TYPE 0x0003 /* Micro Channel adapter */ 1429 1430/* 1431 * Receive Mask definitions 1432 */ 1433#define ACCEPT_MULTICAST 0x0001 1434#define ACCEPT_BROADCAST 0x0002 1435#define PROMISCUOUS_MODE 0x0004 1436#define ACCEPT_SOURCE_ROUTING 0x0008 1437#define ACCEPT_ERR_PACKETS 0x0010 1438#define ACCEPT_ATT_MAC_FRAMES 0x0020 1439#define ACCEPT_MULTI_PROM 0x0040 1440#define TRANSMIT_ONLY 0x0080 1441#define ACCEPT_EXT_MAC_FRAMES 0x0100 1442#define EARLY_RX_ENABLE 0x0200 1443#define PKT_SIZE_NOT_NEEDED 0x0400 1444#define ACCEPT_SOURCE_ROUTING_SPANNING 0x0808 1445 1446#define ACCEPT_ALL_MAC_FRAMES 0x0120 1447 1448/* 1449 * config_mode defs 1450 */ 1451#define STORE_EEROM 0x0001 /* Store config in EEROM. */ 1452#define STORE_REGS 0x0002 /* Store config in register set. */ 1453 1454/* 1455 * equates for lmac_flags in adapter structure (Ethernet) 1456 */ 1457#define MEM_DISABLE 0x0001 1458#define RX_STATUS_POLL 0x0002 1459#define USE_RE_BIT 0x0004 1460/*#define RESERVED 0x0008 */ 1461/*#define RESERVED 0x0010 */ 1462/*#define RESERVED 0x0020 */ 1463/*#define RESERVED 0x0040 */ 1464/*#define RESERVED 0x0080 */ 1465/*#define RESERVED 0x0100 */ 1466/*#define RESERVED 0x0200 */ 1467/*#define RESERVED 0x0400 */ 1468/*#define RESERVED 0x0800 */ 1469/*#define RESERVED 0x1000 */ 1470/*#define RESERVED 0x2000 */ 1471/*#define RESERVED 0x4000 */ 1472/*#define RESERVED 0x8000 */ 1473 1474/* media_opts & media_set Fields bit defs for Ethernet ... */ 1475#define MED_OPT_BNC 0x01 1476#define MED_OPT_UTP 0x02 1477#define MED_OPT_AUI 0x04 1478#define MED_OPT_10MB 0x08 1479#define MED_OPT_100MB 0x10 1480#define MED_OPT_S10 0x20 1481 1482/* media_opts & media_set Fields bit defs for Token Ring ... */ 1483#define MED_OPT_4MB 0x08 1484#define MED_OPT_16MB 0x10 1485#define MED_OPT_STP 0x40 1486 1487#define MAX_8023_SIZE 1500 /* Max 802.3 size of frame. */ 1488#define DEFAULT_ERX_VALUE 4 /* Number of 16-byte blocks for 790B early Rx. */ 1489#define DEFAULT_ETX_VALUE 32 /* Number of bytes for 790B early Tx. */ 1490#define DEFAULT_TX_RETRIES 3 /* Number of transmit retries */ 1491#define LPBK_FRAME_SIZE 1024 /* Default loopback frame for Rx calibration test. */ 1492#define MAX_LOOKAHEAD_SIZE 252 /* Max lookahead size for ethernet. */ 1493 1494#define RW_MAC_STATE 0x1101 1495#define RW_SA_OF_LAST_AMP_OR_SMP 0x2803 1496#define RW_PHYSICAL_DROP_NUMBER 0x3B02 1497#define RW_UPSTREAM_NEIGHBOR_ADDRESS 0x3E03 1498#define RW_PRODUCT_INSTANCE_ID 0x4B09 1499 1500#define RW_TRC_STATUS_BLOCK 0x5412 1501 1502#define RW_MAC_ERROR_COUNTERS_NO_CLEAR 0x8006 1503#define RW_MAC_ERROR_COUNTER_CLEAR 0x7A06 1504#define RW_CONFIG_REGISTER_0 0xA001 1505#define RW_CONFIG_REGISTER_1 0xA101 1506#define RW_PRESCALE_TIMER_THRESHOLD 0xA201 1507#define RW_TPT_THRESHOLD 0xA301 1508#define RW_TQP_THRESHOLD 0xA401 1509#define RW_TNT_THRESHOLD 0xA501 1510#define RW_TBT_THRESHOLD 0xA601 1511#define RW_TSM_THRESHOLD 0xA701 1512#define RW_TAM_THRESHOLD 0xA801 1513#define RW_TBR_THRESHOLD 0xA901 1514#define RW_TER_THRESHOLD 0xAA01 1515#define RW_TGT_THRESHOLD 0xAB01 1516#define RW_THT_THRESHOLD 0xAC01 1517#define RW_TRR_THRESHOLD 0xAD01 1518#define RW_TVX_THRESHOLD 0xAE01 1519#define RW_INDIVIDUAL_MAC_ADDRESS 0xB003 1520 1521#define RW_INDIVIDUAL_GROUP_ADDRESS 0xB303 /* all of group addr */ 1522#define RW_INDIVIDUAL_GROUP_ADDR_WORD_0 0xB301 /* 1st word of group addr */ 1523#define RW_INDIVIDUAL_GROUP_ADDR 0xB402 /* 2nd-3rd word of group addr */ 1524#define RW_FUNCTIONAL_ADDRESS 0xB603 /* all of functional addr */ 1525#define RW_FUNCTIONAL_ADDR_WORD_0 0xB601 /* 1st word of func addr */ 1526#define RW_FUNCTIONAL_ADDR 0xB702 /* 2nd-3rd word func addr */ 1527 1528#define RW_BIT_SIGNIFICANT_GROUP_ADDR 0xB902 1529#define RW_SOURCE_RING_BRIDGE_NUMBER 0xBB01 1530#define RW_TARGET_RING_NUMBER 0xBC01 1531 1532#define RW_HIC_INTERRUPT_MASK 0xC601 1533 1534#define SOURCE_ROUTING_SPANNING_BITS 0x00C0 /* Spanning Tree Frames */ 1535#define SOURCE_ROUTING_EXPLORER_BIT 0x0040 /* Explorer and Single Route */ 1536 1537 /* write */ 1538 1539#define CSR_MSK_ALL 0x80 // Bic 587 Only 1540#define CSR_MSKTINT 0x20 1541#define CSR_MSKCBUSY 0x10 1542#define CSR_CLRTINT 0x08 1543#define CSR_CLRCBUSY 0x04 1544#define CSR_WCSS 0x02 1545#define CSR_CA 0x01 1546 1547 /* read */ 1548 1549#define CSR_TINT 0x20 1550#define CSR_CINT 0x10 1551#define CSR_TSTAT 0x08 1552#define CSR_CSTAT 0x04 1553#define CSR_FAULT 0x02 1554#define CSR_CBUSY 0x01 1555 1556#define LAAR_MEM16ENB 0x80 1557#define Zws16 0x20 1558 1559#define IRR_IEN 0x80 1560#define Zws8 0x01 1561 1562#define IMCCR_EIL 0x04 1563 1564typedef struct { 1565 __u8 ac; /* Access Control */ 1566 __u8 fc; /* Frame Control */ 1567 __u8 da[6]; /* Dest Addr */ 1568 __u8 sa[6]; /* Source Addr */ 1569 1570 __u16 vl; /* Vector Length */ 1571 __u8 dc_sc; /* Dest/Source Class */ 1572 __u8 vc; /* Vector Code */ 1573 } MAC_HEADER; 1574 1575#define MAX_SUB_VECTOR_INFO (RX_DATA_BUFFER_SIZE - sizeof(MAC_HEADER) - 2) 1576 1577typedef struct 1578 { 1579 __u8 svl; /* Sub-vector Length */ 1580 __u8 svi; /* Sub-vector Code */ 1581 __u8 svv[MAX_SUB_VECTOR_INFO]; /* Sub-vector Info */ 1582 } MAC_SUB_VECTOR; 1583 1584#endif /* __KERNEL__ */ 1585#endif /* __LINUX_SMCTR_H */ 1586