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446#include <linux/module.h>
447#include <linux/kernel.h>
448#include <linux/string.h>
449#include <linux/interrupt.h>
450#include <linux/ptrace.h>
451#include <linux/errno.h>
452#include <linux/ioport.h>
453#include <linux/pci.h>
454#include <linux/eisa.h>
455#include <linux/delay.h>
456#include <linux/init.h>
457#include <linux/spinlock.h>
458#include <linux/crc32.h>
459#include <linux/netdevice.h>
460#include <linux/etherdevice.h>
461#include <linux/skbuff.h>
462#include <linux/time.h>
463#include <linux/types.h>
464#include <linux/unistd.h>
465#include <linux/ctype.h>
466#include <linux/dma-mapping.h>
467#include <linux/moduleparam.h>
468#include <linux/bitops.h>
469#include <linux/gfp.h>
470
471#include <asm/io.h>
472#include <asm/dma.h>
473#include <asm/byteorder.h>
474#include <asm/unaligned.h>
475#include <asm/uaccess.h>
476#ifdef CONFIG_PPC_PMAC
477#include <asm/machdep.h>
478#endif
479
480#include "de4x5.h"
481
482static const char version[] __devinitconst =
483 KERN_INFO "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
484
485#define c_char const char
486
487
488
489
490struct phy_table {
491 int reset;
492 int id;
493 int ta;
494 struct {
495 int reg;
496 int mask;
497 int value;
498 } spd;
499};
500
501struct mii_phy {
502 int reset;
503 int id;
504 int ta;
505 struct {
506 int reg;
507 int mask;
508 int value;
509 } spd;
510 int addr;
511 u_char *gep;
512 u_char *rst;
513 u_int mc;
514 u_int ana;
515 u_int fdx;
516 u_int ttm;
517 u_int mci;
518};
519
520#define DE4X5_MAX_PHY 8
521
522struct sia_phy {
523 u_char mc;
524 u_char ext;
525 int csr13;
526 int csr14;
527 int csr15;
528 int gepc;
529 int gep;
530};
531
532
533
534
535
536static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}},
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}},
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}},
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}},
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}}
542};
543
544
545
546
547
548
549#define GENERIC_REG 0x05
550#define GENERIC_MASK MII_ANLPA_100M
551#define GENERIC_VALUE MII_ANLPA_100M
552
553
554
555
556static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
559};
560
561#define SMC 1
562#define ACCTON 2
563
564
565
566
567
568
569static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08,
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
573 0x00,0x18,}
574};
575
576
577#ifdef DE4X5_DEBUG
578static int de4x5_debug = DE4X5_DEBUG;
579#else
580
581static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
582#endif
583
584
585
586
587
588
589
590
591
592
593#ifdef DE4X5_PARM
594static char *args = DE4X5_PARM;
595#else
596static char *args;
597#endif
598
599struct parameters {
600 bool fdx;
601 int autosense;
602};
603
604#define DE4X5_AUTOSENSE_MS 250
605
606#define DE4X5_NDA 0xffe0
607
608
609
610
611#define PROBE_LENGTH 32
612#define ETH_PROM_SIG 0xAA5500FFUL
613
614
615
616
617#define PKT_BUF_SZ 1536
618#define IEEE802_3_SZ 1518
619#define MAX_PKT_SZ 1514
620#define MAX_DAT_SZ 1500
621#define MIN_DAT_SZ 1
622#define PKT_HDR_LEN 14
623#define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624#define QUEUE_PKT_TIMEOUT (3*HZ)
625
626
627
628
629
630#define DE4X5_EISA_IO_PORTS 0x0c00
631#define DE4X5_EISA_TOTAL_SIZE 0x100
632
633#define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
634
635#define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636#define DE4X5_NAME_LENGTH 8
637
638static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
639
640
641
642
643#define PROBE_LENGTH 32
644#define ETH_PROM_SIG 0xAA5500FFUL
645
646
647
648
649#define PCI_MAX_BUS_NUM 8
650#define DE4X5_PCI_TOTAL_SIZE 0x80
651#define DE4X5_CLASS_CODE 0x00020000
652
653
654
655
656
657
658
659#define DE4X5_ALIGN4 ((u_long)4 - 1)
660#define DE4X5_ALIGN8 ((u_long)8 - 1)
661#define DE4X5_ALIGN16 ((u_long)16 - 1)
662#define DE4X5_ALIGN32 ((u_long)32 - 1)
663#define DE4X5_ALIGN64 ((u_long)64 - 1)
664#define DE4X5_ALIGN128 ((u_long)128 - 1)
665
666#define DE4X5_ALIGN DE4X5_ALIGN32
667#define DE4X5_CACHE_ALIGN CAL_16LONG
668#define DESC_SKIP_LEN DSL_0
669
670#define DESC_ALIGN
671
672#ifndef DEC_ONLY
673static int dec_only;
674#else
675static int dec_only = 1;
676#endif
677
678
679
680
681#define ENABLE_IRQs { \
682 imr |= lp->irq_en;\
683 outl(imr, DE4X5_IMR); \
684}
685
686#define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
688 imr &= ~lp->irq_en;\
689 outl(imr, DE4X5_IMR); \
690}
691
692#define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); \
695}
696
697#define MASK_IRQs {\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); \
701}
702
703
704
705
706#define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); \
710}
711
712#define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); \
716}
717
718
719
720
721#define RESET_SIA outl(0, DE4X5_SICR);
722
723
724
725
726#define DE4X5_AUTOSENSE_MS 250
727
728
729
730
731struct de4x5_srom {
732 char sub_vendor_id[2];
733 char sub_system_id[2];
734 char reserved[12];
735 char id_block_crc;
736 char reserved2;
737 char version;
738 char num_controllers;
739 char ieee_addr[6];
740 char info[100];
741 short chksum;
742};
743#define SUB_VENDOR_ID 0x500a
744
745
746
747
748
749
750
751
752
753#define NUM_RX_DESC 8
754#define NUM_TX_DESC 32
755#define RX_BUFF_SZ 1536
756
757
758struct de4x5_desc {
759 volatile __le32 status;
760 __le32 des1;
761 __le32 buf;
762 __le32 next;
763 DESC_ALIGN
764};
765
766
767
768
769#define DE4X5_PKT_STAT_SZ 16
770#define DE4X5_PKT_BIN_SZ 128
771
772
773struct pkt_stats {
774 u_int bins[DE4X5_PKT_STAT_SZ];
775 u_int unicast;
776 u_int multicast;
777 u_int broadcast;
778 u_int excessive_collisions;
779 u_int tx_underruns;
780 u_int excessive_underruns;
781 u_int rx_runt_frames;
782 u_int rx_collision;
783 u_int rx_dribble;
784 u_int rx_overflow;
785};
786
787struct de4x5_private {
788 char adapter_name[80];
789 u_long interrupt;
790 struct de4x5_desc *rx_ring;
791 struct de4x5_desc *tx_ring;
792 struct sk_buff *tx_skb[NUM_TX_DESC];
793 struct sk_buff *rx_skb[NUM_RX_DESC];
794 int rx_new, rx_old;
795 int tx_new, tx_old;
796 char setup_frame[SETUP_FRAME_LEN];
797 char frame[64];
798 spinlock_t lock;
799 struct net_device_stats stats;
800 struct pkt_stats pktStats;
801 char rxRingSize;
802 char txRingSize;
803 int bus;
804 int bus_num;
805 int device;
806 int state;
807 int chipset;
808 s32 irq_mask;
809 s32 irq_en;
810 int media;
811 int c_media;
812 bool fdx;
813 int linkOK;
814 int autosense;
815 bool tx_enable;
816 int setup_f;
817 int local_state;
818 struct mii_phy phy[DE4X5_MAX_PHY];
819 struct sia_phy sia;
820 int active;
821 int mii_cnt;
822 int timeout;
823 struct timer_list timer;
824 int tmp;
825 struct {
826 u_long lock;
827 s32 csr0;
828 s32 csr6;
829 s32 csr7;
830 s32 gep;
831 s32 gepc;
832 s32 csr13;
833 s32 csr14;
834 s32 csr15;
835 int save_cnt;
836 struct sk_buff_head queue;
837 } cache;
838 struct de4x5_srom srom;
839 int cfrv;
840 int rx_ovf;
841 bool useSROM;
842 bool useMII;
843 int asBitValid;
844 int asPolarity;
845 int asBit;
846 int defMedium;
847 int tcount;
848 int infoblock_init;
849 int infoleaf_offset;
850 s32 infoblock_csr6;
851 int infoblock_media;
852 int (*infoleaf_fn)(struct net_device *);
853 u_char *rst;
854 u_char ibn;
855 struct parameters params;
856 struct device *gendev;
857 dma_addr_t dma_rings;
858 int dma_size;
859 char *rx_bufs;
860};
861
862
863
864
865
866
867
868
869
870
871
872
873
874static struct {
875 int chipset;
876 int bus;
877 int irq;
878 u_char addr[ETH_ALEN];
879} last = {0,};
880
881
882
883
884
885
886
887
888#define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
891
892#define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
893
894
895
896
897static int de4x5_open(struct net_device *dev);
898static netdev_tx_t de4x5_queue_pkt(struct sk_buff *skb,
899 struct net_device *dev);
900static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
901static int de4x5_close(struct net_device *dev);
902static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
903static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
904static void set_multicast_list(struct net_device *dev);
905static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
906
907
908
909
910static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
911static int de4x5_init(struct net_device *dev);
912static int de4x5_sw_reset(struct net_device *dev);
913static int de4x5_rx(struct net_device *dev);
914static int de4x5_tx(struct net_device *dev);
915static void de4x5_ast(struct net_device *dev);
916static int de4x5_txur(struct net_device *dev);
917static int de4x5_rx_ovfc(struct net_device *dev);
918
919static int autoconf_media(struct net_device *dev);
920static void create_packet(struct net_device *dev, char *frame, int len);
921static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
922static int dc21040_autoconf(struct net_device *dev);
923static int dc21041_autoconf(struct net_device *dev);
924static int dc21140m_autoconf(struct net_device *dev);
925static int dc2114x_autoconf(struct net_device *dev);
926static int srom_autoconf(struct net_device *dev);
927static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
928static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
929static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
930static int test_for_100Mb(struct net_device *dev, int msec);
931static int wait_for_link(struct net_device *dev);
932static int test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec);
933static int is_spd_100(struct net_device *dev);
934static int is_100_up(struct net_device *dev);
935static int is_10_up(struct net_device *dev);
936static int is_anc_capable(struct net_device *dev);
937static int ping_media(struct net_device *dev, int msec);
938static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
939static void de4x5_free_rx_buffs(struct net_device *dev);
940static void de4x5_free_tx_buffs(struct net_device *dev);
941static void de4x5_save_skbs(struct net_device *dev);
942static void de4x5_rst_desc_ring(struct net_device *dev);
943static void de4x5_cache_state(struct net_device *dev, int flag);
944static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
945static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
946static struct sk_buff *de4x5_get_cache(struct net_device *dev);
947static void de4x5_setup_intr(struct net_device *dev);
948static void de4x5_init_connection(struct net_device *dev);
949static int de4x5_reset_phy(struct net_device *dev);
950static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
951static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
952static int test_tp(struct net_device *dev, s32 msec);
953static int EISA_signature(char *name, struct device *device);
954static int PCI_signature(char *name, struct de4x5_private *lp);
955static void DevicePresent(struct net_device *dev, u_long iobase);
956static void enet_addr_rst(u_long aprom_addr);
957static int de4x5_bad_srom(struct de4x5_private *lp);
958static short srom_rd(u_long address, u_char offset);
959static void srom_latch(u_int command, u_long address);
960static void srom_command(u_int command, u_long address);
961static void srom_address(u_int command, u_long address, u_char offset);
962static short srom_data(u_int command, u_long address);
963
964static void sendto_srom(u_int command, u_long addr);
965static int getfrom_srom(u_long addr);
966static int srom_map_media(struct net_device *dev);
967static int srom_infoleaf_info(struct net_device *dev);
968static void srom_init(struct net_device *dev);
969static void srom_exec(struct net_device *dev, u_char *p);
970static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
971static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
972static int mii_rdata(u_long ioaddr);
973static void mii_wdata(int data, int len, u_long ioaddr);
974static void mii_ta(u_long rw, u_long ioaddr);
975static int mii_swap(int data, int len);
976static void mii_address(u_char addr, u_long ioaddr);
977static void sendto_mii(u32 command, int data, u_long ioaddr);
978static int getfrom_mii(u32 command, u_long ioaddr);
979static int mii_get_oui(u_char phyaddr, u_long ioaddr);
980static int mii_get_phy(struct net_device *dev);
981static void SetMulticastFilter(struct net_device *dev);
982static int get_hw_addr(struct net_device *dev);
983static void srom_repair(struct net_device *dev, int card);
984static int test_bad_enet(struct net_device *dev, int status);
985static int an_exception(struct de4x5_private *lp);
986static char *build_setup_frame(struct net_device *dev, int mode);
987static void disable_ast(struct net_device *dev);
988static long de4x5_switch_mac_port(struct net_device *dev);
989static int gep_rd(struct net_device *dev);
990static void gep_wr(s32 data, struct net_device *dev);
991static void yawn(struct net_device *dev, int state);
992static void de4x5_parse_params(struct net_device *dev);
993static void de4x5_dbg_open(struct net_device *dev);
994static void de4x5_dbg_mii(struct net_device *dev, int k);
995static void de4x5_dbg_media(struct net_device *dev);
996static void de4x5_dbg_srom(struct de4x5_srom *p);
997static void de4x5_dbg_rx(struct sk_buff *skb, int len);
998static int de4x5_strncmp(char *a, char *b, int n);
999static int dc21041_infoleaf(struct net_device *dev);
1000static int dc21140_infoleaf(struct net_device *dev);
1001static int dc21142_infoleaf(struct net_device *dev);
1002static int dc21143_infoleaf(struct net_device *dev);
1003static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1004static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1005static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1006static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1007static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1008static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1009static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1010
1011
1012
1013
1014
1015
1016
1017static int io=0x0;
1018
1019module_param(io, int, 0);
1020module_param(de4x5_debug, int, 0);
1021module_param(dec_only, int, 0);
1022module_param(args, charp, 0);
1023
1024MODULE_PARM_DESC(io, "de4x5 I/O base address");
1025MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1026MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1027MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1028MODULE_LICENSE("GPL");
1029
1030
1031
1032
1033struct InfoLeaf {
1034 int chipset;
1035 int (*fn)(struct net_device *);
1036};
1037static struct InfoLeaf infoleaf_array[] = {
1038 {DC21041, dc21041_infoleaf},
1039 {DC21140, dc21140_infoleaf},
1040 {DC21142, dc21142_infoleaf},
1041 {DC21143, dc21143_infoleaf}
1042};
1043#define INFOLEAF_SIZE ARRAY_SIZE(infoleaf_array)
1044
1045
1046
1047
1048static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1049 type0_infoblock,
1050 type1_infoblock,
1051 type2_infoblock,
1052 type3_infoblock,
1053 type4_infoblock,
1054 type5_infoblock,
1055 compact_infoblock
1056};
1057
1058#define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1059
1060
1061
1062
1063#define RESET_DE4X5 {\
1064 int i;\
1065 i=inl(DE4X5_BMR);\
1066 mdelay(1);\
1067 outl(i | BMR_SWR, DE4X5_BMR);\
1068 mdelay(1);\
1069 outl(i, DE4X5_BMR);\
1070 mdelay(1);\
1071 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1072 mdelay(1);\
1073}
1074
1075#define PHY_HARD_RESET {\
1076 outl(GEP_HRST, DE4X5_GEP); \
1077 mdelay(1); \
1078 outl(0x00, DE4X5_GEP);\
1079 mdelay(2); \
1080}
1081
1082static const struct net_device_ops de4x5_netdev_ops = {
1083 .ndo_open = de4x5_open,
1084 .ndo_stop = de4x5_close,
1085 .ndo_start_xmit = de4x5_queue_pkt,
1086 .ndo_get_stats = de4x5_get_stats,
1087 .ndo_set_multicast_list = set_multicast_list,
1088 .ndo_do_ioctl = de4x5_ioctl,
1089 .ndo_change_mtu = eth_change_mtu,
1090 .ndo_set_mac_address= eth_mac_addr,
1091 .ndo_validate_addr = eth_validate_addr,
1092};
1093
1094
1095static int __devinit
1096de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1097{
1098 char name[DE4X5_NAME_LENGTH + 1];
1099 struct de4x5_private *lp = netdev_priv(dev);
1100 struct pci_dev *pdev = NULL;
1101 int i, status=0;
1102
1103 dev_set_drvdata(gendev, dev);
1104
1105
1106 if (lp->bus == EISA) {
1107 outb(WAKEUP, PCI_CFPM);
1108 } else {
1109 pdev = to_pci_dev (gendev);
1110 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1111 }
1112 mdelay(10);
1113
1114 RESET_DE4X5;
1115
1116 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1117 return -ENXIO;
1118 }
1119
1120
1121
1122
1123 lp->useSROM = false;
1124 if (lp->bus == PCI) {
1125 PCI_signature(name, lp);
1126 } else {
1127 EISA_signature(name, gendev);
1128 }
1129
1130 if (*name == '\0') {
1131 return -ENXIO;
1132 }
1133
1134 dev->base_addr = iobase;
1135 printk ("%s: %s at 0x%04lx", dev_name(gendev), name, iobase);
1136
1137 status = get_hw_addr(dev);
1138 printk(", h/w address %pM\n", dev->dev_addr);
1139
1140 if (status != 0) {
1141 printk(" which has an Ethernet PROM CRC error.\n");
1142 return -ENXIO;
1143 } else {
1144 skb_queue_head_init(&lp->cache.queue);
1145 lp->cache.gepc = GEP_INIT;
1146 lp->asBit = GEP_SLNK;
1147 lp->asPolarity = GEP_SLNK;
1148 lp->asBitValid = ~0;
1149 lp->timeout = -1;
1150 lp->gendev = gendev;
1151 spin_lock_init(&lp->lock);
1152 init_timer(&lp->timer);
1153 lp->timer.function = (void (*)(unsigned long))de4x5_ast;
1154 lp->timer.data = (unsigned long)dev;
1155 de4x5_parse_params(dev);
1156
1157
1158
1159
1160 lp->autosense = lp->params.autosense;
1161 if (lp->chipset != DC21140) {
1162 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1163 lp->params.autosense = TP;
1164 }
1165 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1166 lp->params.autosense = BNC;
1167 }
1168 }
1169 lp->fdx = lp->params.fdx;
1170 sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev));
1171
1172 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1173#if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY)
1174 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1175#endif
1176 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1177 &lp->dma_rings, GFP_ATOMIC);
1178 if (lp->rx_ring == NULL) {
1179 return -ENOMEM;
1180 }
1181
1182 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1183
1184
1185
1186
1187
1188#if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
1189 for (i=0; i<NUM_RX_DESC; i++) {
1190 lp->rx_ring[i].status = 0;
1191 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1192 lp->rx_ring[i].buf = 0;
1193 lp->rx_ring[i].next = 0;
1194 lp->rx_skb[i] = (struct sk_buff *) 1;
1195 }
1196
1197#else
1198 {
1199 dma_addr_t dma_rx_bufs;
1200
1201 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1202 * sizeof(struct de4x5_desc);
1203 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1204 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1205 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1206 for (i=0; i<NUM_RX_DESC; i++) {
1207 lp->rx_ring[i].status = 0;
1208 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1209 lp->rx_ring[i].buf =
1210 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1211 lp->rx_ring[i].next = 0;
1212 lp->rx_skb[i] = (struct sk_buff *) 1;
1213 }
1214
1215 }
1216#endif
1217
1218 barrier();
1219
1220 lp->rxRingSize = NUM_RX_DESC;
1221 lp->txRingSize = NUM_TX_DESC;
1222
1223
1224 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1225 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1226
1227
1228 outl(lp->dma_rings, DE4X5_RRBA);
1229 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1230 DE4X5_TRBA);
1231
1232
1233 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1234 lp->irq_en = IMR_NIM | IMR_AIM;
1235
1236
1237 create_packet(dev, lp->frame, sizeof(lp->frame));
1238
1239
1240 i = lp->cfrv & 0x000000fe;
1241 if ((lp->chipset == DC21140) && (i == 0x20)) {
1242 lp->rx_ovf = 1;
1243 }
1244
1245
1246 if (lp->useSROM) {
1247 lp->state = INITIALISED;
1248 if (srom_infoleaf_info(dev)) {
1249 dma_free_coherent (gendev, lp->dma_size,
1250 lp->rx_ring, lp->dma_rings);
1251 return -ENXIO;
1252 }
1253 srom_init(dev);
1254 }
1255
1256 lp->state = CLOSED;
1257
1258
1259
1260
1261 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1262 mii_get_phy(dev);
1263 }
1264
1265 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1266 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1267 }
1268
1269 if (de4x5_debug & DEBUG_VERSION) {
1270 printk(version);
1271 }
1272
1273
1274 SET_NETDEV_DEV(dev, gendev);
1275 dev->netdev_ops = &de4x5_netdev_ops;
1276 dev->mem_start = 0;
1277
1278
1279 if ((status = register_netdev (dev))) {
1280 dma_free_coherent (gendev, lp->dma_size,
1281 lp->rx_ring, lp->dma_rings);
1282 return status;
1283 }
1284
1285
1286 yawn(dev, SLEEP);
1287
1288 return status;
1289}
1290
1291
1292static int
1293de4x5_open(struct net_device *dev)
1294{
1295 struct de4x5_private *lp = netdev_priv(dev);
1296 u_long iobase = dev->base_addr;
1297 int i, status = 0;
1298 s32 omr;
1299
1300
1301 for (i=0; i<lp->rxRingSize; i++) {
1302 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1303 de4x5_free_rx_buffs(dev);
1304 return -EAGAIN;
1305 }
1306 }
1307
1308
1309
1310
1311 yawn(dev, WAKEUP);
1312
1313
1314
1315
1316 status = de4x5_init(dev);
1317 spin_lock_init(&lp->lock);
1318 lp->state = OPEN;
1319 de4x5_dbg_open(dev);
1320
1321 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1322 lp->adapter_name, dev)) {
1323 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1324 if (request_irq(dev->irq, de4x5_interrupt, IRQF_DISABLED | IRQF_SHARED,
1325 lp->adapter_name, dev)) {
1326 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1327 disable_ast(dev);
1328 de4x5_free_rx_buffs(dev);
1329 de4x5_free_tx_buffs(dev);
1330 yawn(dev, SLEEP);
1331 lp->state = CLOSED;
1332 return -EAGAIN;
1333 } else {
1334 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1335 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1336 }
1337 }
1338
1339 lp->interrupt = UNMASK_INTERRUPTS;
1340 dev->trans_start = jiffies;
1341
1342 START_DE4X5;
1343
1344 de4x5_setup_intr(dev);
1345
1346 if (de4x5_debug & DEBUG_OPEN) {
1347 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1348 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1349 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1350 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1351 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1352 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1353 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1354 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1355 }
1356
1357 return status;
1358}
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368static int
1369de4x5_init(struct net_device *dev)
1370{
1371
1372 netif_stop_queue(dev);
1373
1374 de4x5_sw_reset(dev);
1375
1376
1377 autoconf_media(dev);
1378
1379 return 0;
1380}
1381
1382static int
1383de4x5_sw_reset(struct net_device *dev)
1384{
1385 struct de4x5_private *lp = netdev_priv(dev);
1386 u_long iobase = dev->base_addr;
1387 int i, j, status = 0;
1388 s32 bmr, omr;
1389
1390
1391 if (!lp->useSROM) {
1392 if (lp->phy[lp->active].id != 0) {
1393 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1394 } else {
1395 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1396 }
1397 de4x5_switch_mac_port(dev);
1398 }
1399
1400
1401
1402
1403
1404
1405 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1406 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1407 outl(bmr, DE4X5_BMR);
1408
1409 omr = inl(DE4X5_OMR) & ~OMR_PR;
1410 if (lp->chipset == DC21140) {
1411 omr |= (OMR_SDP | OMR_SB);
1412 }
1413 lp->setup_f = PERFECT;
1414 outl(lp->dma_rings, DE4X5_RRBA);
1415 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1416 DE4X5_TRBA);
1417
1418 lp->rx_new = lp->rx_old = 0;
1419 lp->tx_new = lp->tx_old = 0;
1420
1421 for (i = 0; i < lp->rxRingSize; i++) {
1422 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1423 }
1424
1425 for (i = 0; i < lp->txRingSize; i++) {
1426 lp->tx_ring[i].status = cpu_to_le32(0);
1427 }
1428
1429 barrier();
1430
1431
1432 SetMulticastFilter(dev);
1433
1434 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1435 outl(omr|OMR_ST, DE4X5_OMR);
1436
1437
1438
1439 for (j=0, i=0;(i<500) && (j==0);i++) {
1440 mdelay(1);
1441 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1442 }
1443 outl(omr, DE4X5_OMR);
1444
1445 if (j == 0) {
1446 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1447 inl(DE4X5_STS));
1448 status = -EIO;
1449 }
1450
1451 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1452 lp->tx_old = lp->tx_new;
1453
1454 return status;
1455}
1456
1457
1458
1459
1460static netdev_tx_t
1461de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1462{
1463 struct de4x5_private *lp = netdev_priv(dev);
1464 u_long iobase = dev->base_addr;
1465 u_long flags = 0;
1466
1467 netif_stop_queue(dev);
1468 if (!lp->tx_enable)
1469 return NETDEV_TX_LOCKED;
1470
1471
1472
1473
1474
1475
1476 spin_lock_irqsave(&lp->lock, flags);
1477 de4x5_tx(dev);
1478 spin_unlock_irqrestore(&lp->lock, flags);
1479
1480
1481 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1482 return NETDEV_TX_LOCKED;
1483
1484
1485 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1486 if (lp->interrupt) {
1487 de4x5_putb_cache(dev, skb);
1488 } else {
1489 de4x5_put_cache(dev, skb);
1490 }
1491 if (de4x5_debug & DEBUG_TX) {
1492 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1493 }
1494 } else if (skb->len > 0) {
1495
1496 if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) {
1497 de4x5_put_cache(dev, skb);
1498 skb = de4x5_get_cache(dev);
1499 }
1500
1501 while (skb && !netif_queue_stopped(dev) &&
1502 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1503 spin_lock_irqsave(&lp->lock, flags);
1504 netif_stop_queue(dev);
1505 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1506 lp->stats.tx_bytes += skb->len;
1507 outl(POLL_DEMAND, DE4X5_TPD);
1508
1509 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1510
1511 if (TX_BUFFS_AVAIL) {
1512 netif_start_queue(dev);
1513 }
1514 skb = de4x5_get_cache(dev);
1515 spin_unlock_irqrestore(&lp->lock, flags);
1516 }
1517 if (skb) de4x5_putb_cache(dev, skb);
1518 }
1519
1520 lp->cache.lock = 0;
1521
1522 return NETDEV_TX_OK;
1523}
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536static irqreturn_t
1537de4x5_interrupt(int irq, void *dev_id)
1538{
1539 struct net_device *dev = dev_id;
1540 struct de4x5_private *lp;
1541 s32 imr, omr, sts, limit;
1542 u_long iobase;
1543 unsigned int handled = 0;
1544
1545 lp = netdev_priv(dev);
1546 spin_lock(&lp->lock);
1547 iobase = dev->base_addr;
1548
1549 DISABLE_IRQs;
1550
1551 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1552 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1553
1554 synchronize_irq(dev->irq);
1555
1556 for (limit=0; limit<8; limit++) {
1557 sts = inl(DE4X5_STS);
1558 outl(sts, DE4X5_STS);
1559
1560 if (!(sts & lp->irq_mask)) break;
1561 handled = 1;
1562
1563 if (sts & (STS_RI | STS_RU))
1564 de4x5_rx(dev);
1565
1566 if (sts & (STS_TI | STS_TU))
1567 de4x5_tx(dev);
1568
1569 if (sts & STS_LNF) {
1570 lp->irq_mask &= ~IMR_LFM;
1571 }
1572
1573 if (sts & STS_UNF) {
1574 de4x5_txur(dev);
1575 }
1576
1577 if (sts & STS_SE) {
1578 STOP_DE4X5;
1579 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1580 dev->name, sts);
1581 spin_unlock(&lp->lock);
1582 return IRQ_HANDLED;
1583 }
1584 }
1585
1586
1587 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1588 while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) {
1589 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1590 }
1591 lp->cache.lock = 0;
1592 }
1593
1594 lp->interrupt = UNMASK_INTERRUPTS;
1595 ENABLE_IRQs;
1596 spin_unlock(&lp->lock);
1597
1598 return IRQ_RETVAL(handled);
1599}
1600
1601static int
1602de4x5_rx(struct net_device *dev)
1603{
1604 struct de4x5_private *lp = netdev_priv(dev);
1605 u_long iobase = dev->base_addr;
1606 int entry;
1607 s32 status;
1608
1609 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1610 entry=lp->rx_new) {
1611 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1612
1613 if (lp->rx_ovf) {
1614 if (inl(DE4X5_MFC) & MFC_FOCM) {
1615 de4x5_rx_ovfc(dev);
1616 break;
1617 }
1618 }
1619
1620 if (status & RD_FS) {
1621 lp->rx_old = entry;
1622 }
1623
1624 if (status & RD_LS) {
1625 if (lp->tx_enable) lp->linkOK++;
1626 if (status & RD_ES) {
1627 lp->stats.rx_errors++;
1628 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1629 if (status & RD_CE) lp->stats.rx_crc_errors++;
1630 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1631 if (status & RD_TL) lp->stats.rx_length_errors++;
1632 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1633 if (status & RD_CS) lp->pktStats.rx_collision++;
1634 if (status & RD_DB) lp->pktStats.rx_dribble++;
1635 if (status & RD_OF) lp->pktStats.rx_overflow++;
1636 } else {
1637 struct sk_buff *skb;
1638 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1639 >> 16) - 4;
1640
1641 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1642 printk("%s: Insufficient memory; nuking packet.\n",
1643 dev->name);
1644 lp->stats.rx_dropped++;
1645 } else {
1646 de4x5_dbg_rx(skb, pkt_len);
1647
1648
1649 skb->protocol=eth_type_trans(skb,dev);
1650 de4x5_local_stats(dev, skb->data, pkt_len);
1651 netif_rx(skb);
1652
1653
1654 lp->stats.rx_packets++;
1655 lp->stats.rx_bytes += pkt_len;
1656 }
1657 }
1658
1659
1660 for (;lp->rx_old!=entry;lp->rx_old=(lp->rx_old + 1)%lp->rxRingSize) {
1661 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1662 barrier();
1663 }
1664 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1665 barrier();
1666 }
1667
1668
1669
1670
1671 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1672 }
1673
1674 return 0;
1675}
1676
1677static inline void
1678de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1679{
1680 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1681 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1682 DMA_TO_DEVICE);
1683 if ((u_long) lp->tx_skb[entry] > 1)
1684 dev_kfree_skb_irq(lp->tx_skb[entry]);
1685 lp->tx_skb[entry] = NULL;
1686}
1687
1688
1689
1690
1691static int
1692de4x5_tx(struct net_device *dev)
1693{
1694 struct de4x5_private *lp = netdev_priv(dev);
1695 u_long iobase = dev->base_addr;
1696 int entry;
1697 s32 status;
1698
1699 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1700 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1701 if (status < 0) {
1702 break;
1703 } else if (status != 0x7fffffff) {
1704 if (status & TD_ES) {
1705 lp->stats.tx_errors++;
1706 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1707 if (status & TD_LC) lp->stats.tx_window_errors++;
1708 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1709 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1710 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1711
1712 if (TX_PKT_PENDING) {
1713 outl(POLL_DEMAND, DE4X5_TPD);
1714 }
1715 } else {
1716 lp->stats.tx_packets++;
1717 if (lp->tx_enable) lp->linkOK++;
1718 }
1719
1720 lp->stats.collisions += ((status & TD_EC) ? 16 :
1721 ((status & TD_CC) >> 3));
1722
1723
1724 if (lp->tx_skb[entry] != NULL)
1725 de4x5_free_tx_buff(lp, entry);
1726 }
1727
1728
1729 lp->tx_old = (lp->tx_old + 1) % lp->txRingSize;
1730 }
1731
1732
1733 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1734 if (lp->interrupt)
1735 netif_wake_queue(dev);
1736 else
1737 netif_start_queue(dev);
1738 }
1739
1740 return 0;
1741}
1742
1743static void
1744de4x5_ast(struct net_device *dev)
1745{
1746 struct de4x5_private *lp = netdev_priv(dev);
1747 int next_tick = DE4X5_AUTOSENSE_MS;
1748 int dt;
1749
1750 if (lp->useSROM)
1751 next_tick = srom_autoconf(dev);
1752 else if (lp->chipset == DC21140)
1753 next_tick = dc21140m_autoconf(dev);
1754 else if (lp->chipset == DC21041)
1755 next_tick = dc21041_autoconf(dev);
1756 else if (lp->chipset == DC21040)
1757 next_tick = dc21040_autoconf(dev);
1758 lp->linkOK = 0;
1759
1760 dt = (next_tick * HZ) / 1000;
1761
1762 if (!dt)
1763 dt = 1;
1764
1765 mod_timer(&lp->timer, jiffies + dt);
1766}
1767
1768static int
1769de4x5_txur(struct net_device *dev)
1770{
1771 struct de4x5_private *lp = netdev_priv(dev);
1772 u_long iobase = dev->base_addr;
1773 int omr;
1774
1775 omr = inl(DE4X5_OMR);
1776 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1777 omr &= ~(OMR_ST|OMR_SR);
1778 outl(omr, DE4X5_OMR);
1779 while (inl(DE4X5_STS) & STS_TS);
1780 if ((omr & OMR_TR) < OMR_TR) {
1781 omr += 0x4000;
1782 } else {
1783 omr |= OMR_SF;
1784 }
1785 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1786 }
1787
1788 return 0;
1789}
1790
1791static int
1792de4x5_rx_ovfc(struct net_device *dev)
1793{
1794 struct de4x5_private *lp = netdev_priv(dev);
1795 u_long iobase = dev->base_addr;
1796 int omr;
1797
1798 omr = inl(DE4X5_OMR);
1799 outl(omr & ~OMR_SR, DE4X5_OMR);
1800 while (inl(DE4X5_STS) & STS_RS);
1801
1802 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1803 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1804 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1805 }
1806
1807 outl(omr, DE4X5_OMR);
1808
1809 return 0;
1810}
1811
1812static int
1813de4x5_close(struct net_device *dev)
1814{
1815 struct de4x5_private *lp = netdev_priv(dev);
1816 u_long iobase = dev->base_addr;
1817 s32 imr, omr;
1818
1819 disable_ast(dev);
1820
1821 netif_stop_queue(dev);
1822
1823 if (de4x5_debug & DEBUG_CLOSE) {
1824 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1825 dev->name, inl(DE4X5_STS));
1826 }
1827
1828
1829
1830
1831 DISABLE_IRQs;
1832 STOP_DE4X5;
1833
1834
1835 free_irq(dev->irq, dev);
1836 lp->state = CLOSED;
1837
1838
1839 de4x5_free_rx_buffs(dev);
1840 de4x5_free_tx_buffs(dev);
1841
1842
1843 yawn(dev, SLEEP);
1844
1845 return 0;
1846}
1847
1848static struct net_device_stats *
1849de4x5_get_stats(struct net_device *dev)
1850{
1851 struct de4x5_private *lp = netdev_priv(dev);
1852 u_long iobase = dev->base_addr;
1853
1854 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1855
1856 return &lp->stats;
1857}
1858
1859static void
1860de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1861{
1862 struct de4x5_private *lp = netdev_priv(dev);
1863 int i;
1864
1865 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1866 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1867 lp->pktStats.bins[i]++;
1868 i = DE4X5_PKT_STAT_SZ;
1869 }
1870 }
1871 if (buf[0] & 0x01) {
1872 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1873 lp->pktStats.broadcast++;
1874 } else {
1875 lp->pktStats.multicast++;
1876 }
1877 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1878 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1879 lp->pktStats.unicast++;
1880 }
1881
1882 lp->pktStats.bins[0]++;
1883 if (lp->pktStats.bins[0] == 0) {
1884 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1885 }
1886}
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896static void
1897load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1898{
1899 struct de4x5_private *lp = netdev_priv(dev);
1900 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1901 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1902
1903 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1904 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1905 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1906 lp->tx_skb[lp->tx_new] = skb;
1907 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1908 barrier();
1909
1910 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1911 barrier();
1912}
1913
1914
1915
1916
1917static void
1918set_multicast_list(struct net_device *dev)
1919{
1920 struct de4x5_private *lp = netdev_priv(dev);
1921 u_long iobase = dev->base_addr;
1922
1923
1924 if (lp->state == OPEN) {
1925 if (dev->flags & IFF_PROMISC) {
1926 u32 omr;
1927 omr = inl(DE4X5_OMR);
1928 omr |= OMR_PR;
1929 outl(omr, DE4X5_OMR);
1930 } else {
1931 SetMulticastFilter(dev);
1932 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1933 SETUP_FRAME_LEN, (struct sk_buff *)1);
1934
1935 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1936 outl(POLL_DEMAND, DE4X5_TPD);
1937 dev->trans_start = jiffies;
1938 }
1939 }
1940}
1941
1942
1943
1944
1945
1946
1947static void
1948SetMulticastFilter(struct net_device *dev)
1949{
1950 struct de4x5_private *lp = netdev_priv(dev);
1951 struct netdev_hw_addr *ha;
1952 u_long iobase = dev->base_addr;
1953 int i, bit, byte;
1954 u16 hashcode;
1955 u32 omr, crc;
1956 char *pa;
1957 unsigned char *addrs;
1958
1959 omr = inl(DE4X5_OMR);
1960 omr &= ~(OMR_PR | OMR_PM);
1961 pa = build_setup_frame(dev, ALL);
1962
1963 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 14)) {
1964 omr |= OMR_PM;
1965 } else if (lp->setup_f == HASH_PERF) {
1966 netdev_for_each_mc_addr(ha, dev) {
1967 addrs = ha->addr;
1968 if ((*addrs & 0x01) == 1) {
1969 crc = ether_crc_le(ETH_ALEN, addrs);
1970 hashcode = crc & HASH_BITS;
1971
1972 byte = hashcode >> 3;
1973 bit = 1 << (hashcode & 0x07);
1974
1975 byte <<= 1;
1976 if (byte & 0x02) {
1977 byte -= 1;
1978 }
1979 lp->setup_frame[byte] |= bit;
1980 }
1981 }
1982 } else {
1983 netdev_for_each_mc_addr(ha, dev) {
1984 addrs = ha->addr;
1985 for (i=0; i<ETH_ALEN; i++) {
1986 *(pa + (i&1)) = *addrs++;
1987 if (i & 0x01) pa += 4;
1988 }
1989 }
1990 }
1991 outl(omr, DE4X5_OMR);
1992}
1993
1994#ifdef CONFIG_EISA
1995
1996static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1997
1998static int __init de4x5_eisa_probe (struct device *gendev)
1999{
2000 struct eisa_device *edev;
2001 u_long iobase;
2002 u_char irq, regval;
2003 u_short vendor;
2004 u32 cfid;
2005 int status, device;
2006 struct net_device *dev;
2007 struct de4x5_private *lp;
2008
2009 edev = to_eisa_device (gendev);
2010 iobase = edev->base_addr;
2011
2012 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2013 return -EBUSY;
2014
2015 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2016 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2017 status = -EBUSY;
2018 goto release_reg_1;
2019 }
2020
2021 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2022 status = -ENOMEM;
2023 goto release_reg_2;
2024 }
2025 lp = netdev_priv(dev);
2026
2027 cfid = (u32) inl(PCI_CFID);
2028 lp->cfrv = (u_short) inl(PCI_CFRV);
2029 device = (cfid >> 8) & 0x00ffff00;
2030 vendor = (u_short) cfid;
2031
2032
2033 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2034#ifdef CONFIG_ALPHA
2035
2036
2037
2038
2039
2040
2041 outb (ER1_IAM | 1, EISA_REG1);
2042 mdelay (1);
2043
2044
2045 outb (ER1_IAM, EISA_REG1);
2046 mdelay (1);
2047
2048
2049 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2050
2051
2052 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2053#endif
2054 irq = de4x5_irq[(regval >> 1) & 0x03];
2055
2056 if (is_DC2114x) {
2057 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2058 }
2059 lp->chipset = device;
2060 lp->bus = EISA;
2061
2062
2063 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2064 outl(0x00006000, PCI_CFLT);
2065 outl(iobase, PCI_CBIO);
2066
2067 DevicePresent(dev, EISA_APROM);
2068
2069 dev->irq = irq;
2070
2071 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2072 return 0;
2073 }
2074
2075 free_netdev (dev);
2076 release_reg_2:
2077 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2078 release_reg_1:
2079 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2080
2081 return status;
2082}
2083
2084static int __devexit de4x5_eisa_remove (struct device *device)
2085{
2086 struct net_device *dev;
2087 u_long iobase;
2088
2089 dev = dev_get_drvdata(device);
2090 iobase = dev->base_addr;
2091
2092 unregister_netdev (dev);
2093 free_netdev (dev);
2094 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2095 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2096
2097 return 0;
2098}
2099
2100static struct eisa_device_id de4x5_eisa_ids[] = {
2101 { "DEC4250", 0 },
2102 { "" }
2103};
2104MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2105
2106static struct eisa_driver de4x5_eisa_driver = {
2107 .id_table = de4x5_eisa_ids,
2108 .driver = {
2109 .name = "de4x5",
2110 .probe = de4x5_eisa_probe,
2111 .remove = __devexit_p (de4x5_eisa_remove),
2112 }
2113};
2114MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2115#endif
2116
2117#ifdef CONFIG_PCI
2118
2119
2120
2121
2122
2123
2124
2125static void __devinit
2126srom_search(struct net_device *dev, struct pci_dev *pdev)
2127{
2128 u_char pb;
2129 u_short vendor, status;
2130 u_int irq = 0, device;
2131 u_long iobase = 0;
2132 int i, j;
2133 struct de4x5_private *lp = netdev_priv(dev);
2134 struct list_head *walk;
2135
2136 list_for_each(walk, &pdev->bus_list) {
2137 struct pci_dev *this_dev = pci_dev_b(walk);
2138
2139
2140 if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2141
2142 vendor = this_dev->vendor;
2143 device = this_dev->device << 8;
2144 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2145
2146
2147 pb = this_dev->bus->number;
2148
2149
2150 lp->device = PCI_SLOT(this_dev->devfn);
2151 lp->bus_num = pb;
2152
2153
2154 if (is_DC2114x) {
2155 device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
2156 ? DC21142 : DC21143);
2157 }
2158 lp->chipset = device;
2159
2160
2161 iobase = pci_resource_start(this_dev, 0);
2162
2163
2164 irq = this_dev->irq;
2165 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2166
2167
2168 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2169 if (!(status & PCI_COMMAND_IO)) continue;
2170
2171
2172 DevicePresent(dev, DE4X5_APROM);
2173 for (j=0, i=0; i<ETH_ALEN; i++) {
2174 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2175 }
2176 if (j != 0 && j != 6 * 0xff) {
2177 last.chipset = device;
2178 last.bus = pb;
2179 last.irq = irq;
2180 for (i=0; i<ETH_ALEN; i++) {
2181 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2182 }
2183 return;
2184 }
2185 }
2186}
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2205 const struct pci_device_id *ent)
2206{
2207 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2208 u_short vendor, status;
2209 u_int irq = 0, device;
2210 u_long iobase = 0;
2211 int error;
2212 struct net_device *dev;
2213 struct de4x5_private *lp;
2214
2215 dev_num = PCI_SLOT(pdev->devfn);
2216 pb = pdev->bus->number;
2217
2218 if (io) {
2219 pbus = (u_short)(io >> 8);
2220 dnum = (u_short)(io & 0xff);
2221 if ((pbus != pb) || (dnum != dev_num))
2222 return -ENODEV;
2223 }
2224
2225 vendor = pdev->vendor;
2226 device = pdev->device << 8;
2227 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2228 return -ENODEV;
2229
2230
2231 if ((error = pci_enable_device (pdev)))
2232 return error;
2233
2234 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2235 error = -ENOMEM;
2236 goto disable_dev;
2237 }
2238
2239 lp = netdev_priv(dev);
2240 lp->bus = PCI;
2241 lp->bus_num = 0;
2242
2243
2244 if (lp->bus_num != pb) {
2245 lp->bus_num = pb;
2246 srom_search(dev, pdev);
2247 }
2248
2249
2250 lp->cfrv = pdev->revision;
2251
2252
2253 lp->device = dev_num;
2254 lp->bus_num = pb;
2255
2256
2257 if (is_DC2114x) {
2258 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2259 }
2260 lp->chipset = device;
2261
2262
2263 iobase = pci_resource_start(pdev, 0);
2264
2265
2266 irq = pdev->irq;
2267 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2268 error = -ENODEV;
2269 goto free_dev;
2270 }
2271
2272
2273 pci_read_config_word(pdev, PCI_COMMAND, &status);
2274#ifdef __powerpc__
2275 if (!(status & PCI_COMMAND_IO)) {
2276 status |= PCI_COMMAND_IO;
2277 pci_write_config_word(pdev, PCI_COMMAND, status);
2278 pci_read_config_word(pdev, PCI_COMMAND, &status);
2279 }
2280#endif
2281 if (!(status & PCI_COMMAND_IO)) {
2282 error = -ENODEV;
2283 goto free_dev;
2284 }
2285
2286 if (!(status & PCI_COMMAND_MASTER)) {
2287 status |= PCI_COMMAND_MASTER;
2288 pci_write_config_word(pdev, PCI_COMMAND, status);
2289 pci_read_config_word(pdev, PCI_COMMAND, &status);
2290 }
2291 if (!(status & PCI_COMMAND_MASTER)) {
2292 error = -ENODEV;
2293 goto free_dev;
2294 }
2295
2296
2297 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2298 if (timer < 0x60) {
2299 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2300 }
2301
2302 DevicePresent(dev, DE4X5_APROM);
2303
2304 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2305 error = -EBUSY;
2306 goto free_dev;
2307 }
2308
2309 dev->irq = irq;
2310
2311 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2312 goto release;
2313 }
2314
2315 return 0;
2316
2317 release:
2318 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2319 free_dev:
2320 free_netdev (dev);
2321 disable_dev:
2322 pci_disable_device (pdev);
2323 return error;
2324}
2325
2326static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2327{
2328 struct net_device *dev;
2329 u_long iobase;
2330
2331 dev = dev_get_drvdata(&pdev->dev);
2332 iobase = dev->base_addr;
2333
2334 unregister_netdev (dev);
2335 free_netdev (dev);
2336 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2337 pci_disable_device (pdev);
2338}
2339
2340static struct pci_device_id de4x5_pci_tbl[] = {
2341 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2343 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2345 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2347 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2349 { },
2350};
2351
2352static struct pci_driver de4x5_pci_driver = {
2353 .name = "de4x5",
2354 .id_table = de4x5_pci_tbl,
2355 .probe = de4x5_pci_probe,
2356 .remove = __devexit_p (de4x5_pci_remove),
2357};
2358
2359#endif
2360
2361
2362
2363
2364
2365
2366
2367
2368static int
2369autoconf_media(struct net_device *dev)
2370{
2371 struct de4x5_private *lp = netdev_priv(dev);
2372 u_long iobase = dev->base_addr;
2373
2374 disable_ast(dev);
2375
2376 lp->c_media = AUTO;
2377 inl(DE4X5_MFC);
2378 lp->media = INIT;
2379 lp->tcount = 0;
2380
2381 de4x5_ast(dev);
2382
2383 return lp->media;
2384}
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398static int
2399dc21040_autoconf(struct net_device *dev)
2400{
2401 struct de4x5_private *lp = netdev_priv(dev);
2402 u_long iobase = dev->base_addr;
2403 int next_tick = DE4X5_AUTOSENSE_MS;
2404 s32 imr;
2405
2406 switch (lp->media) {
2407 case INIT:
2408 DISABLE_IRQs;
2409 lp->tx_enable = false;
2410 lp->timeout = -1;
2411 de4x5_save_skbs(dev);
2412 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2413 lp->media = TP;
2414 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2415 lp->media = BNC_AUI;
2416 } else if (lp->autosense == EXT_SIA) {
2417 lp->media = EXT_SIA;
2418 } else {
2419 lp->media = NC;
2420 }
2421 lp->local_state = 0;
2422 next_tick = dc21040_autoconf(dev);
2423 break;
2424
2425 case TP:
2426 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2427 TP_SUSPECT, test_tp);
2428 break;
2429
2430 case TP_SUSPECT:
2431 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2432 break;
2433
2434 case BNC:
2435 case AUI:
2436 case BNC_AUI:
2437 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2438 BNC_AUI_SUSPECT, ping_media);
2439 break;
2440
2441 case BNC_AUI_SUSPECT:
2442 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2443 break;
2444
2445 case EXT_SIA:
2446 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2447 NC, EXT_SIA_SUSPECT, ping_media);
2448 break;
2449
2450 case EXT_SIA_SUSPECT:
2451 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2452 break;
2453
2454 case NC:
2455
2456 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2457 if (lp->media != lp->c_media) {
2458 de4x5_dbg_media(dev);
2459 lp->c_media = lp->media;
2460 }
2461 lp->media = INIT;
2462 lp->tx_enable = false;
2463 break;
2464 }
2465
2466 return next_tick;
2467}
2468
2469static int
2470dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2471 int next_state, int suspect_state,
2472 int (*fn)(struct net_device *, int))
2473{
2474 struct de4x5_private *lp = netdev_priv(dev);
2475 int next_tick = DE4X5_AUTOSENSE_MS;
2476 int linkBad;
2477
2478 switch (lp->local_state) {
2479 case 0:
2480 reset_init_sia(dev, csr13, csr14, csr15);
2481 lp->local_state++;
2482 next_tick = 500;
2483 break;
2484
2485 case 1:
2486 if (!lp->tx_enable) {
2487 linkBad = fn(dev, timeout);
2488 if (linkBad < 0) {
2489 next_tick = linkBad & ~TIMER_CB;
2490 } else {
2491 if (linkBad && (lp->autosense == AUTO)) {
2492 lp->local_state = 0;
2493 lp->media = next_state;
2494 } else {
2495 de4x5_init_connection(dev);
2496 }
2497 }
2498 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2499 lp->media = suspect_state;
2500 next_tick = 3000;
2501 }
2502 break;
2503 }
2504
2505 return next_tick;
2506}
2507
2508static int
2509de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2510 int (*fn)(struct net_device *, int),
2511 int (*asfn)(struct net_device *))
2512{
2513 struct de4x5_private *lp = netdev_priv(dev);
2514 int next_tick = DE4X5_AUTOSENSE_MS;
2515 int linkBad;
2516
2517 switch (lp->local_state) {
2518 case 1:
2519 if (lp->linkOK) {
2520 lp->media = prev_state;
2521 } else {
2522 lp->local_state++;
2523 next_tick = asfn(dev);
2524 }
2525 break;
2526
2527 case 2:
2528 linkBad = fn(dev, timeout);
2529 if (linkBad < 0) {
2530 next_tick = linkBad & ~TIMER_CB;
2531 } else if (!linkBad) {
2532 lp->local_state--;
2533 lp->media = prev_state;
2534 } else {
2535 lp->media = INIT;
2536 lp->tcount++;
2537 }
2538 }
2539
2540 return next_tick;
2541}
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552static int
2553dc21041_autoconf(struct net_device *dev)
2554{
2555 struct de4x5_private *lp = netdev_priv(dev);
2556 u_long iobase = dev->base_addr;
2557 s32 sts, irqs, irq_mask, imr, omr;
2558 int next_tick = DE4X5_AUTOSENSE_MS;
2559
2560 switch (lp->media) {
2561 case INIT:
2562 DISABLE_IRQs;
2563 lp->tx_enable = false;
2564 lp->timeout = -1;
2565 de4x5_save_skbs(dev);
2566 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2567 lp->media = TP;
2568 } else if (lp->autosense == TP) {
2569 lp->media = TP;
2570 } else if (lp->autosense == BNC) {
2571 lp->media = BNC;
2572 } else if (lp->autosense == AUI) {
2573 lp->media = AUI;
2574 } else {
2575 lp->media = NC;
2576 }
2577 lp->local_state = 0;
2578 next_tick = dc21041_autoconf(dev);
2579 break;
2580
2581 case TP_NW:
2582 if (lp->timeout < 0) {
2583 omr = inl(DE4X5_OMR);
2584 outl(omr | OMR_FDX, DE4X5_OMR);
2585 }
2586 irqs = STS_LNF | STS_LNP;
2587 irq_mask = IMR_LFM | IMR_LPM;
2588 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2589 if (sts < 0) {
2590 next_tick = sts & ~TIMER_CB;
2591 } else {
2592 if (sts & STS_LNP) {
2593 lp->media = ANS;
2594 } else {
2595 lp->media = AUI;
2596 }
2597 next_tick = dc21041_autoconf(dev);
2598 }
2599 break;
2600
2601 case ANS:
2602 if (!lp->tx_enable) {
2603 irqs = STS_LNP;
2604 irq_mask = IMR_LPM;
2605 sts = test_ans(dev, irqs, irq_mask, 3000);
2606 if (sts < 0) {
2607 next_tick = sts & ~TIMER_CB;
2608 } else {
2609 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2610 lp->media = TP;
2611 next_tick = dc21041_autoconf(dev);
2612 } else {
2613 lp->local_state = 1;
2614 de4x5_init_connection(dev);
2615 }
2616 }
2617 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2618 lp->media = ANS_SUSPECT;
2619 next_tick = 3000;
2620 }
2621 break;
2622
2623 case ANS_SUSPECT:
2624 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2625 break;
2626
2627 case TP:
2628 if (!lp->tx_enable) {
2629 if (lp->timeout < 0) {
2630 omr = inl(DE4X5_OMR);
2631 outl(omr & ~OMR_FDX, DE4X5_OMR);
2632 }
2633 irqs = STS_LNF | STS_LNP;
2634 irq_mask = IMR_LFM | IMR_LPM;
2635 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2636 if (sts < 0) {
2637 next_tick = sts & ~TIMER_CB;
2638 } else {
2639 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2640 if (inl(DE4X5_SISR) & SISR_NRA) {
2641 lp->media = AUI;
2642 } else {
2643 lp->media = BNC;
2644 }
2645 next_tick = dc21041_autoconf(dev);
2646 } else {
2647 lp->local_state = 1;
2648 de4x5_init_connection(dev);
2649 }
2650 }
2651 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2652 lp->media = TP_SUSPECT;
2653 next_tick = 3000;
2654 }
2655 break;
2656
2657 case TP_SUSPECT:
2658 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2659 break;
2660
2661 case AUI:
2662 if (!lp->tx_enable) {
2663 if (lp->timeout < 0) {
2664 omr = inl(DE4X5_OMR);
2665 outl(omr & ~OMR_FDX, DE4X5_OMR);
2666 }
2667 irqs = 0;
2668 irq_mask = 0;
2669 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2670 if (sts < 0) {
2671 next_tick = sts & ~TIMER_CB;
2672 } else {
2673 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2674 lp->media = BNC;
2675 next_tick = dc21041_autoconf(dev);
2676 } else {
2677 lp->local_state = 1;
2678 de4x5_init_connection(dev);
2679 }
2680 }
2681 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2682 lp->media = AUI_SUSPECT;
2683 next_tick = 3000;
2684 }
2685 break;
2686
2687 case AUI_SUSPECT:
2688 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2689 break;
2690
2691 case BNC:
2692 switch (lp->local_state) {
2693 case 0:
2694 if (lp->timeout < 0) {
2695 omr = inl(DE4X5_OMR);
2696 outl(omr & ~OMR_FDX, DE4X5_OMR);
2697 }
2698 irqs = 0;
2699 irq_mask = 0;
2700 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2701 if (sts < 0) {
2702 next_tick = sts & ~TIMER_CB;
2703 } else {
2704 lp->local_state++;
2705 next_tick = dc21041_autoconf(dev);
2706 }
2707 break;
2708
2709 case 1:
2710 if (!lp->tx_enable) {
2711 if ((sts = ping_media(dev, 3000)) < 0) {
2712 next_tick = sts & ~TIMER_CB;
2713 } else {
2714 if (sts) {
2715 lp->local_state = 0;
2716 lp->media = NC;
2717 } else {
2718 de4x5_init_connection(dev);
2719 }
2720 }
2721 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2722 lp->media = BNC_SUSPECT;
2723 next_tick = 3000;
2724 }
2725 break;
2726 }
2727 break;
2728
2729 case BNC_SUSPECT:
2730 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2731 break;
2732
2733 case NC:
2734 omr = inl(DE4X5_OMR);
2735 outl(omr | OMR_FDX, DE4X5_OMR);
2736 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);
2737 if (lp->media != lp->c_media) {
2738 de4x5_dbg_media(dev);
2739 lp->c_media = lp->media;
2740 }
2741 lp->media = INIT;
2742 lp->tx_enable = false;
2743 break;
2744 }
2745
2746 return next_tick;
2747}
2748
2749
2750
2751
2752
2753
2754static int
2755dc21140m_autoconf(struct net_device *dev)
2756{
2757 struct de4x5_private *lp = netdev_priv(dev);
2758 int ana, anlpa, cap, cr, slnk, sr;
2759 int next_tick = DE4X5_AUTOSENSE_MS;
2760 u_long imr, omr, iobase = dev->base_addr;
2761
2762 switch(lp->media) {
2763 case INIT:
2764 if (lp->timeout < 0) {
2765 DISABLE_IRQs;
2766 lp->tx_enable = false;
2767 lp->linkOK = 0;
2768 de4x5_save_skbs(dev);
2769 }
2770 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2771 next_tick &= ~TIMER_CB;
2772 } else {
2773 if (lp->useSROM) {
2774 if (srom_map_media(dev) < 0) {
2775 lp->tcount++;
2776 return next_tick;
2777 }
2778 srom_exec(dev, lp->phy[lp->active].gep);
2779 if (lp->infoblock_media == ANS) {
2780 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2781 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2782 }
2783 } else {
2784 lp->tmp = MII_SR_ASSC;
2785 SET_10Mb;
2786 if (lp->autosense == _100Mb) {
2787 lp->media = _100Mb;
2788 } else if (lp->autosense == _10Mb) {
2789 lp->media = _10Mb;
2790 } else if ((lp->autosense == AUTO) &&
2791 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2792 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2793 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2794 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2795 lp->media = ANS;
2796 } else if (lp->autosense == AUTO) {
2797 lp->media = SPD_DET;
2798 } else if (is_spd_100(dev) && is_100_up(dev)) {
2799 lp->media = _100Mb;
2800 } else {
2801 lp->media = NC;
2802 }
2803 }
2804 lp->local_state = 0;
2805 next_tick = dc21140m_autoconf(dev);
2806 }
2807 break;
2808
2809 case ANS:
2810 switch (lp->local_state) {
2811 case 0:
2812 if (lp->timeout < 0) {
2813 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2814 }
2815 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2816 if (cr < 0) {
2817 next_tick = cr & ~TIMER_CB;
2818 } else {
2819 if (cr) {
2820 lp->local_state = 0;
2821 lp->media = SPD_DET;
2822 } else {
2823 lp->local_state++;
2824 }
2825 next_tick = dc21140m_autoconf(dev);
2826 }
2827 break;
2828
2829 case 1:
2830 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000)) < 0) {
2831 next_tick = sr & ~TIMER_CB;
2832 } else {
2833 lp->media = SPD_DET;
2834 lp->local_state = 0;
2835 if (sr) {
2836 lp->tmp = MII_SR_ASSC;
2837 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2838 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2839 if (!(anlpa & MII_ANLPA_RF) &&
2840 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2841 if (cap & MII_ANA_100M) {
2842 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
2843 lp->media = _100Mb;
2844 } else if (cap & MII_ANA_10M) {
2845 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
2846
2847 lp->media = _10Mb;
2848 }
2849 }
2850 }
2851 next_tick = dc21140m_autoconf(dev);
2852 }
2853 break;
2854 }
2855 break;
2856
2857 case SPD_DET:
2858 if (lp->timeout < 0) {
2859 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2860 (~gep_rd(dev) & GEP_LNP));
2861 SET_100Mb_PDET;
2862 }
2863 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2864 next_tick = slnk & ~TIMER_CB;
2865 } else {
2866 if (is_spd_100(dev) && is_100_up(dev)) {
2867 lp->media = _100Mb;
2868 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2869 lp->media = _10Mb;
2870 } else {
2871 lp->media = NC;
2872 }
2873 next_tick = dc21140m_autoconf(dev);
2874 }
2875 break;
2876
2877 case _100Mb:
2878 next_tick = 3000;
2879 if (!lp->tx_enable) {
2880 SET_100Mb;
2881 de4x5_init_connection(dev);
2882 } else {
2883 if (!lp->linkOK && (lp->autosense == AUTO)) {
2884 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2885 lp->media = INIT;
2886 lp->tcount++;
2887 next_tick = DE4X5_AUTOSENSE_MS;
2888 }
2889 }
2890 }
2891 break;
2892
2893 case BNC:
2894 case AUI:
2895 case _10Mb:
2896 next_tick = 3000;
2897 if (!lp->tx_enable) {
2898 SET_10Mb;
2899 de4x5_init_connection(dev);
2900 } else {
2901 if (!lp->linkOK && (lp->autosense == AUTO)) {
2902 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2903 lp->media = INIT;
2904 lp->tcount++;
2905 next_tick = DE4X5_AUTOSENSE_MS;
2906 }
2907 }
2908 }
2909 break;
2910
2911 case NC:
2912 if (lp->media != lp->c_media) {
2913 de4x5_dbg_media(dev);
2914 lp->c_media = lp->media;
2915 }
2916 lp->media = INIT;
2917 lp->tx_enable = false;
2918 break;
2919 }
2920
2921 return next_tick;
2922}
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938static int
2939dc2114x_autoconf(struct net_device *dev)
2940{
2941 struct de4x5_private *lp = netdev_priv(dev);
2942 u_long iobase = dev->base_addr;
2943 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2944 int next_tick = DE4X5_AUTOSENSE_MS;
2945
2946 switch (lp->media) {
2947 case INIT:
2948 if (lp->timeout < 0) {
2949 DISABLE_IRQs;
2950 lp->tx_enable = false;
2951 lp->linkOK = 0;
2952 lp->timeout = -1;
2953 de4x5_save_skbs(dev);
2954 if (lp->params.autosense & ~AUTO) {
2955 srom_map_media(dev);
2956 if (lp->media != lp->params.autosense) {
2957 lp->tcount++;
2958 lp->media = INIT;
2959 return next_tick;
2960 }
2961 lp->media = INIT;
2962 }
2963 }
2964 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2965 next_tick &= ~TIMER_CB;
2966 } else {
2967 if (lp->autosense == _100Mb) {
2968 lp->media = _100Mb;
2969 } else if (lp->autosense == _10Mb) {
2970 lp->media = _10Mb;
2971 } else if (lp->autosense == TP) {
2972 lp->media = TP;
2973 } else if (lp->autosense == BNC) {
2974 lp->media = BNC;
2975 } else if (lp->autosense == AUI) {
2976 lp->media = AUI;
2977 } else {
2978 lp->media = SPD_DET;
2979 if ((lp->infoblock_media == ANS) &&
2980 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2981 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2982 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2983 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2984 lp->media = ANS;
2985 }
2986 }
2987 lp->local_state = 0;
2988 next_tick = dc2114x_autoconf(dev);
2989 }
2990 break;
2991
2992 case ANS:
2993 switch (lp->local_state) {
2994 case 0:
2995 if (lp->timeout < 0) {
2996 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2997 }
2998 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2999 if (cr < 0) {
3000 next_tick = cr & ~TIMER_CB;
3001 } else {
3002 if (cr) {
3003 lp->local_state = 0;
3004 lp->media = SPD_DET;
3005 } else {
3006 lp->local_state++;
3007 }
3008 next_tick = dc2114x_autoconf(dev);
3009 }
3010 break;
3011
3012 case 1:
3013 sr = test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000);
3014 if (sr < 0) {
3015 next_tick = sr & ~TIMER_CB;
3016 } else {
3017 lp->media = SPD_DET;
3018 lp->local_state = 0;
3019 if (sr) {
3020 lp->tmp = MII_SR_ASSC;
3021 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3022 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3023 if (!(anlpa & MII_ANLPA_RF) &&
3024 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3025 if (cap & MII_ANA_100M) {
3026 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
3027 lp->media = _100Mb;
3028 } else if (cap & MII_ANA_10M) {
3029 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
3030 lp->media = _10Mb;
3031 }
3032 }
3033 }
3034 next_tick = dc2114x_autoconf(dev);
3035 }
3036 break;
3037 }
3038 break;
3039
3040 case AUI:
3041 if (!lp->tx_enable) {
3042 if (lp->timeout < 0) {
3043 omr = inl(DE4X5_OMR);
3044 outl(omr & ~OMR_FDX, DE4X5_OMR);
3045 }
3046 irqs = 0;
3047 irq_mask = 0;
3048 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3049 if (sts < 0) {
3050 next_tick = sts & ~TIMER_CB;
3051 } else {
3052 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3053 lp->media = BNC;
3054 next_tick = dc2114x_autoconf(dev);
3055 } else {
3056 lp->local_state = 1;
3057 de4x5_init_connection(dev);
3058 }
3059 }
3060 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3061 lp->media = AUI_SUSPECT;
3062 next_tick = 3000;
3063 }
3064 break;
3065
3066 case AUI_SUSPECT:
3067 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3068 break;
3069
3070 case BNC:
3071 switch (lp->local_state) {
3072 case 0:
3073 if (lp->timeout < 0) {
3074 omr = inl(DE4X5_OMR);
3075 outl(omr & ~OMR_FDX, DE4X5_OMR);
3076 }
3077 irqs = 0;
3078 irq_mask = 0;
3079 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3080 if (sts < 0) {
3081 next_tick = sts & ~TIMER_CB;
3082 } else {
3083 lp->local_state++;
3084 next_tick = dc2114x_autoconf(dev);
3085 }
3086 break;
3087
3088 case 1:
3089 if (!lp->tx_enable) {
3090 if ((sts = ping_media(dev, 3000)) < 0) {
3091 next_tick = sts & ~TIMER_CB;
3092 } else {
3093 if (sts) {
3094 lp->local_state = 0;
3095 lp->tcount++;
3096 lp->media = INIT;
3097 } else {
3098 de4x5_init_connection(dev);
3099 }
3100 }
3101 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3102 lp->media = BNC_SUSPECT;
3103 next_tick = 3000;
3104 }
3105 break;
3106 }
3107 break;
3108
3109 case BNC_SUSPECT:
3110 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3111 break;
3112
3113 case SPD_DET:
3114 if (srom_map_media(dev) < 0) {
3115 lp->tcount++;
3116 lp->media = INIT;
3117 return next_tick;
3118 }
3119 if (lp->media == _100Mb) {
3120 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3121 lp->media = SPD_DET;
3122 return slnk & ~TIMER_CB;
3123 }
3124 } else {
3125 if (wait_for_link(dev) < 0) {
3126 lp->media = SPD_DET;
3127 return PDET_LINK_WAIT;
3128 }
3129 }
3130 if (lp->media == ANS) {
3131 if (is_spd_100(dev)) {
3132 lp->media = _100Mb;
3133 } else {
3134 lp->media = _10Mb;
3135 }
3136 next_tick = dc2114x_autoconf(dev);
3137 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3138 (((lp->media == _10Mb) || (lp->media == TP) ||
3139 (lp->media == BNC) || (lp->media == AUI)) &&
3140 is_10_up(dev))) {
3141 next_tick = dc2114x_autoconf(dev);
3142 } else {
3143 lp->tcount++;
3144 lp->media = INIT;
3145 }
3146 break;
3147
3148 case _10Mb:
3149 next_tick = 3000;
3150 if (!lp->tx_enable) {
3151 SET_10Mb;
3152 de4x5_init_connection(dev);
3153 } else {
3154 if (!lp->linkOK && (lp->autosense == AUTO)) {
3155 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3156 lp->media = INIT;
3157 lp->tcount++;
3158 next_tick = DE4X5_AUTOSENSE_MS;
3159 }
3160 }
3161 }
3162 break;
3163
3164 case _100Mb:
3165 next_tick = 3000;
3166 if (!lp->tx_enable) {
3167 SET_100Mb;
3168 de4x5_init_connection(dev);
3169 } else {
3170 if (!lp->linkOK && (lp->autosense == AUTO)) {
3171 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3172 lp->media = INIT;
3173 lp->tcount++;
3174 next_tick = DE4X5_AUTOSENSE_MS;
3175 }
3176 }
3177 }
3178 break;
3179
3180 default:
3181 lp->tcount++;
3182printk("Huh?: media:%02x\n", lp->media);
3183 lp->media = INIT;
3184 break;
3185 }
3186
3187 return next_tick;
3188}
3189
3190static int
3191srom_autoconf(struct net_device *dev)
3192{
3193 struct de4x5_private *lp = netdev_priv(dev);
3194
3195 return lp->infoleaf_fn(dev);
3196}
3197
3198
3199
3200
3201
3202
3203static int
3204srom_map_media(struct net_device *dev)
3205{
3206 struct de4x5_private *lp = netdev_priv(dev);
3207
3208 lp->fdx = false;
3209 if (lp->infoblock_media == lp->media)
3210 return 0;
3211
3212 switch(lp->infoblock_media) {
3213 case SROM_10BASETF:
3214 if (!lp->params.fdx) return -1;
3215 lp->fdx = true;
3216 case SROM_10BASET:
3217 if (lp->params.fdx && !lp->fdx) return -1;
3218 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3219 lp->media = _10Mb;
3220 } else {
3221 lp->media = TP;
3222 }
3223 break;
3224
3225 case SROM_10BASE2:
3226 lp->media = BNC;
3227 break;
3228
3229 case SROM_10BASE5:
3230 lp->media = AUI;
3231 break;
3232
3233 case SROM_100BASETF:
3234 if (!lp->params.fdx) return -1;
3235 lp->fdx = true;
3236 case SROM_100BASET:
3237 if (lp->params.fdx && !lp->fdx) return -1;
3238 lp->media = _100Mb;
3239 break;
3240
3241 case SROM_100BASET4:
3242 lp->media = _100Mb;
3243 break;
3244
3245 case SROM_100BASEFF:
3246 if (!lp->params.fdx) return -1;
3247 lp->fdx = true;
3248 case SROM_100BASEF:
3249 if (lp->params.fdx && !lp->fdx) return -1;
3250 lp->media = _100Mb;
3251 break;
3252
3253 case ANS:
3254 lp->media = ANS;
3255 lp->fdx = lp->params.fdx;
3256 break;
3257
3258 default:
3259 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3260 lp->infoblock_media);
3261 return -1;
3262 break;
3263 }
3264
3265 return 0;
3266}
3267
3268static void
3269de4x5_init_connection(struct net_device *dev)
3270{
3271 struct de4x5_private *lp = netdev_priv(dev);
3272 u_long iobase = dev->base_addr;
3273 u_long flags = 0;
3274
3275 if (lp->media != lp->c_media) {
3276 de4x5_dbg_media(dev);
3277 lp->c_media = lp->media;
3278 }
3279
3280 spin_lock_irqsave(&lp->lock, flags);
3281 de4x5_rst_desc_ring(dev);
3282 de4x5_setup_intr(dev);
3283 lp->tx_enable = true;
3284 spin_unlock_irqrestore(&lp->lock, flags);
3285 outl(POLL_DEMAND, DE4X5_TPD);
3286
3287 netif_wake_queue(dev);
3288}
3289
3290
3291
3292
3293
3294
3295static int
3296de4x5_reset_phy(struct net_device *dev)
3297{
3298 struct de4x5_private *lp = netdev_priv(dev);
3299 u_long iobase = dev->base_addr;
3300 int next_tick = 0;
3301
3302 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3303 if (lp->timeout < 0) {
3304 if (lp->useSROM) {
3305 if (lp->phy[lp->active].rst) {
3306 srom_exec(dev, lp->phy[lp->active].rst);
3307 srom_exec(dev, lp->phy[lp->active].rst);
3308 } else if (lp->rst) {
3309 srom_exec(dev, lp->rst);
3310 srom_exec(dev, lp->rst);
3311 }
3312 } else {
3313 PHY_HARD_RESET;
3314 }
3315 if (lp->useMII) {
3316 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3317 }
3318 }
3319 if (lp->useMII) {
3320 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, false, 500);
3321 }
3322 } else if (lp->chipset == DC21140) {
3323 PHY_HARD_RESET;
3324 }
3325
3326 return next_tick;
3327}
3328
3329static int
3330test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3331{
3332 struct de4x5_private *lp = netdev_priv(dev);
3333 u_long iobase = dev->base_addr;
3334 s32 sts, csr12;
3335
3336 if (lp->timeout < 0) {
3337 lp->timeout = msec/100;
3338 if (!lp->useSROM) {
3339 reset_init_sia(dev, csr13, csr14, csr15);
3340 }
3341
3342
3343 outl(irq_mask, DE4X5_IMR);
3344
3345
3346 sts = inl(DE4X5_STS);
3347 outl(sts, DE4X5_STS);
3348
3349
3350 if ((lp->chipset == DC21041) || lp->useSROM) {
3351 csr12 = inl(DE4X5_SISR);
3352 outl(csr12, DE4X5_SISR);
3353 }
3354 }
3355
3356 sts = inl(DE4X5_STS) & ~TIMER_CB;
3357
3358 if (!(sts & irqs) && --lp->timeout) {
3359 sts = 100 | TIMER_CB;
3360 } else {
3361 lp->timeout = -1;
3362 }
3363
3364 return sts;
3365}
3366
3367static int
3368test_tp(struct net_device *dev, s32 msec)
3369{
3370 struct de4x5_private *lp = netdev_priv(dev);
3371 u_long iobase = dev->base_addr;
3372 int sisr;
3373
3374 if (lp->timeout < 0) {
3375 lp->timeout = msec/100;
3376 }
3377
3378 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3379
3380 if (sisr && --lp->timeout) {
3381 sisr = 100 | TIMER_CB;
3382 } else {
3383 lp->timeout = -1;
3384 }
3385
3386 return sisr;
3387}
3388
3389
3390
3391
3392
3393
3394#define SAMPLE_INTERVAL 500
3395#define SAMPLE_DELAY 2000
3396static int
3397test_for_100Mb(struct net_device *dev, int msec)
3398{
3399 struct de4x5_private *lp = netdev_priv(dev);
3400 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3401
3402 if (lp->timeout < 0) {
3403 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3404 if (msec > SAMPLE_DELAY) {
3405 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3406 gep = SAMPLE_DELAY | TIMER_CB;
3407 return gep;
3408 } else {
3409 lp->timeout = msec/SAMPLE_INTERVAL;
3410 }
3411 }
3412
3413 if (lp->phy[lp->active].id || lp->useSROM) {
3414 gep = is_100_up(dev) | is_spd_100(dev);
3415 } else {
3416 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3417 }
3418 if (!(gep & ret) && --lp->timeout) {
3419 gep = SAMPLE_INTERVAL | TIMER_CB;
3420 } else {
3421 lp->timeout = -1;
3422 }
3423
3424 return gep;
3425}
3426
3427static int
3428wait_for_link(struct net_device *dev)
3429{
3430 struct de4x5_private *lp = netdev_priv(dev);
3431
3432 if (lp->timeout < 0) {
3433 lp->timeout = 1;
3434 }
3435
3436 if (lp->timeout--) {
3437 return TIMER_CB;
3438 } else {
3439 lp->timeout = -1;
3440 }
3441
3442 return 0;
3443}
3444
3445
3446
3447
3448
3449static int
3450test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec)
3451{
3452 struct de4x5_private *lp = netdev_priv(dev);
3453 int test;
3454 u_long iobase = dev->base_addr;
3455
3456 if (lp->timeout < 0) {
3457 lp->timeout = msec/100;
3458 }
3459
3460 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3461 test = (reg ^ (pol ? ~0 : 0)) & mask;
3462
3463 if (test && --lp->timeout) {
3464 reg = 100 | TIMER_CB;
3465 } else {
3466 lp->timeout = -1;
3467 }
3468
3469 return reg;
3470}
3471
3472static int
3473is_spd_100(struct net_device *dev)
3474{
3475 struct de4x5_private *lp = netdev_priv(dev);
3476 u_long iobase = dev->base_addr;
3477 int spd;
3478
3479 if (lp->useMII) {
3480 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3481 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3482 spd &= lp->phy[lp->active].spd.mask;
3483 } else if (!lp->useSROM) {
3484 spd = ((~gep_rd(dev)) & GEP_SLNK);
3485 } else {
3486 if ((lp->ibn == 2) || !lp->asBitValid)
3487 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3488
3489 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3490 (lp->linkOK & ~lp->asBitValid);
3491 }
3492
3493 return spd;
3494}
3495
3496static int
3497is_100_up(struct net_device *dev)
3498{
3499 struct de4x5_private *lp = netdev_priv(dev);
3500 u_long iobase = dev->base_addr;
3501
3502 if (lp->useMII) {
3503
3504 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3505 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3506 } else if (!lp->useSROM) {
3507 return (~gep_rd(dev)) & GEP_SLNK;
3508 } else {
3509 if ((lp->ibn == 2) || !lp->asBitValid)
3510 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3511
3512 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3513 (lp->linkOK & ~lp->asBitValid);
3514 }
3515}
3516
3517static int
3518is_10_up(struct net_device *dev)
3519{
3520 struct de4x5_private *lp = netdev_priv(dev);
3521 u_long iobase = dev->base_addr;
3522
3523 if (lp->useMII) {
3524
3525 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3526 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3527 } else if (!lp->useSROM) {
3528 return (~gep_rd(dev)) & GEP_LNP;
3529 } else {
3530 if ((lp->ibn == 2) || !lp->asBitValid)
3531 return ((lp->chipset & ~0x00ff) == DC2114x) ?
3532 (~inl(DE4X5_SISR)&SISR_LS10):
3533 0;
3534
3535 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3536 (lp->linkOK & ~lp->asBitValid);
3537 }
3538}
3539
3540static int
3541is_anc_capable(struct net_device *dev)
3542{
3543 struct de4x5_private *lp = netdev_priv(dev);
3544 u_long iobase = dev->base_addr;
3545
3546 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3547 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3548 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3549 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3550 } else {
3551 return 0;
3552 }
3553}
3554
3555
3556
3557
3558
3559static int
3560ping_media(struct net_device *dev, int msec)
3561{
3562 struct de4x5_private *lp = netdev_priv(dev);
3563 u_long iobase = dev->base_addr;
3564 int sisr;
3565
3566 if (lp->timeout < 0) {
3567 lp->timeout = msec/100;
3568
3569 lp->tmp = lp->tx_new;
3570 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3571 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
3572 outl(POLL_DEMAND, DE4X5_TPD);
3573 }
3574
3575 sisr = inl(DE4X5_SISR);
3576
3577 if ((!(sisr & SISR_NCR)) &&
3578 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3579 (--lp->timeout)) {
3580 sisr = 100 | TIMER_CB;
3581 } else {
3582 if ((!(sisr & SISR_NCR)) &&
3583 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3584 lp->timeout) {
3585 sisr = 0;
3586 } else {
3587 sisr = 1;
3588 }
3589 lp->timeout = -1;
3590 }
3591
3592 return sisr;
3593}
3594
3595
3596
3597
3598
3599
3600static struct sk_buff *
3601de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3602{
3603 struct de4x5_private *lp = netdev_priv(dev);
3604 struct sk_buff *p;
3605
3606#if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
3607 struct sk_buff *ret;
3608 u_long i=0, tmp;
3609
3610 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3611 if (!p) return NULL;
3612
3613 tmp = virt_to_bus(p->data);
3614 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3615 skb_reserve(p, i);
3616 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3617
3618 ret = lp->rx_skb[index];
3619 lp->rx_skb[index] = p;
3620
3621 if ((u_long) ret > 1) {
3622 skb_put(ret, len);
3623 }
3624
3625 return ret;
3626
3627#else
3628 if (lp->state != OPEN) return (struct sk_buff *)1;
3629
3630 p = dev_alloc_skb(len + 2);
3631 if (!p) return NULL;
3632
3633 skb_reserve(p, 2);
3634 if (index < lp->rx_old) {
3635 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3636 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3637 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3638 } else {
3639 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3640 }
3641
3642 return p;
3643#endif
3644}
3645
3646static void
3647de4x5_free_rx_buffs(struct net_device *dev)
3648{
3649 struct de4x5_private *lp = netdev_priv(dev);
3650 int i;
3651
3652 for (i=0; i<lp->rxRingSize; i++) {
3653 if ((u_long) lp->rx_skb[i] > 1) {
3654 dev_kfree_skb(lp->rx_skb[i]);
3655 }
3656 lp->rx_ring[i].status = 0;
3657 lp->rx_skb[i] = (struct sk_buff *)1;
3658 }
3659}
3660
3661static void
3662de4x5_free_tx_buffs(struct net_device *dev)
3663{
3664 struct de4x5_private *lp = netdev_priv(dev);
3665 int i;
3666
3667 for (i=0; i<lp->txRingSize; i++) {
3668 if (lp->tx_skb[i])
3669 de4x5_free_tx_buff(lp, i);
3670 lp->tx_ring[i].status = 0;
3671 }
3672
3673
3674 __skb_queue_purge(&lp->cache.queue);
3675}
3676
3677
3678
3679
3680
3681
3682
3683
3684static void
3685de4x5_save_skbs(struct net_device *dev)
3686{
3687 struct de4x5_private *lp = netdev_priv(dev);
3688 u_long iobase = dev->base_addr;
3689 s32 omr;
3690
3691 if (!lp->cache.save_cnt) {
3692 STOP_DE4X5;
3693 de4x5_tx(dev);
3694 de4x5_free_tx_buffs(dev);
3695 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3696 de4x5_sw_reset(dev);
3697 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3698 lp->cache.save_cnt++;
3699 START_DE4X5;
3700 }
3701}
3702
3703static void
3704de4x5_rst_desc_ring(struct net_device *dev)
3705{
3706 struct de4x5_private *lp = netdev_priv(dev);
3707 u_long iobase = dev->base_addr;
3708 int i;
3709 s32 omr;
3710
3711 if (lp->cache.save_cnt) {
3712 STOP_DE4X5;
3713 outl(lp->dma_rings, DE4X5_RRBA);
3714 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3715 DE4X5_TRBA);
3716
3717 lp->rx_new = lp->rx_old = 0;
3718 lp->tx_new = lp->tx_old = 0;
3719
3720 for (i = 0; i < lp->rxRingSize; i++) {
3721 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3722 }
3723
3724 for (i = 0; i < lp->txRingSize; i++) {
3725 lp->tx_ring[i].status = cpu_to_le32(0);
3726 }
3727
3728 barrier();
3729 lp->cache.save_cnt--;
3730 START_DE4X5;
3731 }
3732}
3733
3734static void
3735de4x5_cache_state(struct net_device *dev, int flag)
3736{
3737 struct de4x5_private *lp = netdev_priv(dev);
3738 u_long iobase = dev->base_addr;
3739
3740 switch(flag) {
3741 case DE4X5_SAVE_STATE:
3742 lp->cache.csr0 = inl(DE4X5_BMR);
3743 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3744 lp->cache.csr7 = inl(DE4X5_IMR);
3745 break;
3746
3747 case DE4X5_RESTORE_STATE:
3748 outl(lp->cache.csr0, DE4X5_BMR);
3749 outl(lp->cache.csr6, DE4X5_OMR);
3750 outl(lp->cache.csr7, DE4X5_IMR);
3751 if (lp->chipset == DC21140) {
3752 gep_wr(lp->cache.gepc, dev);
3753 gep_wr(lp->cache.gep, dev);
3754 } else {
3755 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3756 lp->cache.csr15);
3757 }
3758 break;
3759 }
3760}
3761
3762static void
3763de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3764{
3765 struct de4x5_private *lp = netdev_priv(dev);
3766
3767 __skb_queue_tail(&lp->cache.queue, skb);
3768}
3769
3770static void
3771de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3772{
3773 struct de4x5_private *lp = netdev_priv(dev);
3774
3775 __skb_queue_head(&lp->cache.queue, skb);
3776}
3777
3778static struct sk_buff *
3779de4x5_get_cache(struct net_device *dev)
3780{
3781 struct de4x5_private *lp = netdev_priv(dev);
3782
3783 return __skb_dequeue(&lp->cache.queue);
3784}
3785
3786
3787
3788
3789
3790static int
3791test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3792{
3793 struct de4x5_private *lp = netdev_priv(dev);
3794 u_long iobase = dev->base_addr;
3795 s32 sts, ans;
3796
3797 if (lp->timeout < 0) {
3798 lp->timeout = msec/100;
3799 outl(irq_mask, DE4X5_IMR);
3800
3801
3802 sts = inl(DE4X5_STS);
3803 outl(sts, DE4X5_STS);
3804 }
3805
3806 ans = inl(DE4X5_SISR) & SISR_ANS;
3807 sts = inl(DE4X5_STS) & ~TIMER_CB;
3808
3809 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3810 sts = 100 | TIMER_CB;
3811 } else {
3812 lp->timeout = -1;
3813 }
3814
3815 return sts;
3816}
3817
3818static void
3819de4x5_setup_intr(struct net_device *dev)
3820{
3821 struct de4x5_private *lp = netdev_priv(dev);
3822 u_long iobase = dev->base_addr;
3823 s32 imr, sts;
3824
3825 if (inl(DE4X5_OMR) & OMR_SR) {
3826 imr = 0;
3827 UNMASK_IRQs;
3828 sts = inl(DE4X5_STS);
3829 outl(sts, DE4X5_STS);
3830 ENABLE_IRQs;
3831 }
3832}
3833
3834
3835
3836
3837static void
3838reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3839{
3840 struct de4x5_private *lp = netdev_priv(dev);
3841 u_long iobase = dev->base_addr;
3842
3843 RESET_SIA;
3844 if (lp->useSROM) {
3845 if (lp->ibn == 3) {
3846 srom_exec(dev, lp->phy[lp->active].rst);
3847 srom_exec(dev, lp->phy[lp->active].gep);
3848 outl(1, DE4X5_SICR);
3849 return;
3850 } else {
3851 csr15 = lp->cache.csr15;
3852 csr14 = lp->cache.csr14;
3853 csr13 = lp->cache.csr13;
3854 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3855 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3856 }
3857 } else {
3858 outl(csr15, DE4X5_SIGR);
3859 }
3860 outl(csr14, DE4X5_STRR);
3861 outl(csr13, DE4X5_SICR);
3862
3863 mdelay(10);
3864}
3865
3866
3867
3868
3869static void
3870create_packet(struct net_device *dev, char *frame, int len)
3871{
3872 int i;
3873 char *buf = frame;
3874
3875 for (i=0; i<ETH_ALEN; i++) {
3876 *buf++ = dev->dev_addr[i];
3877 }
3878 for (i=0; i<ETH_ALEN; i++) {
3879 *buf++ = dev->dev_addr[i];
3880 }
3881
3882 *buf++ = 0;
3883 *buf++ = 1;
3884}
3885
3886
3887
3888
3889static int
3890EISA_signature(char *name, struct device *device)
3891{
3892 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3893 struct eisa_device *edev;
3894
3895 *name = '\0';
3896 edev = to_eisa_device (device);
3897 i = edev->id.driver_data;
3898
3899 if (i >= 0 && i < siglen) {
3900 strcpy (name, de4x5_signatures[i]);
3901 status = 1;
3902 }
3903
3904 return status;
3905}
3906
3907
3908
3909
3910static int
3911PCI_signature(char *name, struct de4x5_private *lp)
3912{
3913 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3914
3915 if (lp->chipset == DC21040) {
3916 strcpy(name, "DE434/5");
3917 return status;
3918 } else {
3919 int tmp = *((char *)&lp->srom + 19) * 3;
3920 strncpy(name, (char *)&lp->srom + 26 + tmp, 8);
3921 }
3922 name[8] = '\0';
3923 for (i=0; i<siglen; i++) {
3924 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3925 }
3926 if (i == siglen) {
3927 if (dec_only) {
3928 *name = '\0';
3929 } else {
3930 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3931 ((lp->chipset == DC21041) ? "DC21041" :
3932 ((lp->chipset == DC21140) ? "DC21140" :
3933 ((lp->chipset == DC21142) ? "DC21142" :
3934 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3935 )))))));
3936 }
3937 if (lp->chipset != DC21041) {
3938 lp->useSROM = true;
3939 }
3940 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3941 lp->useSROM = true;
3942 }
3943
3944 return status;
3945}
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955static void
3956DevicePresent(struct net_device *dev, u_long aprom_addr)
3957{
3958 int i, j=0;
3959 struct de4x5_private *lp = netdev_priv(dev);
3960
3961 if (lp->chipset == DC21040) {
3962 if (lp->bus == EISA) {
3963 enet_addr_rst(aprom_addr);
3964 } else {
3965 outl(0, aprom_addr);
3966 }
3967 } else {
3968 u_short tmp;
3969 __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD);
3970 for (i=0; i<(ETH_ALEN>>1); i++) {
3971 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
3972 j += tmp;
3973 *p = cpu_to_le16(tmp);
3974 }
3975 if (j == 0 || j == 3 * 0xffff) {
3976
3977 return;
3978 }
3979
3980 p = (__le16 *)&lp->srom;
3981 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
3982 tmp = srom_rd(aprom_addr, i);
3983 *p++ = cpu_to_le16(tmp);
3984 }
3985 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
3986 }
3987}
3988
3989
3990
3991
3992
3993
3994static void
3995enet_addr_rst(u_long aprom_addr)
3996{
3997 union {
3998 struct {
3999 u32 a;
4000 u32 b;
4001 } llsig;
4002 char Sig[sizeof(u32) << 1];
4003 } dev;
4004 short sigLength=0;
4005 s8 data;
4006 int i, j;
4007
4008 dev.llsig.a = ETH_PROM_SIG;
4009 dev.llsig.b = ETH_PROM_SIG;
4010 sigLength = sizeof(u32) << 1;
4011
4012 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4013 data = inb(aprom_addr);
4014 if (dev.Sig[j] == data) {
4015 j++;
4016 } else {
4017 if (data == dev.Sig[0]) {
4018 j=1;
4019 } else {
4020 j=0;
4021 }
4022 }
4023 }
4024}
4025
4026
4027
4028
4029
4030
4031
4032static int
4033get_hw_addr(struct net_device *dev)
4034{
4035 u_long iobase = dev->base_addr;
4036 int broken, i, k, tmp, status = 0;
4037 u_short j,chksum;
4038 struct de4x5_private *lp = netdev_priv(dev);
4039
4040 broken = de4x5_bad_srom(lp);
4041
4042 for (i=0,k=0,j=0;j<3;j++) {
4043 k <<= 1;
4044 if (k > 0xffff) k-=0xffff;
4045
4046 if (lp->bus == PCI) {
4047 if (lp->chipset == DC21040) {
4048 while ((tmp = inl(DE4X5_APROM)) < 0);
4049 k += (u_char) tmp;
4050 dev->dev_addr[i++] = (u_char) tmp;
4051 while ((tmp = inl(DE4X5_APROM)) < 0);
4052 k += (u_short) (tmp << 8);
4053 dev->dev_addr[i++] = (u_char) tmp;
4054 } else if (!broken) {
4055 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4056 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4057 } else if ((broken == SMC) || (broken == ACCTON)) {
4058 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4059 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4060 }
4061 } else {
4062 k += (u_char) (tmp = inb(EISA_APROM));
4063 dev->dev_addr[i++] = (u_char) tmp;
4064 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4065 dev->dev_addr[i++] = (u_char) tmp;
4066 }
4067
4068 if (k > 0xffff) k-=0xffff;
4069 }
4070 if (k == 0xffff) k=0;
4071
4072 if (lp->bus == PCI) {
4073 if (lp->chipset == DC21040) {
4074 while ((tmp = inl(DE4X5_APROM)) < 0);
4075 chksum = (u_char) tmp;
4076 while ((tmp = inl(DE4X5_APROM)) < 0);
4077 chksum |= (u_short) (tmp << 8);
4078 if ((k != chksum) && (dec_only)) status = -1;
4079 }
4080 } else {
4081 chksum = (u_char) inb(EISA_APROM);
4082 chksum |= (u_short) (inb(EISA_APROM) << 8);
4083 if ((k != chksum) && (dec_only)) status = -1;
4084 }
4085
4086
4087 srom_repair(dev, broken);
4088
4089#ifdef CONFIG_PPC_PMAC
4090
4091
4092
4093
4094 if ( machine_is(powermac) &&
4095 (dev->dev_addr[0] == 0) &&
4096 (dev->dev_addr[1] == 0xa0) )
4097 {
4098 for (i = 0; i < ETH_ALEN; ++i)
4099 {
4100 int x = dev->dev_addr[i];
4101 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4102 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4103 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4104 }
4105 }
4106#endif
4107
4108
4109 status = test_bad_enet(dev, status);
4110
4111 return status;
4112}
4113
4114
4115
4116
4117
4118static int
4119de4x5_bad_srom(struct de4x5_private *lp)
4120{
4121 int i, status = 0;
4122
4123 for (i = 0; i < ARRAY_SIZE(enet_det); i++) {
4124 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4125 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4126 if (i == 0) {
4127 status = SMC;
4128 } else if (i == 1) {
4129 status = ACCTON;
4130 }
4131 break;
4132 }
4133 }
4134
4135 return status;
4136}
4137
4138static int
4139de4x5_strncmp(char *a, char *b, int n)
4140{
4141 int ret=0;
4142
4143 for (;n && !ret; n--) {
4144 ret = *a++ - *b++;
4145 }
4146
4147 return ret;
4148}
4149
4150static void
4151srom_repair(struct net_device *dev, int card)
4152{
4153 struct de4x5_private *lp = netdev_priv(dev);
4154
4155 switch(card) {
4156 case SMC:
4157 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4158 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4159 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4160 lp->useSROM = true;
4161 break;
4162 }
4163}
4164
4165
4166
4167
4168
4169static int
4170test_bad_enet(struct net_device *dev, int status)
4171{
4172 struct de4x5_private *lp = netdev_priv(dev);
4173 int i, tmp;
4174
4175 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4176 if ((tmp == 0) || (tmp == 0x5fa)) {
4177 if ((lp->chipset == last.chipset) &&
4178 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4179 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4180 for (i=ETH_ALEN-1; i>2; --i) {
4181 dev->dev_addr[i] += 1;
4182 if (dev->dev_addr[i] != 0) break;
4183 }
4184 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4185 if (!an_exception(lp)) {
4186 dev->irq = last.irq;
4187 }
4188
4189 status = 0;
4190 }
4191 } else if (!status) {
4192 last.chipset = lp->chipset;
4193 last.bus = lp->bus_num;
4194 last.irq = dev->irq;
4195 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4196 }
4197
4198 return status;
4199}
4200
4201
4202
4203
4204static int
4205an_exception(struct de4x5_private *lp)
4206{
4207 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4208 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4209 return -1;
4210 }
4211
4212 return 0;
4213}
4214
4215
4216
4217
4218static short
4219srom_rd(u_long addr, u_char offset)
4220{
4221 sendto_srom(SROM_RD | SROM_SR, addr);
4222
4223 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4224 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4225 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4226
4227 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4228}
4229
4230static void
4231srom_latch(u_int command, u_long addr)
4232{
4233 sendto_srom(command, addr);
4234 sendto_srom(command | DT_CLK, addr);
4235 sendto_srom(command, addr);
4236}
4237
4238static void
4239srom_command(u_int command, u_long addr)
4240{
4241 srom_latch(command, addr);
4242 srom_latch(command, addr);
4243 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4244}
4245
4246static void
4247srom_address(u_int command, u_long addr, u_char offset)
4248{
4249 int i, a;
4250
4251 a = offset << 2;
4252 for (i=0; i<6; i++, a <<= 1) {
4253 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4254 }
4255 udelay(1);
4256
4257 i = (getfrom_srom(addr) >> 3) & 0x01;
4258}
4259
4260static short
4261srom_data(u_int command, u_long addr)
4262{
4263 int i;
4264 short word = 0;
4265 s32 tmp;
4266
4267 for (i=0; i<16; i++) {
4268 sendto_srom(command | DT_CLK, addr);
4269 tmp = getfrom_srom(addr);
4270 sendto_srom(command, addr);
4271
4272 word = (word << 1) | ((tmp >> 3) & 0x01);
4273 }
4274
4275 sendto_srom(command & 0x0000ff00, addr);
4276
4277 return word;
4278}
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294static void
4295sendto_srom(u_int command, u_long addr)
4296{
4297 outl(command, addr);
4298 udelay(1);
4299}
4300
4301static int
4302getfrom_srom(u_long addr)
4303{
4304 s32 tmp;
4305
4306 tmp = inl(addr);
4307 udelay(1);
4308
4309 return tmp;
4310}
4311
4312static int
4313srom_infoleaf_info(struct net_device *dev)
4314{
4315 struct de4x5_private *lp = netdev_priv(dev);
4316 int i, count;
4317 u_char *p;
4318
4319
4320 for (i=0; i<INFOLEAF_SIZE; i++) {
4321 if (lp->chipset == infoleaf_array[i].chipset) break;
4322 }
4323 if (i == INFOLEAF_SIZE) {
4324 lp->useSROM = false;
4325 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4326 dev->name);
4327 return -ENXIO;
4328 }
4329
4330 lp->infoleaf_fn = infoleaf_array[i].fn;
4331
4332
4333 count = *((u_char *)&lp->srom + 19);
4334 p = (u_char *)&lp->srom + 26;
4335
4336 if (count > 1) {
4337 for (i=count; i; --i, p+=3) {
4338 if (lp->device == *p) break;
4339 }
4340 if (i == 0) {
4341 lp->useSROM = false;
4342 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4343 dev->name, lp->device);
4344 return -ENXIO;
4345 }
4346 }
4347
4348 lp->infoleaf_offset = get_unaligned_le16(p + 1);
4349
4350 return 0;
4351}
4352
4353
4354
4355
4356
4357
4358
4359
4360static void
4361srom_init(struct net_device *dev)
4362{
4363 struct de4x5_private *lp = netdev_priv(dev);
4364 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4365 u_char count;
4366
4367 p+=2;
4368 if (lp->chipset == DC21140) {
4369 lp->cache.gepc = (*p++ | GEP_CTRL);
4370 gep_wr(lp->cache.gepc, dev);
4371 }
4372
4373
4374 count = *p++;
4375
4376
4377 for (;count; --count) {
4378 if (*p < 128) {
4379 p += COMPACT_LEN;
4380 } else if (*(p+1) == 5) {
4381 type5_infoblock(dev, 1, p);
4382 p += ((*p & BLOCK_LEN) + 1);
4383 } else if (*(p+1) == 4) {
4384 p += ((*p & BLOCK_LEN) + 1);
4385 } else if (*(p+1) == 3) {
4386 type3_infoblock(dev, 1, p);
4387 p += ((*p & BLOCK_LEN) + 1);
4388 } else if (*(p+1) == 2) {
4389 p += ((*p & BLOCK_LEN) + 1);
4390 } else if (*(p+1) == 1) {
4391 type1_infoblock(dev, 1, p);
4392 p += ((*p & BLOCK_LEN) + 1);
4393 } else {
4394 p += ((*p & BLOCK_LEN) + 1);
4395 }
4396 }
4397}
4398
4399
4400
4401
4402
4403static void
4404srom_exec(struct net_device *dev, u_char *p)
4405{
4406 struct de4x5_private *lp = netdev_priv(dev);
4407 u_long iobase = dev->base_addr;
4408 u_char count = (p ? *p++ : 0);
4409 u_short *w = (u_short *)p;
4410
4411 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4412
4413 if (lp->chipset != DC21140) RESET_SIA;
4414
4415 while (count--) {
4416 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4417 *p++ : get_unaligned_le16(w++)), dev);
4418 mdelay(2);
4419 }
4420
4421 if (lp->chipset != DC21140) {
4422 outl(lp->cache.csr14, DE4X5_STRR);
4423 outl(lp->cache.csr13, DE4X5_SICR);
4424 }
4425}
4426
4427
4428
4429
4430
4431
4432static int
4433dc21041_infoleaf(struct net_device *dev)
4434{
4435 return DE4X5_AUTOSENSE_MS;
4436}
4437
4438static int
4439dc21140_infoleaf(struct net_device *dev)
4440{
4441 struct de4x5_private *lp = netdev_priv(dev);
4442 u_char count = 0;
4443 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4444 int next_tick = DE4X5_AUTOSENSE_MS;
4445
4446
4447 p+=2;
4448
4449
4450 lp->cache.gepc = (*p++ | GEP_CTRL);
4451
4452
4453 count = *p++;
4454
4455
4456 if (*p < 128) {
4457 next_tick = dc_infoblock[COMPACT](dev, count, p);
4458 } else {
4459 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4460 }
4461
4462 if (lp->tcount == count) {
4463 lp->media = NC;
4464 if (lp->media != lp->c_media) {
4465 de4x5_dbg_media(dev);
4466 lp->c_media = lp->media;
4467 }
4468 lp->media = INIT;
4469 lp->tcount = 0;
4470 lp->tx_enable = false;
4471 }
4472
4473 return next_tick & ~TIMER_CB;
4474}
4475
4476static int
4477dc21142_infoleaf(struct net_device *dev)
4478{
4479 struct de4x5_private *lp = netdev_priv(dev);
4480 u_char count = 0;
4481 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4482 int next_tick = DE4X5_AUTOSENSE_MS;
4483
4484
4485 p+=2;
4486
4487
4488 count = *p++;
4489
4490
4491 if (*p < 128) {
4492 next_tick = dc_infoblock[COMPACT](dev, count, p);
4493 } else {
4494 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4495 }
4496
4497 if (lp->tcount == count) {
4498 lp->media = NC;
4499 if (lp->media != lp->c_media) {
4500 de4x5_dbg_media(dev);
4501 lp->c_media = lp->media;
4502 }
4503 lp->media = INIT;
4504 lp->tcount = 0;
4505 lp->tx_enable = false;
4506 }
4507
4508 return next_tick & ~TIMER_CB;
4509}
4510
4511static int
4512dc21143_infoleaf(struct net_device *dev)
4513{
4514 struct de4x5_private *lp = netdev_priv(dev);
4515 u_char count = 0;
4516 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4517 int next_tick = DE4X5_AUTOSENSE_MS;
4518
4519
4520 p+=2;
4521
4522
4523 count = *p++;
4524
4525
4526 if (*p < 128) {
4527 next_tick = dc_infoblock[COMPACT](dev, count, p);
4528 } else {
4529 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4530 }
4531 if (lp->tcount == count) {
4532 lp->media = NC;
4533 if (lp->media != lp->c_media) {
4534 de4x5_dbg_media(dev);
4535 lp->c_media = lp->media;
4536 }
4537 lp->media = INIT;
4538 lp->tcount = 0;
4539 lp->tx_enable = false;
4540 }
4541
4542 return next_tick & ~TIMER_CB;
4543}
4544
4545
4546
4547
4548
4549static int
4550compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4551{
4552 struct de4x5_private *lp = netdev_priv(dev);
4553 u_char flags, csr6;
4554
4555
4556 if (--count > lp->tcount) {
4557 if (*(p+COMPACT_LEN) < 128) {
4558 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4559 } else {
4560 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4561 }
4562 }
4563
4564 if ((lp->media == INIT) && (lp->timeout < 0)) {
4565 lp->ibn = COMPACT;
4566 lp->active = 0;
4567 gep_wr(lp->cache.gepc, dev);
4568 lp->infoblock_media = (*p++) & COMPACT_MC;
4569 lp->cache.gep = *p++;
4570 csr6 = *p++;
4571 flags = *p++;
4572
4573 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4574 lp->defMedium = (flags & 0x40) ? -1 : 0;
4575 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4576 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4577 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4578 lp->useMII = false;
4579
4580 de4x5_switch_mac_port(dev);
4581 }
4582
4583 return dc21140m_autoconf(dev);
4584}
4585
4586
4587
4588
4589static int
4590type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4591{
4592 struct de4x5_private *lp = netdev_priv(dev);
4593 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4594
4595
4596 if (--count > lp->tcount) {
4597 if (*(p+len) < 128) {
4598 return dc_infoblock[COMPACT](dev, count, p+len);
4599 } else {
4600 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4601 }
4602 }
4603
4604 if ((lp->media == INIT) && (lp->timeout < 0)) {
4605 lp->ibn = 0;
4606 lp->active = 0;
4607 gep_wr(lp->cache.gepc, dev);
4608 p+=2;
4609 lp->infoblock_media = (*p++) & BLOCK0_MC;
4610 lp->cache.gep = *p++;
4611 csr6 = *p++;
4612 flags = *p++;
4613
4614 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4615 lp->defMedium = (flags & 0x40) ? -1 : 0;
4616 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4617 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4618 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4619 lp->useMII = false;
4620
4621 de4x5_switch_mac_port(dev);
4622 }
4623
4624 return dc21140m_autoconf(dev);
4625}
4626
4627
4628
4629static int
4630type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4631{
4632 struct de4x5_private *lp = netdev_priv(dev);
4633 u_char len = (*p & BLOCK_LEN)+1;
4634
4635
4636 if (--count > lp->tcount) {
4637 if (*(p+len) < 128) {
4638 return dc_infoblock[COMPACT](dev, count, p+len);
4639 } else {
4640 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4641 }
4642 }
4643
4644 p += 2;
4645 if (lp->state == INITIALISED) {
4646 lp->ibn = 1;
4647 lp->active = *p++;
4648 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4649 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4650 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4651 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4652 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4653 lp->phy[lp->active].ttm = get_unaligned_le16(p);
4654 return 0;
4655 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4656 lp->ibn = 1;
4657 lp->active = *p;
4658 lp->infoblock_csr6 = OMR_MII_100;
4659 lp->useMII = true;
4660 lp->infoblock_media = ANS;
4661
4662 de4x5_switch_mac_port(dev);
4663 }
4664
4665 return dc21140m_autoconf(dev);
4666}
4667
4668static int
4669type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4670{
4671 struct de4x5_private *lp = netdev_priv(dev);
4672 u_char len = (*p & BLOCK_LEN)+1;
4673
4674
4675 if (--count > lp->tcount) {
4676 if (*(p+len) < 128) {
4677 return dc_infoblock[COMPACT](dev, count, p+len);
4678 } else {
4679 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4680 }
4681 }
4682
4683 if ((lp->media == INIT) && (lp->timeout < 0)) {
4684 lp->ibn = 2;
4685 lp->active = 0;
4686 p += 2;
4687 lp->infoblock_media = (*p) & MEDIA_CODE;
4688
4689 if ((*p++) & EXT_FIELD) {
4690 lp->cache.csr13 = get_unaligned_le16(p); p += 2;
4691 lp->cache.csr14 = get_unaligned_le16(p); p += 2;
4692 lp->cache.csr15 = get_unaligned_le16(p); p += 2;
4693 } else {
4694 lp->cache.csr13 = CSR13;
4695 lp->cache.csr14 = CSR14;
4696 lp->cache.csr15 = CSR15;
4697 }
4698 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4699 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16);
4700 lp->infoblock_csr6 = OMR_SIA;
4701 lp->useMII = false;
4702
4703 de4x5_switch_mac_port(dev);
4704 }
4705
4706 return dc2114x_autoconf(dev);
4707}
4708
4709static int
4710type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4711{
4712 struct de4x5_private *lp = netdev_priv(dev);
4713 u_char len = (*p & BLOCK_LEN)+1;
4714
4715
4716 if (--count > lp->tcount) {
4717 if (*(p+len) < 128) {
4718 return dc_infoblock[COMPACT](dev, count, p+len);
4719 } else {
4720 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4721 }
4722 }
4723
4724 p += 2;
4725 if (lp->state == INITIALISED) {
4726 lp->ibn = 3;
4727 lp->active = *p++;
4728 if (MOTO_SROM_BUG) lp->active = 0;
4729 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4730 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4731 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4732 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4733 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4734 lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2;
4735 lp->phy[lp->active].mci = *p;
4736 return 0;
4737 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4738 lp->ibn = 3;
4739 lp->active = *p;
4740 if (MOTO_SROM_BUG) lp->active = 0;
4741 lp->infoblock_csr6 = OMR_MII_100;
4742 lp->useMII = true;
4743 lp->infoblock_media = ANS;
4744
4745 de4x5_switch_mac_port(dev);
4746 }
4747
4748 return dc2114x_autoconf(dev);
4749}
4750
4751static int
4752type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4753{
4754 struct de4x5_private *lp = netdev_priv(dev);
4755 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4756
4757
4758 if (--count > lp->tcount) {
4759 if (*(p+len) < 128) {
4760 return dc_infoblock[COMPACT](dev, count, p+len);
4761 } else {
4762 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4763 }
4764 }
4765
4766 if ((lp->media == INIT) && (lp->timeout < 0)) {
4767 lp->ibn = 4;
4768 lp->active = 0;
4769 p+=2;
4770 lp->infoblock_media = (*p++) & MEDIA_CODE;
4771 lp->cache.csr13 = CSR13;
4772 lp->cache.csr14 = CSR14;
4773 lp->cache.csr15 = CSR15;
4774 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4775 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4776 csr6 = *p++;
4777 flags = *p++;
4778
4779 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4780 lp->defMedium = (flags & 0x40) ? -1 : 0;
4781 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4782 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4783 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4784 lp->useMII = false;
4785
4786 de4x5_switch_mac_port(dev);
4787 }
4788
4789 return dc2114x_autoconf(dev);
4790}
4791
4792
4793
4794
4795
4796static int
4797type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4798{
4799 struct de4x5_private *lp = netdev_priv(dev);
4800 u_char len = (*p & BLOCK_LEN)+1;
4801
4802
4803 if (--count > lp->tcount) {
4804 if (*(p+len) < 128) {
4805 return dc_infoblock[COMPACT](dev, count, p+len);
4806 } else {
4807 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4808 }
4809 }
4810
4811
4812 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4813 p+=2;
4814 lp->rst = p;
4815 srom_exec(dev, lp->rst);
4816 }
4817
4818 return DE4X5_AUTOSENSE_MS;
4819}
4820
4821
4822
4823
4824
4825static int
4826mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4827{
4828 mii_wdata(MII_PREAMBLE, 2, ioaddr);
4829 mii_wdata(MII_PREAMBLE, 32, ioaddr);
4830 mii_wdata(MII_STRD, 4, ioaddr);
4831 mii_address(phyaddr, ioaddr);
4832 mii_address(phyreg, ioaddr);
4833 mii_ta(MII_STRD, ioaddr);
4834
4835 return mii_rdata(ioaddr);
4836}
4837
4838static void
4839mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4840{
4841 mii_wdata(MII_PREAMBLE, 2, ioaddr);
4842 mii_wdata(MII_PREAMBLE, 32, ioaddr);
4843 mii_wdata(MII_STWR, 4, ioaddr);
4844 mii_address(phyaddr, ioaddr);
4845 mii_address(phyreg, ioaddr);
4846 mii_ta(MII_STWR, ioaddr);
4847 data = mii_swap(data, 16);
4848 mii_wdata(data, 16, ioaddr);
4849}
4850
4851static int
4852mii_rdata(u_long ioaddr)
4853{
4854 int i;
4855 s32 tmp = 0;
4856
4857 for (i=0; i<16; i++) {
4858 tmp <<= 1;
4859 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4860 }
4861
4862 return tmp;
4863}
4864
4865static void
4866mii_wdata(int data, int len, u_long ioaddr)
4867{
4868 int i;
4869
4870 for (i=0; i<len; i++) {
4871 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4872 data >>= 1;
4873 }
4874}
4875
4876static void
4877mii_address(u_char addr, u_long ioaddr)
4878{
4879 int i;
4880
4881 addr = mii_swap(addr, 5);
4882 for (i=0; i<5; i++) {
4883 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4884 addr >>= 1;
4885 }
4886}
4887
4888static void
4889mii_ta(u_long rw, u_long ioaddr)
4890{
4891 if (rw == MII_STWR) {
4892 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4893 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4894 } else {
4895 getfrom_mii(MII_MRD | MII_RD, ioaddr);
4896 }
4897}
4898
4899static int
4900mii_swap(int data, int len)
4901{
4902 int i, tmp = 0;
4903
4904 for (i=0; i<len; i++) {
4905 tmp <<= 1;
4906 tmp |= (data & 1);
4907 data >>= 1;
4908 }
4909
4910 return tmp;
4911}
4912
4913static void
4914sendto_mii(u32 command, int data, u_long ioaddr)
4915{
4916 u32 j;
4917
4918 j = (data & 1) << 17;
4919 outl(command | j, ioaddr);
4920 udelay(1);
4921 outl(command | MII_MDC | j, ioaddr);
4922 udelay(1);
4923}
4924
4925static int
4926getfrom_mii(u32 command, u_long ioaddr)
4927{
4928 outl(command, ioaddr);
4929 udelay(1);
4930 outl(command | MII_MDC, ioaddr);
4931 udelay(1);
4932
4933 return (inl(ioaddr) >> 19) & 1;
4934}
4935
4936
4937
4938
4939static int
4940mii_get_oui(u_char phyaddr, u_long ioaddr)
4941{
4942
4943
4944
4945
4946
4947
4948 int r2, r3;
4949
4950
4951 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
4952 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980 return r2;
4981}
4982
4983
4984
4985
4986static int
4987mii_get_phy(struct net_device *dev)
4988{
4989 struct de4x5_private *lp = netdev_priv(dev);
4990 u_long iobase = dev->base_addr;
4991 int i, j, k, n, limit=ARRAY_SIZE(phy_info);
4992 int id;
4993
4994 lp->active = 0;
4995 lp->useMII = true;
4996
4997
4998 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
4999 lp->phy[lp->active].addr = i;
5000 if (i==0) n++;
5001 while (de4x5_reset_phy(dev)<0) udelay(100);
5002 id = mii_get_oui(i, DE4X5_MII);
5003 if ((id == 0) || (id == 65535)) continue;
5004 for (j=0; j<limit; j++) {
5005 if (id != phy_info[j].id) continue;
5006 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
5007 if (k < DE4X5_MAX_PHY) {
5008 memcpy((char *)&lp->phy[k],
5009 (char *)&phy_info[j], sizeof(struct phy_table));
5010 lp->phy[k].addr = i;
5011 lp->mii_cnt++;
5012 lp->active++;
5013 } else {
5014 goto purgatory;
5015 }
5016 break;
5017 }
5018 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5019 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
5020 lp->phy[k].addr = i;
5021 lp->phy[k].id = id;
5022 lp->phy[k].spd.reg = GENERIC_REG;
5023 lp->phy[k].spd.mask = GENERIC_MASK;
5024 lp->phy[k].spd.value = GENERIC_VALUE;
5025 lp->mii_cnt++;
5026 lp->active++;
5027 printk("%s: Using generic MII device control. If the board doesn't operate,\nplease mail the following dump to the author:\n", dev->name);
5028 j = de4x5_debug;
5029 de4x5_debug |= DEBUG_MII;
5030 de4x5_dbg_mii(dev, k);
5031 de4x5_debug = j;
5032 printk("\n");
5033 }
5034 }
5035 purgatory:
5036 lp->active = 0;
5037 if (lp->phy[0].id) {
5038 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) {
5039 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5040 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5041
5042 de4x5_dbg_mii(dev, k);
5043 }
5044 }
5045 if (!lp->mii_cnt) lp->useMII = false;
5046
5047 return lp->mii_cnt;
5048}
5049
5050static char *
5051build_setup_frame(struct net_device *dev, int mode)
5052{
5053 struct de4x5_private *lp = netdev_priv(dev);
5054 int i;
5055 char *pa = lp->setup_frame;
5056
5057
5058 if (mode == ALL) {
5059 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5060 }
5061
5062 if (lp->setup_f == HASH_PERF) {
5063 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5064 *(pa + i) = dev->dev_addr[i];
5065 if (i & 0x01) pa += 2;
5066 }
5067 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5068 } else {
5069 for (i=0; i<ETH_ALEN; i++) {
5070 *(pa + (i&1)) = dev->dev_addr[i];
5071 if (i & 0x01) pa += 4;
5072 }
5073 for (i=0; i<ETH_ALEN; i++) {
5074 *(pa + (i&1)) = (char) 0xff;
5075 if (i & 0x01) pa += 4;
5076 }
5077 }
5078
5079 return pa;
5080}
5081
5082static void
5083disable_ast(struct net_device *dev)
5084{
5085 struct de4x5_private *lp = netdev_priv(dev);
5086 del_timer_sync(&lp->timer);
5087}
5088
5089static long
5090de4x5_switch_mac_port(struct net_device *dev)
5091{
5092 struct de4x5_private *lp = netdev_priv(dev);
5093 u_long iobase = dev->base_addr;
5094 s32 omr;
5095
5096 STOP_DE4X5;
5097
5098
5099 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5100 OMR_FDX));
5101 omr |= lp->infoblock_csr6;
5102 if (omr & OMR_PS) omr |= OMR_HBD;
5103 outl(omr, DE4X5_OMR);
5104
5105
5106 RESET_DE4X5;
5107
5108
5109 if (lp->chipset == DC21140) {
5110 gep_wr(lp->cache.gepc, dev);
5111 gep_wr(lp->cache.gep, dev);
5112 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5113 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5114 }
5115
5116
5117 outl(omr, DE4X5_OMR);
5118
5119
5120 inl(DE4X5_MFC);
5121
5122 return omr;
5123}
5124
5125static void
5126gep_wr(s32 data, struct net_device *dev)
5127{
5128 struct de4x5_private *lp = netdev_priv(dev);
5129 u_long iobase = dev->base_addr;
5130
5131 if (lp->chipset == DC21140) {
5132 outl(data, DE4X5_GEP);
5133 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5134 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5135 }
5136}
5137
5138static int
5139gep_rd(struct net_device *dev)
5140{
5141 struct de4x5_private *lp = netdev_priv(dev);
5142 u_long iobase = dev->base_addr;
5143
5144 if (lp->chipset == DC21140) {
5145 return inl(DE4X5_GEP);
5146 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5147 return inl(DE4X5_SIGR) & 0x000fffff;
5148 }
5149
5150 return 0;
5151}
5152
5153static void
5154yawn(struct net_device *dev, int state)
5155{
5156 struct de4x5_private *lp = netdev_priv(dev);
5157 u_long iobase = dev->base_addr;
5158
5159 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5160
5161 if(lp->bus == EISA) {
5162 switch(state) {
5163 case WAKEUP:
5164 outb(WAKEUP, PCI_CFPM);
5165 mdelay(10);
5166 break;
5167
5168 case SNOOZE:
5169 outb(SNOOZE, PCI_CFPM);
5170 break;
5171
5172 case SLEEP:
5173 outl(0, DE4X5_SICR);
5174 outb(SLEEP, PCI_CFPM);
5175 break;
5176 }
5177 } else {
5178 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5179 switch(state) {
5180 case WAKEUP:
5181 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5182 mdelay(10);
5183 break;
5184
5185 case SNOOZE:
5186 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5187 break;
5188
5189 case SLEEP:
5190 outl(0, DE4X5_SICR);
5191 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5192 break;
5193 }
5194 }
5195}
5196
5197static void
5198de4x5_parse_params(struct net_device *dev)
5199{
5200 struct de4x5_private *lp = netdev_priv(dev);
5201 char *p, *q, t;
5202
5203 lp->params.fdx = 0;
5204 lp->params.autosense = AUTO;
5205
5206 if (args == NULL) return;
5207
5208 if ((p = strstr(args, dev->name))) {
5209 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5210 t = *q;
5211 *q = '\0';
5212
5213 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5214
5215 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5216 if (strstr(p, "TP")) {
5217 lp->params.autosense = TP;
5218 } else if (strstr(p, "TP_NW")) {
5219 lp->params.autosense = TP_NW;
5220 } else if (strstr(p, "BNC")) {
5221 lp->params.autosense = BNC;
5222 } else if (strstr(p, "AUI")) {
5223 lp->params.autosense = AUI;
5224 } else if (strstr(p, "BNC_AUI")) {
5225 lp->params.autosense = BNC;
5226 } else if (strstr(p, "10Mb")) {
5227 lp->params.autosense = _10Mb;
5228 } else if (strstr(p, "100Mb")) {
5229 lp->params.autosense = _100Mb;
5230 } else if (strstr(p, "AUTO")) {
5231 lp->params.autosense = AUTO;
5232 }
5233 }
5234 *q = t;
5235 }
5236}
5237
5238static void
5239de4x5_dbg_open(struct net_device *dev)
5240{
5241 struct de4x5_private *lp = netdev_priv(dev);
5242 int i;
5243
5244 if (de4x5_debug & DEBUG_OPEN) {
5245 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5246 printk("\tphysical address: ");
5247 for (i=0;i<6;i++) {
5248 printk("%2.2x:",(short)dev->dev_addr[i]);
5249 }
5250 printk("\n");
5251 printk("Descriptor head addresses:\n");
5252 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5253 printk("Descriptor addresses:\nRX: ");
5254 for (i=0;i<lp->rxRingSize-1;i++){
5255 if (i < 3) {
5256 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5257 }
5258 }
5259 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5260 printk("TX: ");
5261 for (i=0;i<lp->txRingSize-1;i++){
5262 if (i < 3) {
5263 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5264 }
5265 }
5266 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5267 printk("Descriptor buffers:\nRX: ");
5268 for (i=0;i<lp->rxRingSize-1;i++){
5269 if (i < 3) {
5270 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5271 }
5272 }
5273 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5274 printk("TX: ");
5275 for (i=0;i<lp->txRingSize-1;i++){
5276 if (i < 3) {
5277 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5278 }
5279 }
5280 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5281 printk("Ring size:\nRX: %d\nTX: %d\n",
5282 (short)lp->rxRingSize,
5283 (short)lp->txRingSize);
5284 }
5285}
5286
5287static void
5288de4x5_dbg_mii(struct net_device *dev, int k)
5289{
5290 struct de4x5_private *lp = netdev_priv(dev);
5291 u_long iobase = dev->base_addr;
5292
5293 if (de4x5_debug & DEBUG_MII) {
5294 printk("\nMII device address: %d\n", lp->phy[k].addr);
5295 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5296 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5297 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5298 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5299 if (lp->phy[k].id != BROADCOM_T4) {
5300 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5301 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5302 }
5303 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5304 if (lp->phy[k].id != BROADCOM_T4) {
5305 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5306 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5307 } else {
5308 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5309 }
5310 }
5311}
5312
5313static void
5314de4x5_dbg_media(struct net_device *dev)
5315{
5316 struct de4x5_private *lp = netdev_priv(dev);
5317
5318 if (lp->media != lp->c_media) {
5319 if (de4x5_debug & DEBUG_MEDIA) {
5320 printk("%s: media is %s%s\n", dev->name,
5321 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5322 (lp->media == TP ? "TP" :
5323 (lp->media == ANS ? "TP/Nway" :
5324 (lp->media == BNC ? "BNC" :
5325 (lp->media == AUI ? "AUI" :
5326 (lp->media == BNC_AUI ? "BNC/AUI" :
5327 (lp->media == EXT_SIA ? "EXT SIA" :
5328 (lp->media == _100Mb ? "100Mb/s" :
5329 (lp->media == _10Mb ? "10Mb/s" :
5330 "???"
5331 ))))))))), (lp->fdx?" full duplex.":"."));
5332 }
5333 lp->c_media = lp->media;
5334 }
5335}
5336
5337static void
5338de4x5_dbg_srom(struct de4x5_srom *p)
5339{
5340 int i;
5341
5342 if (de4x5_debug & DEBUG_SROM) {
5343 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5344 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5345 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5346 printk("SROM version: %02x\n", (u_char)(p->version));
5347 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5348
5349 printk("Hardware Address: %pM\n", p->ieee_addr);
5350 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5351 for (i=0; i<64; i++) {
5352 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5353 }
5354 }
5355}
5356
5357static void
5358de4x5_dbg_rx(struct sk_buff *skb, int len)
5359{
5360 int i, j;
5361
5362 if (de4x5_debug & DEBUG_RX) {
5363 printk("R: %pM <- %pM len/SAP:%02x%02x [%d]\n",
5364 skb->data, &skb->data[6],
5365 (u_char)skb->data[12],
5366 (u_char)skb->data[13],
5367 len);
5368 for (j=0; len>0;j+=16, len-=16) {
5369 printk(" %03x: ",j);
5370 for (i=0; i<16 && i<len; i++) {
5371 printk("%02x ",(u_char)skb->data[i+j]);
5372 }
5373 printk("\n");
5374 }
5375 }
5376}
5377
5378
5379
5380
5381
5382
5383static int
5384de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5385{
5386 struct de4x5_private *lp = netdev_priv(dev);
5387 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5388 u_long iobase = dev->base_addr;
5389 int i, j, status = 0;
5390 s32 omr;
5391 union {
5392 u8 addr[144];
5393 u16 sval[72];
5394 u32 lval[36];
5395 } tmp;
5396 u_long flags = 0;
5397
5398 switch(ioc->cmd) {
5399 case DE4X5_GET_HWADDR:
5400 ioc->len = ETH_ALEN;
5401 for (i=0; i<ETH_ALEN; i++) {
5402 tmp.addr[i] = dev->dev_addr[i];
5403 }
5404 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5405 break;
5406
5407 case DE4X5_SET_HWADDR:
5408 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5409 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5410 if (netif_queue_stopped(dev))
5411 return -EBUSY;
5412 netif_stop_queue(dev);
5413 for (i=0; i<ETH_ALEN; i++) {
5414 dev->dev_addr[i] = tmp.addr[i];
5415 }
5416 build_setup_frame(dev, PHYS_ADDR_ONLY);
5417
5418 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5419 SETUP_FRAME_LEN, (struct sk_buff *)1);
5420 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
5421 outl(POLL_DEMAND, DE4X5_TPD);
5422 netif_wake_queue(dev);
5423 break;
5424
5425 case DE4X5_SAY_BOO:
5426 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5427 printk("%s: Boo!\n", dev->name);
5428 break;
5429
5430 case DE4X5_MCA_EN:
5431 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5432 omr = inl(DE4X5_OMR);
5433 omr |= OMR_PM;
5434 outl(omr, DE4X5_OMR);
5435 break;
5436
5437 case DE4X5_GET_STATS:
5438 {
5439 struct pkt_stats statbuf;
5440 ioc->len = sizeof(statbuf);
5441 spin_lock_irqsave(&lp->lock, flags);
5442 memcpy(&statbuf, &lp->pktStats, ioc->len);
5443 spin_unlock_irqrestore(&lp->lock, flags);
5444 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5445 return -EFAULT;
5446 break;
5447 }
5448 case DE4X5_CLR_STATS:
5449 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5450 spin_lock_irqsave(&lp->lock, flags);
5451 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5452 spin_unlock_irqrestore(&lp->lock, flags);
5453 break;
5454
5455 case DE4X5_GET_OMR:
5456 tmp.addr[0] = inl(DE4X5_OMR);
5457 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5458 break;
5459
5460 case DE4X5_SET_OMR:
5461 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5462 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5463 outl(tmp.addr[0], DE4X5_OMR);
5464 break;
5465
5466 case DE4X5_GET_REG:
5467 j = 0;
5468 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5469 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5470 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5471 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5472 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5473 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5474 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5475 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5476 ioc->len = j;
5477 if (copy_to_user(ioc->data, tmp.lval, ioc->len))
5478 return -EFAULT;
5479 break;
5480
5481#define DE4X5_DUMP 0x0f
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498
5499
5500
5501
5502
5503
5504
5505
5506
5507
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531
5532
5533
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567
5568
5569
5570
5571 default:
5572 return -EOPNOTSUPP;
5573 }
5574
5575 return status;
5576}
5577
5578static int __init de4x5_module_init (void)
5579{
5580 int err = 0;
5581
5582#ifdef CONFIG_PCI
5583 err = pci_register_driver(&de4x5_pci_driver);
5584#endif
5585#ifdef CONFIG_EISA
5586 err |= eisa_driver_register (&de4x5_eisa_driver);
5587#endif
5588
5589 return err;
5590}
5591
5592static void __exit de4x5_module_exit (void)
5593{
5594#ifdef CONFIG_PCI
5595 pci_unregister_driver (&de4x5_pci_driver);
5596#endif
5597#ifdef CONFIG_EISA
5598 eisa_driver_unregister (&de4x5_eisa_driver);
5599#endif
5600}
5601
5602module_init (de4x5_module_init);
5603module_exit (de4x5_module_exit);
5604