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16#ifndef __NET_TULIP_H__
17#define __NET_TULIP_H__
18
19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/spinlock.h>
22#include <linux/netdevice.h>
23#include <linux/ethtool.h>
24#include <linux/timer.h>
25#include <linux/delay.h>
26#include <linux/pci.h>
27#include <asm/io.h>
28#include <asm/irq.h>
29#include <asm/unaligned.h>
30
31
32
33
34#define TULIP_DEBUG 1
35
36#ifdef CONFIG_TULIP_MMIO
37#define TULIP_BAR 1
38#else
39#define TULIP_BAR 0
40#endif
41
42
43
44struct tulip_chip_table {
45 char *chip_name;
46 int io_size;
47 int valid_intrs;
48 int flags;
49 void (*media_timer) (unsigned long);
50 work_func_t media_task;
51};
52
53
54enum tbl_flag {
55 HAS_MII = 0x00001,
56 HAS_MEDIA_TABLE = 0x00002,
57 CSR12_IN_SROM = 0x00004,
58 ALWAYS_CHECK_MII = 0x00008,
59 HAS_ACPI = 0x00010,
60 MC_HASH_ONLY = 0x00020,
61 HAS_PNICNWAY = 0x00080,
62 HAS_NWAY = 0x00040,
63 HAS_INTR_MITIGATION = 0x00100,
64 IS_ASIX = 0x00200,
65 HAS_8023X = 0x00400,
66 COMET_MAC_ADDR = 0x00800,
67 HAS_PCI_MWI = 0x01000,
68 HAS_PHY_IRQ = 0x02000,
69 HAS_SWAPPED_SEEPROM = 0x04000,
70 NEEDS_FAKE_MEDIA_TABLE = 0x08000,
71 COMET_PM = 0x10000,
72};
73
74
75
76
77
78enum chips {
79 DC21040 = 0,
80 DC21041 = 1,
81 DC21140 = 2,
82 DC21142 = 3, DC21143 = 3,
83 LC82C168,
84 MX98713,
85 MX98715,
86 MX98725,
87 AX88140,
88 PNIC2,
89 COMET,
90 COMPEX9881,
91 I21145,
92 DM910X,
93 CONEXANT,
94};
95
96
97enum MediaIs {
98 MediaIsFD = 1,
99 MediaAlwaysFD = 2,
100 MediaIsMII = 4,
101 MediaIsFx = 8,
102 MediaIs100 = 16
103};
104
105
106
107
108enum tulip_offsets {
109 CSR0 = 0,
110 CSR1 = 0x08,
111 CSR2 = 0x10,
112 CSR3 = 0x18,
113 CSR4 = 0x20,
114 CSR5 = 0x28,
115 CSR6 = 0x30,
116 CSR7 = 0x38,
117 CSR8 = 0x40,
118 CSR9 = 0x48,
119 CSR10 = 0x50,
120 CSR11 = 0x58,
121 CSR12 = 0x60,
122 CSR13 = 0x68,
123 CSR14 = 0x70,
124 CSR15 = 0x78,
125 CSR18 = 0x88,
126 CSR19 = 0x8c,
127 CSR20 = 0x90,
128 CSR27 = 0xAC,
129 CSR28 = 0xB0,
130};
131
132
133enum pci_cfg_driver_reg {
134 CFDD = 0x40,
135 CFDD_Sleep = (1 << 31),
136 CFDD_Snooze = (1 << 30),
137};
138
139#define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
140
141
142enum status_bits {
143 TimerInt = 0x800,
144 SystemError = 0x2000,
145 TPLnkFail = 0x1000,
146 TPLnkPass = 0x10,
147 NormalIntr = 0x10000,
148 AbnormalIntr = 0x8000,
149 RxJabber = 0x200,
150 RxDied = 0x100,
151 RxNoBuf = 0x80,
152 RxIntr = 0x40,
153 TxFIFOUnderflow = 0x20,
154 RxErrIntr = 0x10,
155 TxJabber = 0x08,
156 TxNoBuf = 0x04,
157 TxDied = 0x02,
158 TxIntr = 0x01,
159};
160
161
162#define CSR5_TS 0x00700000
163#define CSR5_RS 0x000e0000
164
165enum tulip_mode_bits {
166 TxThreshold = (1 << 22),
167 FullDuplex = (1 << 9),
168 TxOn = 0x2000,
169 AcceptBroadcast = 0x0100,
170 AcceptAllMulticast = 0x0080,
171 AcceptAllPhys = 0x0040,
172 AcceptRunt = 0x0008,
173 RxOn = 0x0002,
174 RxTx = (TxOn | RxOn),
175};
176
177
178enum tulip_busconfig_bits {
179 MWI = (1 << 24),
180 MRL = (1 << 23),
181 MRM = (1 << 21),
182 CALShift = 14,
183 BurstLenShift = 8,
184};
185
186
187
188struct tulip_rx_desc {
189 __le32 status;
190 __le32 length;
191 __le32 buffer1;
192 __le32 buffer2;
193};
194
195
196struct tulip_tx_desc {
197 __le32 status;
198 __le32 length;
199 __le32 buffer1;
200 __le32 buffer2;
201};
202
203
204enum desc_status_bits {
205 DescOwned = 0x80000000,
206 DescWholePkt = 0x60000000,
207 DescEndPkt = 0x40000000,
208 DescStartPkt = 0x20000000,
209 DescEndRing = 0x02000000,
210 DescUseLink = 0x01000000,
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217 RxDescErrorSummary = 0x8000,
218 RxDescCRCError = 0x0002,
219 RxDescCollisionSeen = 0x0040,
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232 RxDescFrameTooLong = 0x0080,
233 RxDescRunt = 0x0800,
234 RxDescDescErr = 0x4000,
235 RxWholePkt = 0x00000300,
236
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242 RxLengthOver2047 = 0x38000010
243};
244
245
246enum t21143_csr6_bits {
247 csr6_sc = (1<<31),
248 csr6_ra = (1<<30),
249 csr6_ign_dest_msb = (1<<26),
250 csr6_mbo = (1<<25),
251 csr6_scr = (1<<24),
252 csr6_pcs = (1<<23),
253 csr6_ttm = (1<<22),
254 csr6_sf = (1<<21),
255 csr6_hbd = (1<<19),
256 csr6_ps = (1<<18),
257 csr6_ca = (1<<17),
258 csr6_trh = (1<<15),
259 csr6_trl = (1<<14),
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275
276 csr6_fc = (1<<12),
277 csr6_om_int_loop = (1<<10),
278 csr6_om_ext_loop = (1<<11),
279
280 csr6_fd = (1<<9),
281 csr6_pm = (1<<7),
282 csr6_pr = (1<<6),
283 csr6_sb = (1<<5),
284 csr6_if = (1<<4),
285 csr6_pb = (1<<3),
286 csr6_ho = (1<<2),
287 csr6_hp = (1<<0),
288
289 csr6_mask_capture = (csr6_sc | csr6_ca),
290 csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
291 csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
292 csr6_mask_hdcaptt = (csr6_mask_hdcap | csr6_trh | csr6_trl),
293 csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
294 csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
295 csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
296 csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
297};
298
299enum tulip_comet_csr13_bits {
300
301
302
303 comet_csr13_linkoffe = (1 << 17),
304 comet_csr13_linkone = (1 << 16),
305 comet_csr13_wfre = (1 << 10),
306 comet_csr13_mpre = (1 << 9),
307 comet_csr13_lsce = (1 << 8),
308 comet_csr13_wfr = (1 << 2),
309 comet_csr13_mpr = (1 << 1),
310 comet_csr13_lsc = (1 << 0),
311};
312
313enum tulip_comet_csr18_bits {
314 comet_csr18_pmes_sticky = (1 << 24),
315 comet_csr18_pm_mode = (1 << 19),
316 comet_csr18_apm_mode = (1 << 18),
317 comet_csr18_d3a = (1 << 7)
318};
319
320enum tulip_comet_csr20_bits {
321 comet_csr20_pmes = (1 << 15),
322};
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328
329#define TX_RING_SIZE 32
330#define RX_RING_SIZE 128
331#define MEDIA_MASK 31
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337
338#define PKT_BUF_SZ (1536 + 4)
339
340#define TULIP_MIN_CACHE_LINE 8
341
342#if defined(__sparc__) || defined(__hppa__)
343
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346
347#define TULIP_MAX_CACHE_LINE 16
348#else
349#define TULIP_MAX_CACHE_LINE 32
350#endif
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360
361#define DESC_RING_WRAP 0x02000000
362
363
364#define EEPROM_SIZE 512
365
366
367#define RUN_AT(x) (jiffies + (x))
368
369#define get_u16(ptr) get_unaligned_le16((ptr))
370
371struct medialeaf {
372 u8 type;
373 u8 media;
374 unsigned char *leafdata;
375};
376
377
378struct mediatable {
379 u16 defaultmedia;
380 u8 leafcount;
381 u8 csr12dir;
382 unsigned has_mii:1;
383 unsigned has_nonmii:1;
384 unsigned has_reset:6;
385 u32 csr15dir;
386 u32 csr15val;
387 struct medialeaf mleaf[0];
388};
389
390
391struct mediainfo {
392 struct mediainfo *next;
393 int info_type;
394 int index;
395 unsigned char *info;
396};
397
398struct ring_info {
399 struct sk_buff *skb;
400 dma_addr_t mapping;
401};
402
403
404struct tulip_private {
405 const char *product_name;
406 struct net_device *next_module;
407 struct tulip_rx_desc *rx_ring;
408 struct tulip_tx_desc *tx_ring;
409 dma_addr_t rx_ring_dma;
410 dma_addr_t tx_ring_dma;
411
412 struct ring_info tx_buffers[TX_RING_SIZE];
413
414 struct ring_info rx_buffers[RX_RING_SIZE];
415 u16 setup_frame[96];
416 int chip_id;
417 int revision;
418 int flags;
419 struct napi_struct napi;
420 struct timer_list timer;
421 struct timer_list oom_timer;
422 u32 mc_filter[2];
423 spinlock_t lock;
424 spinlock_t mii_lock;
425 unsigned int cur_rx, cur_tx;
426 unsigned int dirty_rx, dirty_tx;
427
428#ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
429 int mit_on;
430#endif
431 unsigned int full_duplex:1;
432 unsigned int full_duplex_lock:1;
433 unsigned int fake_addr:1;
434 unsigned int default_port:4;
435 unsigned int media2:4;
436 unsigned int medialock:1;
437 unsigned int mediasense:1;
438 unsigned int nway:1, nwayset:1;
439 unsigned int timeout_recovery:1;
440 unsigned int csr0;
441 unsigned int csr6;
442 unsigned char eeprom[EEPROM_SIZE];
443 void (*link_change) (struct net_device * dev, int csr5);
444 struct ethtool_wolinfo wolinfo;
445 u16 sym_advertise, mii_advertise;
446 u16 lpar;
447 u16 advertising[4];
448 signed char phys[4], mii_cnt;
449 struct mediatable *mtable;
450 int cur_index;
451 int saved_if_port;
452 struct pci_dev *pdev;
453 int ttimer;
454 int susp_rx;
455 unsigned long nir;
456 void __iomem *base_addr;
457 int csr12_shadow;
458 int pad0;
459 struct work_struct media_work;
460 struct net_device *dev;
461};
462
463
464struct eeprom_fixup {
465 char *name;
466 unsigned char addr0;
467 unsigned char addr1;
468 unsigned char addr2;
469 u16 newtable[32];
470};
471
472
473
474extern u16 t21142_csr14[];
475void t21142_media_task(struct work_struct *work);
476void t21142_start_nway(struct net_device *dev);
477void t21142_lnk_change(struct net_device *dev, int csr5);
478
479
480
481void pnic2_lnk_change(struct net_device *dev, int csr5);
482void pnic2_timer(unsigned long data);
483void pnic2_start_nway(struct net_device *dev);
484void pnic2_lnk_change(struct net_device *dev, int csr5);
485
486
487void tulip_parse_eeprom(struct net_device *dev);
488int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
489
490
491extern unsigned int tulip_max_interrupt_work;
492extern int tulip_rx_copybreak;
493irqreturn_t tulip_interrupt(int irq, void *dev_instance);
494int tulip_refill_rx(struct net_device *dev);
495#ifdef CONFIG_TULIP_NAPI
496int tulip_poll(struct napi_struct *napi, int budget);
497#endif
498
499
500
501int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
502void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
503void tulip_select_media(struct net_device *dev, int startup);
504int tulip_check_duplex(struct net_device *dev);
505void tulip_find_mii (struct net_device *dev, int board_idx);
506
507
508void pnic_do_nway(struct net_device *dev);
509void pnic_lnk_change(struct net_device *dev, int csr5);
510void pnic_timer(unsigned long data);
511
512
513void tulip_media_task(struct work_struct *work);
514void mxic_timer(unsigned long data);
515void comet_timer(unsigned long data);
516
517
518extern int tulip_debug;
519extern const char * const medianame[];
520extern const char tulip_media_cap[];
521extern struct tulip_chip_table tulip_tbl[];
522void oom_timer(unsigned long data);
523extern u8 t21040_csr13[];
524
525static inline void tulip_start_rxtx(struct tulip_private *tp)
526{
527 void __iomem *ioaddr = tp->base_addr;
528 iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
529 barrier();
530 (void) ioread32(ioaddr + CSR6);
531}
532
533static inline void tulip_stop_rxtx(struct tulip_private *tp)
534{
535 void __iomem *ioaddr = tp->base_addr;
536 u32 csr6 = ioread32(ioaddr + CSR6);
537
538 if (csr6 & RxTx) {
539 unsigned i=1300/10;
540 iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
541 barrier();
542
543
544
545
546 while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
547 udelay(10);
548
549 if (!i)
550 printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed"
551 " (CSR5 0x%x CSR6 0x%x)\n",
552 pci_name(tp->pdev),
553 ioread32(ioaddr + CSR5),
554 ioread32(ioaddr + CSR6));
555 }
556}
557
558static inline void tulip_restart_rxtx(struct tulip_private *tp)
559{
560 tulip_stop_rxtx(tp);
561 udelay(5);
562 tulip_start_rxtx(tp);
563}
564
565static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr)
566{
567
568 tulip_restart_rxtx(tp);
569
570 iowrite32(0, ioaddr + CSR1);
571
572 tp->dev->stats.tx_errors++;
573}
574
575#endif
576