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43#include <linux/module.h>
44#include <linux/delay.h>
45#include <linux/hardirq.h>
46#include <linux/if.h>
47#include <linux/io.h>
48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
52#include <linux/slab.h>
53#include <linux/etherdevice.h>
54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
62#include "ani.h"
63
64int ath5k_modparam_nohwcrypt;
65module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
66MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
67
68static int modparam_all_channels;
69module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
70MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
71
72
73MODULE_AUTHOR("Jiri Slaby");
74MODULE_AUTHOR("Nick Kossifidis");
75MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77MODULE_LICENSE("Dual BSD/GPL");
78
79static int ath5k_init(struct ieee80211_hw *hw);
80static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
81 bool skip_pcu);
82int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
83void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
84
85
86static const struct ath5k_srev_name srev_names[] = {
87#ifdef CONFIG_ATHEROS_AR231X
88 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
89 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
90 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
91 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
92 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
93 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
94 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
95#else
96 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
97 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
98 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
99 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
100 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
101 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
102 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
103 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
104 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
105 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
106 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
107 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
108 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
109 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
110 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
111 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
112 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
113 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
114#endif
115 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
116 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
117 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
118 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
119 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
120 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
121 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
122 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
123 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
124 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
125 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
126 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
127 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
128 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
129 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
130#ifdef CONFIG_ATHEROS_AR231X
131 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
132 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
133#endif
134 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
135};
136
137static const struct ieee80211_rate ath5k_rates[] = {
138 { .bitrate = 10,
139 .hw_value = ATH5K_RATE_CODE_1M, },
140 { .bitrate = 20,
141 .hw_value = ATH5K_RATE_CODE_2M,
142 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
143 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
144 { .bitrate = 55,
145 .hw_value = ATH5K_RATE_CODE_5_5M,
146 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
147 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
148 { .bitrate = 110,
149 .hw_value = ATH5K_RATE_CODE_11M,
150 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 60,
153 .hw_value = ATH5K_RATE_CODE_6M,
154 .flags = 0 },
155 { .bitrate = 90,
156 .hw_value = ATH5K_RATE_CODE_9M,
157 .flags = 0 },
158 { .bitrate = 120,
159 .hw_value = ATH5K_RATE_CODE_12M,
160 .flags = 0 },
161 { .bitrate = 180,
162 .hw_value = ATH5K_RATE_CODE_18M,
163 .flags = 0 },
164 { .bitrate = 240,
165 .hw_value = ATH5K_RATE_CODE_24M,
166 .flags = 0 },
167 { .bitrate = 360,
168 .hw_value = ATH5K_RATE_CODE_36M,
169 .flags = 0 },
170 { .bitrate = 480,
171 .hw_value = ATH5K_RATE_CODE_48M,
172 .flags = 0 },
173 { .bitrate = 540,
174 .hw_value = ATH5K_RATE_CODE_54M,
175 .flags = 0 },
176
177};
178
179static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
180{
181 u64 tsf = ath5k_hw_get_tsf64(ah);
182
183 if ((tsf & 0x7fff) < rstamp)
184 tsf -= 0x8000;
185
186 return (tsf & ~0x7fff) | rstamp;
187}
188
189const char *
190ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
191{
192 const char *name = "xxxxx";
193 unsigned int i;
194
195 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
196 if (srev_names[i].sr_type != type)
197 continue;
198
199 if ((val & 0xf0) == srev_names[i].sr_val)
200 name = srev_names[i].sr_name;
201
202 if ((val & 0xff) == srev_names[i].sr_val) {
203 name = srev_names[i].sr_name;
204 break;
205 }
206 }
207
208 return name;
209}
210static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
211{
212 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
213 return ath5k_hw_reg_read(ah, reg_offset);
214}
215
216static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
217{
218 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
219 ath5k_hw_reg_write(ah, val, reg_offset);
220}
221
222static const struct ath_ops ath5k_common_ops = {
223 .read = ath5k_ioread32,
224 .write = ath5k_iowrite32,
225};
226
227
228
229
230
231static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
232{
233 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
234 struct ath5k_softc *sc = hw->priv;
235 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
236
237 return ath_reg_notifier_apply(wiphy, request, regulatory);
238}
239
240
241
242
243
244
245
246
247static inline short
248ath5k_ieee2mhz(short chan)
249{
250 if (chan <= 14 || chan >= 27)
251 return ieee80211chan2mhz(chan);
252 else
253 return 2212 + chan * 20;
254}
255
256
257
258
259static bool ath5k_is_standard_channel(short chan)
260{
261 return ((chan <= 14) ||
262
263 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
264
265 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
266
267 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
268}
269
270static unsigned int
271ath5k_copy_channels(struct ath5k_hw *ah,
272 struct ieee80211_channel *channels,
273 unsigned int mode,
274 unsigned int max)
275{
276 unsigned int i, count, size, chfreq, freq, ch;
277
278 if (!test_bit(mode, ah->ah_modes))
279 return 0;
280
281 switch (mode) {
282 case AR5K_MODE_11A:
283
284 size = 220 ;
285 chfreq = CHANNEL_5GHZ;
286 break;
287 case AR5K_MODE_11B:
288 case AR5K_MODE_11G:
289 size = 26;
290 chfreq = CHANNEL_2GHZ;
291 break;
292 default:
293 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
294 return 0;
295 }
296
297 for (i = 0, count = 0; i < size && max > 0; i++) {
298 ch = i + 1 ;
299 freq = ath5k_ieee2mhz(ch);
300
301
302 if (!ath5k_channel_ok(ah, freq, chfreq))
303 continue;
304
305 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
306 continue;
307
308
309 channels[count].center_freq = freq;
310 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
311 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
312 switch (mode) {
313 case AR5K_MODE_11A:
314 case AR5K_MODE_11G:
315 channels[count].hw_value = chfreq | CHANNEL_OFDM;
316 break;
317 case AR5K_MODE_11B:
318 channels[count].hw_value = CHANNEL_B;
319 }
320
321 count++;
322 max--;
323 }
324
325 return count;
326}
327
328static void
329ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
330{
331 u8 i;
332
333 for (i = 0; i < AR5K_MAX_RATES; i++)
334 sc->rate_idx[b->band][i] = -1;
335
336 for (i = 0; i < b->n_bitrates; i++) {
337 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
338 if (b->bitrates[i].hw_value_short)
339 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
340 }
341}
342
343static int
344ath5k_setup_bands(struct ieee80211_hw *hw)
345{
346 struct ath5k_softc *sc = hw->priv;
347 struct ath5k_hw *ah = sc->ah;
348 struct ieee80211_supported_band *sband;
349 int max_c, count_c = 0;
350 int i;
351
352 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
353 max_c = ARRAY_SIZE(sc->channels);
354
355
356 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
357 sband->band = IEEE80211_BAND_2GHZ;
358 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
359
360 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
361
362 memcpy(sband->bitrates, &ath5k_rates[0],
363 sizeof(struct ieee80211_rate) * 12);
364 sband->n_bitrates = 12;
365
366 sband->channels = sc->channels;
367 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
368 AR5K_MODE_11G, max_c);
369
370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
371 count_c = sband->n_channels;
372 max_c -= count_c;
373 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
374
375 memcpy(sband->bitrates, &ath5k_rates[0],
376 sizeof(struct ieee80211_rate) * 4);
377 sband->n_bitrates = 4;
378
379
380
381
382
383 if (ah->ah_version == AR5K_AR5211) {
384 for (i = 0; i < 4; i++) {
385 sband->bitrates[i].hw_value =
386 sband->bitrates[i].hw_value & 0xF;
387 sband->bitrates[i].hw_value_short =
388 sband->bitrates[i].hw_value_short & 0xF;
389 }
390 }
391
392 sband->channels = sc->channels;
393 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
394 AR5K_MODE_11B, max_c);
395
396 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
397 count_c = sband->n_channels;
398 max_c -= count_c;
399 }
400 ath5k_setup_rate_idx(sc, sband);
401
402
403 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
404 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
405 sband->band = IEEE80211_BAND_5GHZ;
406 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
407
408 memcpy(sband->bitrates, &ath5k_rates[4],
409 sizeof(struct ieee80211_rate) * 8);
410 sband->n_bitrates = 8;
411
412 sband->channels = &sc->channels[count_c];
413 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
414 AR5K_MODE_11A, max_c);
415
416 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
417 }
418 ath5k_setup_rate_idx(sc, sband);
419
420 ath5k_debug_dump_bands(sc);
421
422 return 0;
423}
424
425
426
427
428
429
430
431
432int
433ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
434{
435 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
436 "channel set, resetting (%u -> %u MHz)\n",
437 sc->curchan->center_freq, chan->center_freq);
438
439
440
441
442
443
444
445 return ath5k_reset(sc, chan, true);
446}
447
448static void
449ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
450{
451 sc->curmode = mode;
452
453 if (mode == AR5K_MODE_11A) {
454 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
455 } else {
456 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
457 }
458}
459
460struct ath_vif_iter_data {
461 const u8 *hw_macaddr;
462 u8 mask[ETH_ALEN];
463 u8 active_mac[ETH_ALEN];
464 bool need_set_hw_addr;
465 bool found_active;
466 bool any_assoc;
467 enum nl80211_iftype opmode;
468};
469
470static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
471{
472 struct ath_vif_iter_data *iter_data = data;
473 int i;
474 struct ath5k_vif *avf = (void *)vif->drv_priv;
475
476 if (iter_data->hw_macaddr)
477 for (i = 0; i < ETH_ALEN; i++)
478 iter_data->mask[i] &=
479 ~(iter_data->hw_macaddr[i] ^ mac[i]);
480
481 if (!iter_data->found_active) {
482 iter_data->found_active = true;
483 memcpy(iter_data->active_mac, mac, ETH_ALEN);
484 }
485
486 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
487 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
488 iter_data->need_set_hw_addr = false;
489
490 if (!iter_data->any_assoc) {
491 if (avf->assoc)
492 iter_data->any_assoc = true;
493 }
494
495
496
497
498
499
500 if (avf->opmode == NL80211_IFTYPE_AP)
501 iter_data->opmode = NL80211_IFTYPE_AP;
502 else
503 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
504 iter_data->opmode = avf->opmode;
505}
506
507void
508ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
509 struct ieee80211_vif *vif)
510{
511 struct ath_common *common = ath5k_hw_common(sc->ah);
512 struct ath_vif_iter_data iter_data;
513
514
515
516
517
518 iter_data.hw_macaddr = common->macaddr;
519 memset(&iter_data.mask, 0xff, ETH_ALEN);
520 iter_data.found_active = false;
521 iter_data.need_set_hw_addr = true;
522 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
523
524 if (vif)
525 ath_vif_iter(&iter_data, vif->addr, vif);
526
527
528 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
529 &iter_data);
530 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
531
532 sc->opmode = iter_data.opmode;
533 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
534
535 sc->opmode = NL80211_IFTYPE_STATION;
536
537 ath5k_hw_set_opmode(sc->ah, sc->opmode);
538 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
539 sc->opmode, ath_opmode_to_string(sc->opmode));
540
541 if (iter_data.need_set_hw_addr && iter_data.found_active)
542 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
543
544 if (ath5k_hw_hasbssidmask(sc->ah))
545 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
546}
547
548void
549ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
550{
551 struct ath5k_hw *ah = sc->ah;
552 u32 rfilt;
553
554
555 rfilt = sc->filter_flags;
556 ath5k_hw_set_rx_filter(ah, rfilt);
557 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
558
559 ath5k_update_bssid_mask_and_opmode(sc, vif);
560}
561
562static inline int
563ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
564{
565 int rix;
566
567
568 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
569 "hw_rix out of bounds: %x\n", hw_rix))
570 return 0;
571
572 rix = sc->rate_idx[sc->curband->band][hw_rix];
573 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
574 rix = 0;
575
576 return rix;
577}
578
579
580
581
582
583static
584struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
585{
586 struct ath_common *common = ath5k_hw_common(sc->ah);
587 struct sk_buff *skb;
588
589
590
591
592
593 skb = ath_rxbuf_alloc(common,
594 common->rx_bufsize,
595 GFP_ATOMIC);
596
597 if (!skb) {
598 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
599 common->rx_bufsize);
600 return NULL;
601 }
602
603 *skb_addr = dma_map_single(sc->dev,
604 skb->data, common->rx_bufsize,
605 DMA_FROM_DEVICE);
606
607 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
608 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
609 dev_kfree_skb(skb);
610 return NULL;
611 }
612 return skb;
613}
614
615static int
616ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
617{
618 struct ath5k_hw *ah = sc->ah;
619 struct sk_buff *skb = bf->skb;
620 struct ath5k_desc *ds;
621 int ret;
622
623 if (!skb) {
624 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
625 if (!skb)
626 return -ENOMEM;
627 bf->skb = skb;
628 }
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645 ds = bf->desc;
646 ds->ds_link = bf->daddr;
647 ds->ds_data = bf->skbaddr;
648 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
649 if (ret) {
650 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
651 return ret;
652 }
653
654 if (sc->rxlink != NULL)
655 *sc->rxlink = bf->daddr;
656 sc->rxlink = &ds->ds_link;
657 return 0;
658}
659
660static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
661{
662 struct ieee80211_hdr *hdr;
663 enum ath5k_pkt_type htype;
664 __le16 fc;
665
666 hdr = (struct ieee80211_hdr *)skb->data;
667 fc = hdr->frame_control;
668
669 if (ieee80211_is_beacon(fc))
670 htype = AR5K_PKT_TYPE_BEACON;
671 else if (ieee80211_is_probe_resp(fc))
672 htype = AR5K_PKT_TYPE_PROBE_RESP;
673 else if (ieee80211_is_atim(fc))
674 htype = AR5K_PKT_TYPE_ATIM;
675 else if (ieee80211_is_pspoll(fc))
676 htype = AR5K_PKT_TYPE_PSPOLL;
677 else
678 htype = AR5K_PKT_TYPE_NORMAL;
679
680 return htype;
681}
682
683static int
684ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
685 struct ath5k_txq *txq, int padsize)
686{
687 struct ath5k_hw *ah = sc->ah;
688 struct ath5k_desc *ds = bf->desc;
689 struct sk_buff *skb = bf->skb;
690 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
691 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
692 struct ieee80211_rate *rate;
693 unsigned int mrr_rate[3], mrr_tries[3];
694 int i, ret;
695 u16 hw_rate;
696 u16 cts_rate = 0;
697 u16 duration = 0;
698 u8 rc_flags;
699
700 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
701
702
703 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
704 DMA_TO_DEVICE);
705
706 rate = ieee80211_get_tx_rate(sc->hw, info);
707 if (!rate) {
708 ret = -EINVAL;
709 goto err_unmap;
710 }
711
712 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
713 flags |= AR5K_TXDESC_NOACK;
714
715 rc_flags = info->control.rates[0].flags;
716 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
717 rate->hw_value_short : rate->hw_value;
718
719 pktlen = skb->len;
720
721
722
723
724 if (info->control.hw_key) {
725 keyidx = info->control.hw_key->hw_key_idx;
726 pktlen += info->control.hw_key->icv_len;
727 }
728 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
729 flags |= AR5K_TXDESC_RTSENA;
730 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
731 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
732 info->control.vif, pktlen, info));
733 }
734 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
735 flags |= AR5K_TXDESC_CTSENA;
736 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
737 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
738 info->control.vif, pktlen, info));
739 }
740 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
741 ieee80211_get_hdrlen_from_skb(skb), padsize,
742 get_hw_packet_type(skb),
743 (sc->power_level * 2),
744 hw_rate,
745 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
746 cts_rate, duration);
747 if (ret)
748 goto err_unmap;
749
750 memset(mrr_rate, 0, sizeof(mrr_rate));
751 memset(mrr_tries, 0, sizeof(mrr_tries));
752 for (i = 0; i < 3; i++) {
753 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
754 if (!rate)
755 break;
756
757 mrr_rate[i] = rate->hw_value;
758 mrr_tries[i] = info->control.rates[i + 1].count;
759 }
760
761 ath5k_hw_setup_mrr_tx_desc(ah, ds,
762 mrr_rate[0], mrr_tries[0],
763 mrr_rate[1], mrr_tries[1],
764 mrr_rate[2], mrr_tries[2]);
765
766 ds->ds_link = 0;
767 ds->ds_data = bf->skbaddr;
768
769 spin_lock_bh(&txq->lock);
770 list_add_tail(&bf->list, &txq->q);
771 txq->txq_len++;
772 if (txq->link == NULL)
773 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
774 else
775 *txq->link = bf->daddr;
776
777 txq->link = &ds->ds_link;
778 ath5k_hw_start_tx_dma(ah, txq->qnum);
779 mmiowb();
780 spin_unlock_bh(&txq->lock);
781
782 return 0;
783err_unmap:
784 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
785 return ret;
786}
787
788
789
790
791
792static int
793ath5k_desc_alloc(struct ath5k_softc *sc)
794{
795 struct ath5k_desc *ds;
796 struct ath5k_buf *bf;
797 dma_addr_t da;
798 unsigned int i;
799 int ret;
800
801
802 sc->desc_len = sizeof(struct ath5k_desc) *
803 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
804
805 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
806 &sc->desc_daddr, GFP_KERNEL);
807 if (sc->desc == NULL) {
808 ATH5K_ERR(sc, "can't allocate descriptors\n");
809 ret = -ENOMEM;
810 goto err;
811 }
812 ds = sc->desc;
813 da = sc->desc_daddr;
814 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
815 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
816
817 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
818 sizeof(struct ath5k_buf), GFP_KERNEL);
819 if (bf == NULL) {
820 ATH5K_ERR(sc, "can't allocate bufptr\n");
821 ret = -ENOMEM;
822 goto err_free;
823 }
824 sc->bufptr = bf;
825
826 INIT_LIST_HEAD(&sc->rxbuf);
827 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
828 bf->desc = ds;
829 bf->daddr = da;
830 list_add_tail(&bf->list, &sc->rxbuf);
831 }
832
833 INIT_LIST_HEAD(&sc->txbuf);
834 sc->txbuf_len = ATH_TXBUF;
835 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
836 da += sizeof(*ds)) {
837 bf->desc = ds;
838 bf->daddr = da;
839 list_add_tail(&bf->list, &sc->txbuf);
840 }
841
842
843 INIT_LIST_HEAD(&sc->bcbuf);
844 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
845 bf->desc = ds;
846 bf->daddr = da;
847 list_add_tail(&bf->list, &sc->bcbuf);
848 }
849
850 return 0;
851err_free:
852 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
853err:
854 sc->desc = NULL;
855 return ret;
856}
857
858void
859ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
860{
861 BUG_ON(!bf);
862 if (!bf->skb)
863 return;
864 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
865 DMA_TO_DEVICE);
866 dev_kfree_skb_any(bf->skb);
867 bf->skb = NULL;
868 bf->skbaddr = 0;
869 bf->desc->ds_data = 0;
870}
871
872void
873ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
874{
875 struct ath5k_hw *ah = sc->ah;
876 struct ath_common *common = ath5k_hw_common(ah);
877
878 BUG_ON(!bf);
879 if (!bf->skb)
880 return;
881 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
882 DMA_FROM_DEVICE);
883 dev_kfree_skb_any(bf->skb);
884 bf->skb = NULL;
885 bf->skbaddr = 0;
886 bf->desc->ds_data = 0;
887}
888
889static void
890ath5k_desc_free(struct ath5k_softc *sc)
891{
892 struct ath5k_buf *bf;
893
894 list_for_each_entry(bf, &sc->txbuf, list)
895 ath5k_txbuf_free_skb(sc, bf);
896 list_for_each_entry(bf, &sc->rxbuf, list)
897 ath5k_rxbuf_free_skb(sc, bf);
898 list_for_each_entry(bf, &sc->bcbuf, list)
899 ath5k_txbuf_free_skb(sc, bf);
900
901
902 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
903 sc->desc = NULL;
904 sc->desc_daddr = 0;
905
906 kfree(sc->bufptr);
907 sc->bufptr = NULL;
908}
909
910
911
912
913
914
915static struct ath5k_txq *
916ath5k_txq_setup(struct ath5k_softc *sc,
917 int qtype, int subtype)
918{
919 struct ath5k_hw *ah = sc->ah;
920 struct ath5k_txq *txq;
921 struct ath5k_txq_info qi = {
922 .tqi_subtype = subtype,
923
924
925 .tqi_aifs = AR5K_TUNE_AIFS,
926 .tqi_cw_min = AR5K_TUNE_CWMIN,
927 .tqi_cw_max = AR5K_TUNE_CWMAX
928 };
929 int qnum;
930
931
932
933
934
935
936
937
938
939
940
941
942
943 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
944 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
945 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
946 if (qnum < 0) {
947
948
949
950
951 return ERR_PTR(qnum);
952 }
953 if (qnum >= ARRAY_SIZE(sc->txqs)) {
954 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
955 qnum, ARRAY_SIZE(sc->txqs));
956 ath5k_hw_release_tx_queue(ah, qnum);
957 return ERR_PTR(-EINVAL);
958 }
959 txq = &sc->txqs[qnum];
960 if (!txq->setup) {
961 txq->qnum = qnum;
962 txq->link = NULL;
963 INIT_LIST_HEAD(&txq->q);
964 spin_lock_init(&txq->lock);
965 txq->setup = true;
966 txq->txq_len = 0;
967 txq->txq_poll_mark = false;
968 txq->txq_stuck = 0;
969 }
970 return &sc->txqs[qnum];
971}
972
973static int
974ath5k_beaconq_setup(struct ath5k_hw *ah)
975{
976 struct ath5k_txq_info qi = {
977
978
979 .tqi_aifs = AR5K_TUNE_AIFS,
980 .tqi_cw_min = AR5K_TUNE_CWMIN,
981 .tqi_cw_max = AR5K_TUNE_CWMAX,
982
983 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
984 };
985
986 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
987}
988
989static int
990ath5k_beaconq_config(struct ath5k_softc *sc)
991{
992 struct ath5k_hw *ah = sc->ah;
993 struct ath5k_txq_info qi;
994 int ret;
995
996 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
997 if (ret)
998 goto err;
999
1000 if (sc->opmode == NL80211_IFTYPE_AP ||
1001 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1002
1003
1004
1005
1006 qi.tqi_aifs = 0;
1007 qi.tqi_cw_min = 0;
1008 qi.tqi_cw_max = 0;
1009 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1010
1011
1012
1013 qi.tqi_aifs = 0;
1014 qi.tqi_cw_min = 0;
1015 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
1016 }
1017
1018 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1019 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1020 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1021
1022 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1023 if (ret) {
1024 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1025 "hardware queue!\n", __func__);
1026 goto err;
1027 }
1028 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq);
1029 if (ret)
1030 goto err;
1031
1032
1033 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1034 if (ret)
1035 goto err;
1036
1037 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1038 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1039 if (ret)
1040 goto err;
1041
1042 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1043err:
1044 return ret;
1045}
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058static void
1059ath5k_drain_tx_buffs(struct ath5k_softc *sc)
1060{
1061 struct ath5k_txq *txq;
1062 struct ath5k_buf *bf, *bf0;
1063 int i;
1064
1065 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1066 if (sc->txqs[i].setup) {
1067 txq = &sc->txqs[i];
1068 spin_lock_bh(&txq->lock);
1069 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1070 ath5k_debug_printtxbuf(sc, bf);
1071
1072 ath5k_txbuf_free_skb(sc, bf);
1073
1074 spin_lock_bh(&sc->txbuflock);
1075 list_move_tail(&bf->list, &sc->txbuf);
1076 sc->txbuf_len++;
1077 txq->txq_len--;
1078 spin_unlock_bh(&sc->txbuflock);
1079 }
1080 txq->link = NULL;
1081 txq->txq_poll_mark = false;
1082 spin_unlock_bh(&txq->lock);
1083 }
1084 }
1085}
1086
1087static void
1088ath5k_txq_release(struct ath5k_softc *sc)
1089{
1090 struct ath5k_txq *txq = sc->txqs;
1091 unsigned int i;
1092
1093 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1094 if (txq->setup) {
1095 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1096 txq->setup = false;
1097 }
1098}
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108static int
1109ath5k_rx_start(struct ath5k_softc *sc)
1110{
1111 struct ath5k_hw *ah = sc->ah;
1112 struct ath_common *common = ath5k_hw_common(ah);
1113 struct ath5k_buf *bf;
1114 int ret;
1115
1116 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1117
1118 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1119 common->cachelsz, common->rx_bufsize);
1120
1121 spin_lock_bh(&sc->rxbuflock);
1122 sc->rxlink = NULL;
1123 list_for_each_entry(bf, &sc->rxbuf, list) {
1124 ret = ath5k_rxbuf_setup(sc, bf);
1125 if (ret != 0) {
1126 spin_unlock_bh(&sc->rxbuflock);
1127 goto err;
1128 }
1129 }
1130 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1131 ath5k_hw_set_rxdp(ah, bf->daddr);
1132 spin_unlock_bh(&sc->rxbuflock);
1133
1134 ath5k_hw_start_rx_dma(ah);
1135 ath5k_mode_setup(sc, NULL);
1136 ath5k_hw_start_rx_pcu(ah);
1137
1138 return 0;
1139err:
1140 return ret;
1141}
1142
1143
1144
1145
1146
1147
1148
1149
1150static void
1151ath5k_rx_stop(struct ath5k_softc *sc)
1152{
1153 struct ath5k_hw *ah = sc->ah;
1154
1155 ath5k_hw_set_rx_filter(ah, 0);
1156 ath5k_hw_stop_rx_pcu(ah);
1157
1158 ath5k_debug_printrxbuffs(sc, ah);
1159}
1160
1161static unsigned int
1162ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1163 struct ath5k_rx_status *rs)
1164{
1165 struct ath5k_hw *ah = sc->ah;
1166 struct ath_common *common = ath5k_hw_common(ah);
1167 struct ieee80211_hdr *hdr = (void *)skb->data;
1168 unsigned int keyix, hlen;
1169
1170 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1171 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1172 return RX_FLAG_DECRYPTED;
1173
1174
1175
1176
1177 hlen = ieee80211_hdrlen(hdr->frame_control);
1178 if (ieee80211_has_protected(hdr->frame_control) &&
1179 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1180 skb->len >= hlen + 4) {
1181 keyix = skb->data[hlen + 3] >> 6;
1182
1183 if (test_bit(keyix, common->keymap))
1184 return RX_FLAG_DECRYPTED;
1185 }
1186
1187 return 0;
1188}
1189
1190
1191static void
1192ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1193 struct ieee80211_rx_status *rxs)
1194{
1195 struct ath_common *common = ath5k_hw_common(sc->ah);
1196 u64 tsf, bc_tstamp;
1197 u32 hw_tu;
1198 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1199
1200 if (ieee80211_is_beacon(mgmt->frame_control) &&
1201 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1202 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1203
1204
1205
1206
1207
1208 tsf = ath5k_hw_get_tsf64(sc->ah);
1209 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1210 hw_tu = TSF_TO_TU(tsf);
1211
1212 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1213 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1214 (unsigned long long)bc_tstamp,
1215 (unsigned long long)rxs->mactime,
1216 (unsigned long long)(rxs->mactime - bc_tstamp),
1217 (unsigned long long)tsf);
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230 if (bc_tstamp > rxs->mactime) {
1231 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1232 "fixing mactime from %llx to %llx\n",
1233 (unsigned long long)rxs->mactime,
1234 (unsigned long long)tsf);
1235 rxs->mactime = tsf;
1236 }
1237
1238
1239
1240
1241
1242
1243
1244 if (hw_tu >= sc->nexttbtt)
1245 ath5k_beacon_update_timers(sc, bc_tstamp);
1246
1247
1248
1249
1250 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1251 ath5k_beacon_update_timers(sc, bc_tstamp);
1252 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1253 "fixed beacon timers after beacon receive\n");
1254 }
1255 }
1256}
1257
1258static void
1259ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1260{
1261 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1262 struct ath5k_hw *ah = sc->ah;
1263 struct ath_common *common = ath5k_hw_common(ah);
1264
1265
1266 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1267 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1268 return;
1269
1270 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
1271
1272
1273
1274}
1275
1276
1277
1278
1279static int ath5k_common_padpos(struct sk_buff *skb)
1280{
1281 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1282 __le16 frame_control = hdr->frame_control;
1283 int padpos = 24;
1284
1285 if (ieee80211_has_a4(frame_control)) {
1286 padpos += ETH_ALEN;
1287 }
1288 if (ieee80211_is_data_qos(frame_control)) {
1289 padpos += IEEE80211_QOS_CTL_LEN;
1290 }
1291
1292 return padpos;
1293}
1294
1295
1296
1297
1298
1299static int ath5k_add_padding(struct sk_buff *skb)
1300{
1301 int padpos = ath5k_common_padpos(skb);
1302 int padsize = padpos & 3;
1303
1304 if (padsize && skb->len>padpos) {
1305
1306 if (skb_headroom(skb) < padsize)
1307 return -1;
1308
1309 skb_push(skb, padsize);
1310 memmove(skb->data, skb->data+padsize, padpos);
1311 return padsize;
1312 }
1313
1314 return 0;
1315}
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330static int ath5k_remove_padding(struct sk_buff *skb)
1331{
1332 int padpos = ath5k_common_padpos(skb);
1333 int padsize = padpos & 3;
1334
1335 if (padsize && skb->len>=padpos+padsize) {
1336 memmove(skb->data + padsize, skb->data, padpos);
1337 skb_pull(skb, padsize);
1338 return padsize;
1339 }
1340
1341 return 0;
1342}
1343
1344static void
1345ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1346 struct ath5k_rx_status *rs)
1347{
1348 struct ieee80211_rx_status *rxs;
1349
1350 ath5k_remove_padding(skb);
1351
1352 rxs = IEEE80211_SKB_RXCB(skb);
1353
1354 rxs->flag = 0;
1355 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1356 rxs->flag |= RX_FLAG_MMIC_ERROR;
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1379 rxs->flag |= RX_FLAG_TSFT;
1380
1381 rxs->freq = sc->curchan->center_freq;
1382 rxs->band = sc->curband->band;
1383
1384 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
1385
1386 rxs->antenna = rs->rs_antenna;
1387
1388 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1389 sc->stats.antenna_rx[rs->rs_antenna]++;
1390 else
1391 sc->stats.antenna_rx[0]++;
1392
1393 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1394 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
1395
1396 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1397 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1398 rxs->flag |= RX_FLAG_SHORTPRE;
1399
1400 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1401
1402 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
1403
1404
1405 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1406 ath5k_check_ibss_tsf(sc, skb, rxs);
1407
1408 ieee80211_rx(sc->hw, skb);
1409}
1410
1411
1412
1413
1414
1415
1416static bool
1417ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1418{
1419 sc->stats.rx_all_count++;
1420 sc->stats.rx_bytes_count += rs->rs_datalen;
1421
1422 if (unlikely(rs->rs_status)) {
1423 if (rs->rs_status & AR5K_RXERR_CRC)
1424 sc->stats.rxerr_crc++;
1425 if (rs->rs_status & AR5K_RXERR_FIFO)
1426 sc->stats.rxerr_fifo++;
1427 if (rs->rs_status & AR5K_RXERR_PHY) {
1428 sc->stats.rxerr_phy++;
1429 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1430 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1431 return false;
1432 }
1433 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444 sc->stats.rxerr_decrypt++;
1445 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1446 !(rs->rs_status & AR5K_RXERR_CRC))
1447 return true;
1448 }
1449 if (rs->rs_status & AR5K_RXERR_MIC) {
1450 sc->stats.rxerr_mic++;
1451 return true;
1452 }
1453
1454
1455 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1456 return false;
1457 }
1458
1459 if (unlikely(rs->rs_more)) {
1460 sc->stats.rxerr_jumbo++;
1461 return false;
1462 }
1463 return true;
1464}
1465
1466static void
1467ath5k_tasklet_rx(unsigned long data)
1468{
1469 struct ath5k_rx_status rs = {};
1470 struct sk_buff *skb, *next_skb;
1471 dma_addr_t next_skb_addr;
1472 struct ath5k_softc *sc = (void *)data;
1473 struct ath5k_hw *ah = sc->ah;
1474 struct ath_common *common = ath5k_hw_common(ah);
1475 struct ath5k_buf *bf;
1476 struct ath5k_desc *ds;
1477 int ret;
1478
1479 spin_lock(&sc->rxbuflock);
1480 if (list_empty(&sc->rxbuf)) {
1481 ATH5K_WARN(sc, "empty rx buf pool\n");
1482 goto unlock;
1483 }
1484 do {
1485 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1486 BUG_ON(bf->skb == NULL);
1487 skb = bf->skb;
1488 ds = bf->desc;
1489
1490
1491 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1492 break;
1493
1494 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1495 if (unlikely(ret == -EINPROGRESS))
1496 break;
1497 else if (unlikely(ret)) {
1498 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1499 sc->stats.rxerr_proc++;
1500 break;
1501 }
1502
1503 if (ath5k_receive_frame_ok(sc, &rs)) {
1504 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1505
1506
1507
1508
1509
1510 if (!next_skb)
1511 goto next;
1512
1513 dma_unmap_single(sc->dev, bf->skbaddr,
1514 common->rx_bufsize,
1515 DMA_FROM_DEVICE);
1516
1517 skb_put(skb, rs.rs_datalen);
1518
1519 ath5k_receive_frame(sc, skb, &rs);
1520
1521 bf->skb = next_skb;
1522 bf->skbaddr = next_skb_addr;
1523 }
1524next:
1525 list_move_tail(&bf->list, &sc->rxbuf);
1526 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1527unlock:
1528 spin_unlock(&sc->rxbuflock);
1529}
1530
1531
1532
1533
1534
1535
1536int
1537ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1538 struct ath5k_txq *txq)
1539{
1540 struct ath5k_softc *sc = hw->priv;
1541 struct ath5k_buf *bf;
1542 unsigned long flags;
1543 int padsize;
1544
1545 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
1546
1547
1548
1549
1550
1551 padsize = ath5k_add_padding(skb);
1552 if (padsize < 0) {
1553 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1554 " headroom to pad");
1555 goto drop_packet;
1556 }
1557
1558 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1559 ieee80211_stop_queue(hw, txq->qnum);
1560
1561 spin_lock_irqsave(&sc->txbuflock, flags);
1562 if (list_empty(&sc->txbuf)) {
1563 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1564 spin_unlock_irqrestore(&sc->txbuflock, flags);
1565 ieee80211_stop_queues(hw);
1566 goto drop_packet;
1567 }
1568 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1569 list_del(&bf->list);
1570 sc->txbuf_len--;
1571 if (list_empty(&sc->txbuf))
1572 ieee80211_stop_queues(hw);
1573 spin_unlock_irqrestore(&sc->txbuflock, flags);
1574
1575 bf->skb = skb;
1576
1577 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1578 bf->skb = NULL;
1579 spin_lock_irqsave(&sc->txbuflock, flags);
1580 list_add_tail(&bf->list, &sc->txbuf);
1581 sc->txbuf_len++;
1582 spin_unlock_irqrestore(&sc->txbuflock, flags);
1583 goto drop_packet;
1584 }
1585 return NETDEV_TX_OK;
1586
1587drop_packet:
1588 dev_kfree_skb_any(skb);
1589 return NETDEV_TX_OK;
1590}
1591
1592static void
1593ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1594 struct ath5k_tx_status *ts)
1595{
1596 struct ieee80211_tx_info *info;
1597 int i;
1598
1599 sc->stats.tx_all_count++;
1600 sc->stats.tx_bytes_count += skb->len;
1601 info = IEEE80211_SKB_CB(skb);
1602
1603 ieee80211_tx_info_clear_status(info);
1604 for (i = 0; i < 4; i++) {
1605 struct ieee80211_tx_rate *r =
1606 &info->status.rates[i];
1607
1608 if (ts->ts_rate[i]) {
1609 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1610 r->count = ts->ts_retry[i];
1611 } else {
1612 r->idx = -1;
1613 r->count = 0;
1614 }
1615 }
1616
1617
1618 info->status.rates[ts->ts_final_idx].count++;
1619
1620 if (unlikely(ts->ts_status)) {
1621 sc->stats.ack_fail++;
1622 if (ts->ts_status & AR5K_TXERR_FILT) {
1623 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1624 sc->stats.txerr_filt++;
1625 }
1626 if (ts->ts_status & AR5K_TXERR_XRETRY)
1627 sc->stats.txerr_retry++;
1628 if (ts->ts_status & AR5K_TXERR_FIFO)
1629 sc->stats.txerr_fifo++;
1630 } else {
1631 info->flags |= IEEE80211_TX_STAT_ACK;
1632 info->status.ack_signal = ts->ts_rssi;
1633 }
1634
1635
1636
1637
1638
1639 ath5k_remove_padding(skb);
1640
1641 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1642 sc->stats.antenna_tx[ts->ts_antenna]++;
1643 else
1644 sc->stats.antenna_tx[0]++;
1645
1646 ieee80211_tx_status(sc->hw, skb);
1647}
1648
1649static void
1650ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1651{
1652 struct ath5k_tx_status ts = {};
1653 struct ath5k_buf *bf, *bf0;
1654 struct ath5k_desc *ds;
1655 struct sk_buff *skb;
1656 int ret;
1657
1658 spin_lock(&txq->lock);
1659 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1660
1661 txq->txq_poll_mark = false;
1662
1663
1664 if (bf->skb != NULL) {
1665 ds = bf->desc;
1666
1667 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1668 if (unlikely(ret == -EINPROGRESS))
1669 break;
1670 else if (unlikely(ret)) {
1671 ATH5K_ERR(sc,
1672 "error %d while processing "
1673 "queue %u\n", ret, txq->qnum);
1674 break;
1675 }
1676
1677 skb = bf->skb;
1678 bf->skb = NULL;
1679
1680 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1681 DMA_TO_DEVICE);
1682 ath5k_tx_frame_completed(sc, skb, &ts);
1683 }
1684
1685
1686
1687
1688
1689
1690
1691 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1692 spin_lock(&sc->txbuflock);
1693 list_move_tail(&bf->list, &sc->txbuf);
1694 sc->txbuf_len++;
1695 txq->txq_len--;
1696 spin_unlock(&sc->txbuflock);
1697 }
1698 }
1699 spin_unlock(&txq->lock);
1700 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1701 ieee80211_wake_queue(sc->hw, txq->qnum);
1702}
1703
1704static void
1705ath5k_tasklet_tx(unsigned long data)
1706{
1707 int i;
1708 struct ath5k_softc *sc = (void *)data;
1709
1710 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1711 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1712 ath5k_tx_processq(sc, &sc->txqs[i]);
1713}
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723static int
1724ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1725{
1726 struct sk_buff *skb = bf->skb;
1727 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1728 struct ath5k_hw *ah = sc->ah;
1729 struct ath5k_desc *ds;
1730 int ret = 0;
1731 u8 antenna;
1732 u32 flags;
1733 const int padsize = 0;
1734
1735 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1736 DMA_TO_DEVICE);
1737 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1738 "skbaddr %llx\n", skb, skb->data, skb->len,
1739 (unsigned long long)bf->skbaddr);
1740
1741 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
1742 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1743 return -EIO;
1744 }
1745
1746 ds = bf->desc;
1747 antenna = ah->ah_tx_ant;
1748
1749 flags = AR5K_TXDESC_NOACK;
1750 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1751 ds->ds_link = bf->daddr;
1752 flags |= AR5K_TXDESC_VEOL;
1753 } else
1754 ds->ds_link = 0;
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1775 antenna = sc->bsent & 4 ? 2 : 1;
1776
1777
1778
1779
1780
1781 ds->ds_data = bf->skbaddr;
1782 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1783 ieee80211_get_hdrlen_from_skb(skb), padsize,
1784 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1785 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1786 1, AR5K_TXKEYIX_INVALID,
1787 antenna, flags, 0, 0);
1788 if (ret)
1789 goto err_unmap;
1790
1791 return 0;
1792err_unmap:
1793 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1794 return ret;
1795}
1796
1797
1798
1799
1800
1801
1802
1803
1804int
1805ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1806{
1807 int ret;
1808 struct ath5k_softc *sc = hw->priv;
1809 struct ath5k_vif *avf = (void *)vif->drv_priv;
1810 struct sk_buff *skb;
1811
1812 if (WARN_ON(!vif)) {
1813 ret = -EINVAL;
1814 goto out;
1815 }
1816
1817 skb = ieee80211_beacon_get(hw, vif);
1818
1819 if (!skb) {
1820 ret = -ENOMEM;
1821 goto out;
1822 }
1823
1824 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1825
1826 ath5k_txbuf_free_skb(sc, avf->bbuf);
1827 avf->bbuf->skb = skb;
1828 ret = ath5k_beacon_setup(sc, avf->bbuf);
1829 if (ret)
1830 avf->bbuf->skb = NULL;
1831out:
1832 return ret;
1833}
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843static void
1844ath5k_beacon_send(struct ath5k_softc *sc)
1845{
1846 struct ath5k_hw *ah = sc->ah;
1847 struct ieee80211_vif *vif;
1848 struct ath5k_vif *avf;
1849 struct ath5k_buf *bf;
1850 struct sk_buff *skb;
1851
1852 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1853
1854
1855
1856
1857
1858
1859
1860
1861 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1862 sc->bmisscount++;
1863 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1864 "missed %u consecutive beacons\n", sc->bmisscount);
1865 if (sc->bmisscount > 10) {
1866 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1867 "stuck beacon time (%u missed)\n",
1868 sc->bmisscount);
1869 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1870 "stuck beacon, resetting\n");
1871 ieee80211_queue_work(sc->hw, &sc->reset_work);
1872 }
1873 return;
1874 }
1875 if (unlikely(sc->bmisscount != 0)) {
1876 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1877 "resume beacon xmit after %u misses\n",
1878 sc->bmisscount);
1879 sc->bmisscount = 0;
1880 }
1881
1882 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
1883 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1884 u64 tsf = ath5k_hw_get_tsf64(ah);
1885 u32 tsftu = TSF_TO_TU(tsf);
1886 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1887 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1888 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1889 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1890 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1891 } else
1892 vif = sc->bslot[0];
1893
1894 if (!vif)
1895 return;
1896
1897 avf = (void *)vif->drv_priv;
1898 bf = avf->bbuf;
1899 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1900 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1901 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1902 return;
1903 }
1904
1905
1906
1907
1908
1909
1910 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
1911 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
1912
1913 }
1914
1915
1916 if (sc->opmode == NL80211_IFTYPE_AP ||
1917 sc->opmode == NL80211_IFTYPE_MESH_POINT)
1918 ath5k_beacon_update(sc->hw, vif);
1919
1920 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1921 ath5k_hw_start_tx_dma(ah, sc->bhalq);
1922 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1923 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1924
1925 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1926 while (skb) {
1927 ath5k_tx_queue(sc->hw, skb, sc->cabq);
1928 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1929 }
1930
1931 sc->bsent++;
1932}
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950void
1951ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
1952{
1953 struct ath5k_hw *ah = sc->ah;
1954 u32 nexttbtt, intval, hw_tu, bc_tu;
1955 u64 hw_tsf;
1956
1957 intval = sc->bintval & AR5K_BEACON_PERIOD;
1958 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1959 intval /= ATH_BCBUF;
1960 if (intval < 15)
1961 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1962 intval);
1963 }
1964 if (WARN_ON(!intval))
1965 return;
1966
1967
1968 bc_tu = TSF_TO_TU(bc_tsf);
1969
1970
1971 hw_tsf = ath5k_hw_get_tsf64(ah);
1972 hw_tu = TSF_TO_TU(hw_tsf);
1973
1974#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1975
1976
1977
1978
1979 if (bc_tsf == -1) {
1980
1981
1982
1983
1984 nexttbtt = roundup(hw_tu + FUDGE, intval);
1985 } else if (bc_tsf == 0) {
1986
1987
1988
1989
1990 nexttbtt = intval;
1991 intval |= AR5K_BEACON_RESET_TSF;
1992 } else if (bc_tsf > hw_tsf) {
1993
1994
1995
1996
1997
1998
1999
2000 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2001 "need to wait for HW TSF sync\n");
2002 return;
2003 } else {
2004
2005
2006
2007
2008
2009
2010
2011 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2012 }
2013#undef FUDGE
2014
2015 sc->nexttbtt = nexttbtt;
2016
2017 intval |= AR5K_BEACON_ENA;
2018 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2019
2020
2021
2022
2023
2024 if (bc_tsf == -1)
2025 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2026 "reconfigured timers based on HW TSF\n");
2027 else if (bc_tsf == 0)
2028 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2029 "reset HW TSF and timers\n");
2030 else
2031 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2032 "updated timers based on beacon TSF\n");
2033
2034 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2035 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2036 (unsigned long long) bc_tsf,
2037 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2038 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2039 intval & AR5K_BEACON_PERIOD,
2040 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2041 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2042}
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052void
2053ath5k_beacon_config(struct ath5k_softc *sc)
2054{
2055 struct ath5k_hw *ah = sc->ah;
2056 unsigned long flags;
2057
2058 spin_lock_irqsave(&sc->block, flags);
2059 sc->bmisscount = 0;
2060 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2061
2062 if (sc->enable_beacon) {
2063
2064
2065
2066
2067
2068
2069
2070 ath5k_beaconq_config(sc);
2071
2072 sc->imask |= AR5K_INT_SWBA;
2073
2074 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2075 if (ath5k_hw_hasveol(ah))
2076 ath5k_beacon_send(sc);
2077 } else
2078 ath5k_beacon_update_timers(sc, -1);
2079 } else {
2080 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
2081 }
2082
2083 ath5k_hw_set_imr(ah, sc->imask);
2084 mmiowb();
2085 spin_unlock_irqrestore(&sc->block, flags);
2086}
2087
2088static void ath5k_tasklet_beacon(unsigned long data)
2089{
2090 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2101
2102 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2103 sc->nexttbtt += sc->bintval;
2104 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2105 "SWBA nexttbtt: %x hw_tu: %x "
2106 "TSF: %llx\n",
2107 sc->nexttbtt,
2108 TSF_TO_TU(tsf),
2109 (unsigned long long) tsf);
2110 } else {
2111 spin_lock(&sc->block);
2112 ath5k_beacon_send(sc);
2113 spin_unlock(&sc->block);
2114 }
2115}
2116
2117
2118
2119
2120
2121
2122static void
2123ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2124{
2125 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2126 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2127
2128 ah->ah_cal_next_ani = jiffies +
2129 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2130 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2131
2132 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2133 ah->ah_cal_next_full = jiffies +
2134 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2135 tasklet_schedule(&ah->ah_sc->calib);
2136 }
2137
2138
2139
2140}
2141
2142irqreturn_t
2143ath5k_intr(int irq, void *dev_id)
2144{
2145 struct ath5k_softc *sc = dev_id;
2146 struct ath5k_hw *ah = sc->ah;
2147 enum ath5k_int status;
2148 unsigned int counter = 1000;
2149
2150 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2151 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2152 !ath5k_hw_is_intr_pending(ah))))
2153 return IRQ_NONE;
2154
2155 do {
2156 ath5k_hw_get_isr(ah, &status);
2157 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2158 status, sc->imask);
2159 if (unlikely(status & AR5K_INT_FATAL)) {
2160
2161
2162
2163
2164 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2165 "fatal int, resetting\n");
2166 ieee80211_queue_work(sc->hw, &sc->reset_work);
2167 } else if (unlikely(status & AR5K_INT_RXORN)) {
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177 sc->stats.rxorn_intr++;
2178 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2179 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2180 "rx overrun, resetting\n");
2181 ieee80211_queue_work(sc->hw, &sc->reset_work);
2182 }
2183 else
2184 tasklet_schedule(&sc->rxtq);
2185 } else {
2186 if (status & AR5K_INT_SWBA) {
2187 tasklet_hi_schedule(&sc->beacontq);
2188 }
2189 if (status & AR5K_INT_RXEOL) {
2190
2191
2192
2193
2194
2195 sc->stats.rxeol_intr++;
2196 }
2197 if (status & AR5K_INT_TXURN) {
2198
2199 ath5k_hw_update_tx_triglevel(ah, true);
2200 }
2201 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2202 tasklet_schedule(&sc->rxtq);
2203 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2204 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2205 tasklet_schedule(&sc->txtq);
2206 if (status & AR5K_INT_BMISS) {
2207
2208 }
2209 if (status & AR5K_INT_MIB) {
2210 sc->stats.mib_intr++;
2211 ath5k_hw_update_mib_counters(ah);
2212 ath5k_ani_mib_intr(ah);
2213 }
2214 if (status & AR5K_INT_GPIO)
2215 tasklet_schedule(&sc->rf_kill.toggleq);
2216
2217 }
2218
2219 if (ath5k_get_bus_type(ah) == ATH_AHB)
2220 break;
2221
2222 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2223
2224 if (unlikely(!counter))
2225 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2226
2227 ath5k_intr_calibration_poll(ah);
2228
2229 return IRQ_HANDLED;
2230}
2231
2232
2233
2234
2235
2236static void
2237ath5k_tasklet_calibrate(unsigned long data)
2238{
2239 struct ath5k_softc *sc = (void *)data;
2240 struct ath5k_hw *ah = sc->ah;
2241
2242
2243 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2244
2245 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2246 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2247 sc->curchan->hw_value);
2248
2249 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2250
2251
2252
2253
2254 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2255 ieee80211_queue_work(sc->hw, &sc->reset_work);
2256 }
2257 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2258 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2259 ieee80211_frequency_to_channel(
2260 sc->curchan->center_freq));
2261
2262
2263
2264
2265
2266 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2267 ah->ah_cal_next_nf = jiffies +
2268 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2269 ath5k_hw_update_noise_floor(ah);
2270 }
2271
2272 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2273}
2274
2275
2276static void
2277ath5k_tasklet_ani(unsigned long data)
2278{
2279 struct ath5k_softc *sc = (void *)data;
2280 struct ath5k_hw *ah = sc->ah;
2281
2282 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2283 ath5k_ani_calibration(ah);
2284 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2285}
2286
2287
2288static void
2289ath5k_tx_complete_poll_work(struct work_struct *work)
2290{
2291 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2292 tx_complete_work.work);
2293 struct ath5k_txq *txq;
2294 int i;
2295 bool needreset = false;
2296
2297 mutex_lock(&sc->lock);
2298
2299 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2300 if (sc->txqs[i].setup) {
2301 txq = &sc->txqs[i];
2302 spin_lock_bh(&txq->lock);
2303 if (txq->txq_len > 1) {
2304 if (txq->txq_poll_mark) {
2305 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2306 "TX queue stuck %d\n",
2307 txq->qnum);
2308 needreset = true;
2309 txq->txq_stuck++;
2310 spin_unlock_bh(&txq->lock);
2311 break;
2312 } else {
2313 txq->txq_poll_mark = true;
2314 }
2315 }
2316 spin_unlock_bh(&txq->lock);
2317 }
2318 }
2319
2320 if (needreset) {
2321 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2322 "TX queues stuck, resetting\n");
2323 ath5k_reset(sc, NULL, true);
2324 }
2325
2326 mutex_unlock(&sc->lock);
2327
2328 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2329 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2330}
2331
2332
2333
2334
2335
2336
2337int
2338ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2339{
2340 struct ieee80211_hw *hw = sc->hw;
2341 struct ath_common *common;
2342 int ret;
2343 int csz;
2344
2345
2346 SET_IEEE80211_DEV(hw, sc->dev);
2347 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2348 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2349 IEEE80211_HW_SIGNAL_DBM |
2350 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2351
2352 hw->wiphy->interface_modes =
2353 BIT(NL80211_IFTYPE_AP) |
2354 BIT(NL80211_IFTYPE_STATION) |
2355 BIT(NL80211_IFTYPE_ADHOC) |
2356 BIT(NL80211_IFTYPE_MESH_POINT);
2357
2358
2359 hw->wiphy->available_antennas_tx = 0x3;
2360 hw->wiphy->available_antennas_rx = 0x3;
2361
2362 hw->extra_tx_headroom = 2;
2363 hw->channel_change_time = 5000;
2364
2365
2366
2367
2368
2369 __set_bit(ATH_STAT_INVALID, sc->status);
2370
2371 sc->opmode = NL80211_IFTYPE_STATION;
2372 sc->bintval = 1000;
2373 mutex_init(&sc->lock);
2374 spin_lock_init(&sc->rxbuflock);
2375 spin_lock_init(&sc->txbuflock);
2376 spin_lock_init(&sc->block);
2377
2378
2379
2380 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2381 if (ret) {
2382 ATH5K_ERR(sc, "request_irq failed\n");
2383 goto err;
2384 }
2385
2386
2387 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2388 if (!sc->ah) {
2389 ret = -ENOMEM;
2390 ATH5K_ERR(sc, "out of memory\n");
2391 goto err_irq;
2392 }
2393
2394 sc->ah->ah_sc = sc;
2395 sc->ah->ah_iobase = sc->iobase;
2396 common = ath5k_hw_common(sc->ah);
2397 common->ops = &ath5k_common_ops;
2398 common->bus_ops = bus_ops;
2399 common->ah = sc->ah;
2400 common->hw = hw;
2401 common->priv = sc;
2402
2403
2404
2405
2406
2407 ath5k_read_cachesize(common, &csz);
2408 common->cachelsz = csz << 2;
2409
2410 spin_lock_init(&common->cc_lock);
2411
2412
2413 ret = ath5k_hw_init(sc);
2414 if (ret)
2415 goto err_free_ah;
2416
2417
2418 if (sc->ah->ah_version == AR5K_AR5212) {
2419 hw->max_rates = 4;
2420 hw->max_rate_tries = 11;
2421 }
2422
2423 hw->vif_data_size = sizeof(struct ath5k_vif);
2424
2425
2426 ret = ath5k_init(hw);
2427 if (ret)
2428 goto err_ah;
2429
2430 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2431 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2432 sc->ah->ah_mac_srev,
2433 sc->ah->ah_phy_revision);
2434
2435 if (!sc->ah->ah_single_chip) {
2436
2437 if (sc->ah->ah_radio_5ghz_revision &&
2438 !sc->ah->ah_radio_2ghz_revision) {
2439
2440 if (!test_bit(AR5K_MODE_11A,
2441 sc->ah->ah_capabilities.cap_mode)) {
2442 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2443 ath5k_chip_name(AR5K_VERSION_RAD,
2444 sc->ah->ah_radio_5ghz_revision),
2445 sc->ah->ah_radio_5ghz_revision);
2446
2447
2448 } else if (!test_bit(AR5K_MODE_11B,
2449 sc->ah->ah_capabilities.cap_mode)) {
2450 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2451 ath5k_chip_name(AR5K_VERSION_RAD,
2452 sc->ah->ah_radio_5ghz_revision),
2453 sc->ah->ah_radio_5ghz_revision);
2454
2455 } else {
2456 ATH5K_INFO(sc, "RF%s multiband radio found"
2457 " (0x%x)\n",
2458 ath5k_chip_name(AR5K_VERSION_RAD,
2459 sc->ah->ah_radio_5ghz_revision),
2460 sc->ah->ah_radio_5ghz_revision);
2461 }
2462 }
2463
2464
2465 else if (sc->ah->ah_radio_5ghz_revision &&
2466 sc->ah->ah_radio_2ghz_revision){
2467 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2468 ath5k_chip_name(AR5K_VERSION_RAD,
2469 sc->ah->ah_radio_5ghz_revision),
2470 sc->ah->ah_radio_5ghz_revision);
2471 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2472 ath5k_chip_name(AR5K_VERSION_RAD,
2473 sc->ah->ah_radio_2ghz_revision),
2474 sc->ah->ah_radio_2ghz_revision);
2475 }
2476 }
2477
2478 ath5k_debug_init_device(sc);
2479
2480
2481 __clear_bit(ATH_STAT_INVALID, sc->status);
2482
2483 return 0;
2484err_ah:
2485 ath5k_hw_deinit(sc->ah);
2486err_free_ah:
2487 kfree(sc->ah);
2488err_irq:
2489 free_irq(sc->irq, sc);
2490err:
2491 return ret;
2492}
2493
2494static int
2495ath5k_stop_locked(struct ath5k_softc *sc)
2496{
2497 struct ath5k_hw *ah = sc->ah;
2498
2499 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2500 test_bit(ATH_STAT_INVALID, sc->status));
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517 ieee80211_stop_queues(sc->hw);
2518
2519 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2520 ath5k_led_off(sc);
2521 ath5k_hw_set_imr(ah, 0);
2522 synchronize_irq(sc->irq);
2523 ath5k_rx_stop(sc);
2524 ath5k_hw_dma_stop(ah);
2525 ath5k_drain_tx_buffs(sc);
2526 ath5k_hw_phy_disable(ah);
2527 }
2528
2529 return 0;
2530}
2531
2532int
2533ath5k_init_hw(struct ath5k_softc *sc)
2534{
2535 struct ath5k_hw *ah = sc->ah;
2536 struct ath_common *common = ath5k_hw_common(ah);
2537 int ret, i;
2538
2539 mutex_lock(&sc->lock);
2540
2541 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2542
2543
2544
2545
2546
2547 ath5k_stop_locked(sc);
2548
2549
2550
2551
2552
2553
2554
2555
2556 sc->curchan = sc->hw->conf.channel;
2557 sc->curband = &sc->sbands[sc->curchan->band];
2558 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2559 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2560 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2561
2562 ret = ath5k_reset(sc, NULL, false);
2563 if (ret)
2564 goto done;
2565
2566 ath5k_rfkill_hw_start(ah);
2567
2568
2569
2570
2571
2572 for (i = 0; i < common->keymax; i++)
2573 ath_hw_keyreset(common, (u16) i);
2574
2575
2576
2577 ah->ah_ack_bitrate_high = true;
2578
2579 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2580 sc->bslot[i] = NULL;
2581
2582 ret = 0;
2583done:
2584 mmiowb();
2585 mutex_unlock(&sc->lock);
2586
2587 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2588 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2589
2590 return ret;
2591}
2592
2593static void stop_tasklets(struct ath5k_softc *sc)
2594{
2595 tasklet_kill(&sc->rxtq);
2596 tasklet_kill(&sc->txtq);
2597 tasklet_kill(&sc->calib);
2598 tasklet_kill(&sc->beacontq);
2599 tasklet_kill(&sc->ani_tasklet);
2600}
2601
2602
2603
2604
2605
2606
2607
2608int
2609ath5k_stop_hw(struct ath5k_softc *sc)
2610{
2611 int ret;
2612
2613 mutex_lock(&sc->lock);
2614 ret = ath5k_stop_locked(sc);
2615 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636 ret = ath5k_hw_on_hold(sc->ah);
2637
2638 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2639 "putting device to sleep\n");
2640 }
2641
2642 mmiowb();
2643 mutex_unlock(&sc->lock);
2644
2645 stop_tasklets(sc);
2646
2647 cancel_delayed_work_sync(&sc->tx_complete_work);
2648
2649 ath5k_rfkill_hw_stop(sc->ah);
2650
2651 return ret;
2652}
2653
2654
2655
2656
2657
2658
2659
2660static int
2661ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2662 bool skip_pcu)
2663{
2664 struct ath5k_hw *ah = sc->ah;
2665 struct ath_common *common = ath5k_hw_common(ah);
2666 int ret, ani_mode;
2667
2668 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2669
2670 ath5k_hw_set_imr(ah, 0);
2671 synchronize_irq(sc->irq);
2672 stop_tasklets(sc);
2673
2674
2675
2676
2677 ani_mode = ah->ah_sc->ani_state.ani_mode;
2678 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2679
2680
2681
2682
2683 ath5k_drain_tx_buffs(sc);
2684 if (chan) {
2685 sc->curchan = chan;
2686 sc->curband = &sc->sbands[chan->band];
2687 }
2688 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL,
2689 skip_pcu);
2690 if (ret) {
2691 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2692 goto err;
2693 }
2694
2695 ret = ath5k_rx_start(sc);
2696 if (ret) {
2697 ATH5K_ERR(sc, "can't start recv logic\n");
2698 goto err;
2699 }
2700
2701 ath5k_ani_init(ah, ani_mode);
2702
2703 ah->ah_cal_next_full = jiffies;
2704 ah->ah_cal_next_ani = jiffies;
2705 ah->ah_cal_next_nf = jiffies;
2706 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2707
2708
2709 memset(&sc->survey, 0, sizeof(sc->survey));
2710 spin_lock_bh(&common->cc_lock);
2711 ath_hw_cycle_counters_update(common);
2712 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2713 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
2714 spin_unlock_bh(&common->cc_lock);
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727 ath5k_beacon_config(sc);
2728
2729
2730 ieee80211_wake_queues(sc->hw);
2731
2732 return 0;
2733err:
2734 return ret;
2735}
2736
2737static void ath5k_reset_work(struct work_struct *work)
2738{
2739 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2740 reset_work);
2741
2742 mutex_lock(&sc->lock);
2743 ath5k_reset(sc, NULL, true);
2744 mutex_unlock(&sc->lock);
2745}
2746
2747static int
2748ath5k_init(struct ieee80211_hw *hw)
2749{
2750
2751 struct ath5k_softc *sc = hw->priv;
2752 struct ath5k_hw *ah = sc->ah;
2753 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2754 struct ath5k_txq *txq;
2755 u8 mac[ETH_ALEN] = {};
2756 int ret;
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
2767
2768 if (ret < 0)
2769 goto err;
2770 if (ret > 0)
2771 __set_bit(ATH_STAT_MRRETRY, sc->status);
2772
2773
2774
2775
2776
2777
2778
2779 ret = ath5k_setup_bands(hw);
2780 if (ret) {
2781 ATH5K_ERR(sc, "can't get channels\n");
2782 goto err;
2783 }
2784
2785
2786 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2787 ath5k_setcurmode(sc, AR5K_MODE_11A);
2788 else
2789 ath5k_setcurmode(sc, AR5K_MODE_11B);
2790
2791
2792
2793
2794 ret = ath5k_desc_alloc(sc);
2795 if (ret) {
2796 ATH5K_ERR(sc, "can't allocate descriptors\n");
2797 goto err;
2798 }
2799
2800
2801
2802
2803
2804
2805
2806 ret = ath5k_beaconq_setup(ah);
2807 if (ret < 0) {
2808 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2809 goto err_desc;
2810 }
2811 sc->bhalq = ret;
2812 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2813 if (IS_ERR(sc->cabq)) {
2814 ATH5K_ERR(sc, "can't setup cab queue\n");
2815 ret = PTR_ERR(sc->cabq);
2816 goto err_bhal;
2817 }
2818
2819
2820
2821 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2822
2823
2824 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2825 if (IS_ERR(txq)) {
2826 ATH5K_ERR(sc, "can't setup xmit queue\n");
2827 ret = PTR_ERR(txq);
2828 goto err_queues;
2829 }
2830 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2831 if (IS_ERR(txq)) {
2832 ATH5K_ERR(sc, "can't setup xmit queue\n");
2833 ret = PTR_ERR(txq);
2834 goto err_queues;
2835 }
2836 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2837 if (IS_ERR(txq)) {
2838 ATH5K_ERR(sc, "can't setup xmit queue\n");
2839 ret = PTR_ERR(txq);
2840 goto err_queues;
2841 }
2842 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2843 if (IS_ERR(txq)) {
2844 ATH5K_ERR(sc, "can't setup xmit queue\n");
2845 ret = PTR_ERR(txq);
2846 goto err_queues;
2847 }
2848 hw->queues = 4;
2849 } else {
2850
2851 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2852 if (IS_ERR(txq)) {
2853 ATH5K_ERR(sc, "can't setup xmit queue\n");
2854 ret = PTR_ERR(txq);
2855 goto err_queues;
2856 }
2857 hw->queues = 1;
2858 }
2859
2860 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2861 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2862 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2863 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2864 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
2865
2866 INIT_WORK(&sc->reset_work, ath5k_reset_work);
2867 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
2868
2869 ret = ath5k_eeprom_read_mac(ah, mac);
2870 if (ret) {
2871 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
2872 goto err_queues;
2873 }
2874
2875 SET_IEEE80211_PERM_ADDR(hw, mac);
2876 memcpy(&sc->lladdr, mac, ETH_ALEN);
2877
2878 ath5k_update_bssid_mask_and_opmode(sc, NULL);
2879
2880 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2881 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2882 if (ret) {
2883 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2884 goto err_queues;
2885 }
2886
2887 ret = ieee80211_register_hw(hw);
2888 if (ret) {
2889 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2890 goto err_queues;
2891 }
2892
2893 if (!ath_is_world_regd(regulatory))
2894 regulatory_hint(hw->wiphy, regulatory->alpha2);
2895
2896 ath5k_init_leds(sc);
2897
2898 ath5k_sysfs_register(sc);
2899
2900 return 0;
2901err_queues:
2902 ath5k_txq_release(sc);
2903err_bhal:
2904 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2905err_desc:
2906 ath5k_desc_free(sc);
2907err:
2908 return ret;
2909}
2910
2911void
2912ath5k_deinit_softc(struct ath5k_softc *sc)
2913{
2914 struct ieee80211_hw *hw = sc->hw;
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929 ath5k_debug_finish_device(sc);
2930 ieee80211_unregister_hw(hw);
2931 ath5k_desc_free(sc);
2932 ath5k_txq_release(sc);
2933 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2934 ath5k_unregister_leds(sc);
2935
2936 ath5k_sysfs_unregister(sc);
2937
2938
2939
2940
2941
2942 ath5k_hw_deinit(sc->ah);
2943 free_irq(sc->irq, sc);
2944}
2945
2946bool
2947ath_any_vif_assoc(struct ath5k_softc *sc)
2948{
2949 struct ath_vif_iter_data iter_data;
2950 iter_data.hw_macaddr = NULL;
2951 iter_data.any_assoc = false;
2952 iter_data.need_set_hw_addr = false;
2953 iter_data.found_active = true;
2954
2955 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
2956 &iter_data);
2957 return iter_data.any_assoc;
2958}
2959
2960void
2961set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2962{
2963 struct ath5k_softc *sc = hw->priv;
2964 struct ath5k_hw *ah = sc->ah;
2965 u32 rfilt;
2966 rfilt = ath5k_hw_get_rx_filter(ah);
2967 if (enable)
2968 rfilt |= AR5K_RX_FILTER_BEACON;
2969 else
2970 rfilt &= ~AR5K_RX_FILTER_BEACON;
2971 ath5k_hw_set_rx_filter(ah, rfilt);
2972 sc->filter_flags = rfilt;
2973}
2974