LXR linux/drivers/net/wireless/ath/ath9k/phy.h

   1/*
   2 * Copyright (c) 2008-2009 Atheros Communications Inc.
   3 *
   4 * Permission to use, copy, modify, and/or distribute this software for any
   5 * purpose with or without fee is hereby granted, provided that the above
   6 * copyright notice and this permission notice appear in all copies.
   7 *
   8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15 */
  16
  17#ifndef PHY_H
  18#define PHY_H
  19
  20#define CHANSEL_DIV             15
  21#define CHANSEL_2G(_freq)       (((_freq) * 0x10000) / CHANSEL_DIV)
  22#define CHANSEL_2G_9485(_freq)  ((((_freq) * 0x10000) - 215) / CHANSEL_DIV)
  23#define CHANSEL_5G(_freq)       (((_freq) * 0x8000) / CHANSEL_DIV)
  24
  25#define AR_PHY_BASE     0x9800
  26#define AR_PHY(_n)      (AR_PHY_BASE + ((_n)<<2))
  27
  28#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX   0x0007E000
  29#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
  30#define AR_PHY_TX_GAIN_CLC       0x0000001E
  31#define AR_PHY_TX_GAIN_CLC_S     1
  32#define AR_PHY_TX_GAIN           0x0007F000
  33#define AR_PHY_TX_GAIN_S         12
  34
  35#define AR_PHY_CLC_TBL1      0xa35c
  36#define AR_PHY_CLC_I0        0x07ff0000
  37#define AR_PHY_CLC_I0_S      16
  38#define AR_PHY_CLC_Q0        0x0000ffd0
  39#define AR_PHY_CLC_Q0_S      5
  40
  41#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do {               \
  42                int r;                                                  \
  43                for (r = 0; r < ((iniarray)->ia_rows); r++) {           \
  44                        REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
  45                        DO_DELAY(regWr);                                \
  46                }                                                       \
  47        } while (0)
  48
  49#define ANTSWAP_AB 0x0001
  50#define REDUCE_CHAIN_0 0x00000050
  51#define REDUCE_CHAIN_1 0x00000051
  52#define AR_PHY_CHIP_ID 0x9818
  53
  54#define RF_BANK_SETUP(_bank, _iniarray, _col) do {                      \
  55                int i;                                                  \
  56                for (i = 0; i < (_iniarray)->ia_rows; i++)              \
  57                        (_bank)[i] = INI_RA((_iniarray), i, _col);;     \
  58        } while (0)
  59
  60#define AR_PHY_TIMING11_SPUR_FREQ_SD            0x3FF00000
  61#define AR_PHY_TIMING11_SPUR_FREQ_SD_S          20
  62
  63#endif
  64