1#ifndef B43_H_
2#define B43_H_
3
4#include <linux/kernel.h>
5#include <linux/spinlock.h>
6#include <linux/interrupt.h>
7#include <linux/hw_random.h>
8#include <linux/ssb/ssb.h>
9#include <net/mac80211.h>
10
11#include "debugfs.h"
12#include "leds.h"
13#include "rfkill.h"
14#include "lo.h"
15#include "phy_common.h"
16
17
18
19
20#define B43_SUPPORTED_FIRMWARE_ID "FW13"
21
22
23#ifdef CONFIG_B43_DEBUG
24# define B43_DEBUG 1
25#else
26# define B43_DEBUG 0
27#endif
28
29
30#define B43_MMIO_DMA0_REASON 0x20
31#define B43_MMIO_DMA0_IRQ_MASK 0x24
32#define B43_MMIO_DMA1_REASON 0x28
33#define B43_MMIO_DMA1_IRQ_MASK 0x2C
34#define B43_MMIO_DMA2_REASON 0x30
35#define B43_MMIO_DMA2_IRQ_MASK 0x34
36#define B43_MMIO_DMA3_REASON 0x38
37#define B43_MMIO_DMA3_IRQ_MASK 0x3C
38#define B43_MMIO_DMA4_REASON 0x40
39#define B43_MMIO_DMA4_IRQ_MASK 0x44
40#define B43_MMIO_DMA5_REASON 0x48
41#define B43_MMIO_DMA5_IRQ_MASK 0x4C
42#define B43_MMIO_MACCTL 0x120
43#define B43_MMIO_MACCMD 0x124
44#define B43_MMIO_GEN_IRQ_REASON 0x128
45#define B43_MMIO_GEN_IRQ_MASK 0x12C
46#define B43_MMIO_RAM_CONTROL 0x130
47#define B43_MMIO_RAM_DATA 0x134
48#define B43_MMIO_PS_STATUS 0x140
49#define B43_MMIO_RADIO_HWENABLED_HI 0x158
50#define B43_MMIO_SHM_CONTROL 0x160
51#define B43_MMIO_SHM_DATA 0x164
52#define B43_MMIO_SHM_DATA_UNALIGNED 0x166
53#define B43_MMIO_XMITSTAT_0 0x170
54#define B43_MMIO_XMITSTAT_1 0x174
55#define B43_MMIO_REV3PLUS_TSF_LOW 0x180
56#define B43_MMIO_REV3PLUS_TSF_HIGH 0x184
57#define B43_MMIO_TSF_CFP_REP 0x188
58#define B43_MMIO_TSF_CFP_START 0x18C
59#define B43_MMIO_TSF_CFP_MAXDUR 0x190
60
61
62#define B43_MMIO_DMA32_BASE0 0x200
63#define B43_MMIO_DMA32_BASE1 0x220
64#define B43_MMIO_DMA32_BASE2 0x240
65#define B43_MMIO_DMA32_BASE3 0x260
66#define B43_MMIO_DMA32_BASE4 0x280
67#define B43_MMIO_DMA32_BASE5 0x2A0
68
69#define B43_MMIO_DMA64_BASE0 0x200
70#define B43_MMIO_DMA64_BASE1 0x240
71#define B43_MMIO_DMA64_BASE2 0x280
72#define B43_MMIO_DMA64_BASE3 0x2C0
73#define B43_MMIO_DMA64_BASE4 0x300
74#define B43_MMIO_DMA64_BASE5 0x340
75
76
77#define B43_MMIO_PIO_BASE0 0x300
78#define B43_MMIO_PIO_BASE1 0x310
79#define B43_MMIO_PIO_BASE2 0x320
80#define B43_MMIO_PIO_BASE3 0x330
81#define B43_MMIO_PIO_BASE4 0x340
82#define B43_MMIO_PIO_BASE5 0x350
83#define B43_MMIO_PIO_BASE6 0x360
84#define B43_MMIO_PIO_BASE7 0x370
85
86#define B43_MMIO_PIO11_BASE0 0x200
87#define B43_MMIO_PIO11_BASE1 0x240
88#define B43_MMIO_PIO11_BASE2 0x280
89#define B43_MMIO_PIO11_BASE3 0x2C0
90#define B43_MMIO_PIO11_BASE4 0x300
91#define B43_MMIO_PIO11_BASE5 0x340
92
93#define B43_MMIO_PHY_VER 0x3E0
94#define B43_MMIO_PHY_RADIO 0x3E2
95#define B43_MMIO_PHY0 0x3E6
96#define B43_MMIO_ANTENNA 0x3E8
97#define B43_MMIO_CHANNEL 0x3F0
98#define B43_MMIO_CHANNEL_EXT 0x3F4
99#define B43_MMIO_RADIO_CONTROL 0x3F6
100#define B43_MMIO_RADIO_DATA_HIGH 0x3F8
101#define B43_MMIO_RADIO_DATA_LOW 0x3FA
102#define B43_MMIO_PHY_CONTROL 0x3FC
103#define B43_MMIO_PHY_DATA 0x3FE
104#define B43_MMIO_MACFILTER_CONTROL 0x420
105#define B43_MMIO_MACFILTER_DATA 0x422
106#define B43_MMIO_RCMTA_COUNT 0x43C
107#define B43_MMIO_PSM_PHY_HDR 0x492
108#define B43_MMIO_RADIO_HWENABLED_LO 0x49A
109#define B43_MMIO_GPIO_CONTROL 0x49C
110#define B43_MMIO_GPIO_MASK 0x49E
111#define B43_MMIO_TSF_CFP_START_LOW 0x604
112#define B43_MMIO_TSF_CFP_START_HIGH 0x606
113#define B43_MMIO_TSF_CFP_PRETBTT 0x612
114#define B43_MMIO_TSF_0 0x632
115#define B43_MMIO_TSF_1 0x634
116#define B43_MMIO_TSF_2 0x636
117#define B43_MMIO_TSF_3 0x638
118#define B43_MMIO_RNG 0x65A
119#define B43_MMIO_IFSSLOT 0x684
120#define B43_MMIO_IFSCTL 0x688
121#define B43_MMIO_IFSCTL_USE_EDCF 0x0004
122#define B43_MMIO_POWERUP_DELAY 0x6A8
123#define B43_MMIO_BTCOEX_CTL 0x6B4
124#define B43_MMIO_BTCOEX_STAT 0x6B6
125#define B43_MMIO_BTCOEX_TXCTL 0x6B8
126
127
128#define B43_BFL_BTCOEXIST 0x0001
129#define B43_BFL_PACTRL 0x0002
130#define B43_BFL_AIRLINEMODE 0x0004
131#define B43_BFL_RSSI 0x0008
132#define B43_BFL_ENETSPI 0x0010
133#define B43_BFL_XTAL_NOSLOW 0x0020
134#define B43_BFL_CCKHIPWR 0x0040
135#define B43_BFL_ENETADM 0x0080
136#define B43_BFL_ENETVLAN 0x0100
137#define B43_BFL_AFTERBURNER 0x0200
138#define B43_BFL_NOPCI 0x0400
139#define B43_BFL_FEM 0x0800
140#define B43_BFL_EXTLNA 0x1000
141#define B43_BFL_HGPA 0x2000
142#define B43_BFL_BTCMOD 0x4000
143#define B43_BFL_ALTIQ 0x8000
144
145
146#define B43_BFH_NOPA 0x0001
147#define B43_BFH_RSSIINV 0x0002
148#define B43_BFH_PAREF 0x0004
149#define B43_BFH_3TSWITCH 0x0008
150
151#define B43_BFH_PHASESHIFT 0x0010
152#define B43_BFH_BUCKBOOST 0x0020
153#define B43_BFH_FEM_BT 0x0040
154
155
156
157#define B43_BFL2_RXBB_INT_REG_DIS 0x0001
158#define B43_BFL2_APLL_WAR 0x0002
159#define B43_BFL2_TXPWRCTRL_EN 0x0004
160#define B43_BFL2_2X4_DIV 0x0008
161#define B43_BFL2_5G_PWRGAIN 0x0010
162#define B43_BFL2_PCIEWAR_OVR 0x0020
163#define B43_BFL2_CAESERS_BRD 0x0040
164#define B43_BFL2_BTC3WIRE 0x0080
165#define B43_BFL2_SKWRKFEM_BRD 0x0100
166#define B43_BFL2_SPUR_WAR 0x0200
167#define B43_BFL2_GPLL_WAR 0x0400
168
169
170#define B43_GPIO_CONTROL 0x6c
171
172
173enum {
174 B43_SHM_UCODE,
175 B43_SHM_SHARED,
176 B43_SHM_SCRATCH,
177 B43_SHM_HW,
178 B43_SHM_RCMTA,
179};
180
181#define B43_SHM_AUTOINC_R 0x0200
182#define B43_SHM_AUTOINC_W 0x0100
183#define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \
184 B43_SHM_AUTOINC_W)
185
186
187#define B43_SHM_SH_WLCOREREV 0x0016
188#define B43_SHM_SH_PCTLWDPOS 0x0008
189#define B43_SHM_SH_RXPADOFF 0x0034
190#define B43_SHM_SH_FWCAPA 0x0042
191#define B43_SHM_SH_PHYVER 0x0050
192#define B43_SHM_SH_PHYTYPE 0x0052
193#define B43_SHM_SH_ANTSWAP 0x005C
194#define B43_SHM_SH_HOSTFLO 0x005E
195#define B43_SHM_SH_HOSTFMI 0x0060
196#define B43_SHM_SH_HOSTFHI 0x0062
197#define B43_SHM_SH_RFATT 0x0064
198#define B43_SHM_SH_RADAR 0x0066
199#define B43_SHM_SH_PHYTXNOI 0x006E
200#define B43_SHM_SH_RFRXSP1 0x0072
201#define B43_SHM_SH_CHAN 0x00A0
202#define B43_SHM_SH_CHAN_5GHZ 0x0100
203#define B43_SHM_SH_CHAN_40MHZ 0x0200
204#define B43_SHM_SH_BCMCFIFOID 0x0108
205
206#define B43_SHM_SH_TSSI_CCK 0x0058
207#define B43_SHM_SH_TSSI_OFDM_A 0x0068
208#define B43_SHM_SH_TSSI_OFDM_G 0x0070
209#define B43_TSSI_MAX 0x7F
210
211#define B43_SHM_SH_SIZE01 0x0098
212#define B43_SHM_SH_SIZE23 0x009A
213#define B43_SHM_SH_SIZE45 0x009C
214#define B43_SHM_SH_SIZE67 0x009E
215
216#define B43_SHM_SH_JSSI0 0x0088
217#define B43_SHM_SH_JSSI1 0x008A
218#define B43_SHM_SH_JSSIAUX 0x008C
219
220#define B43_SHM_SH_DEFAULTIV 0x003C
221#define B43_SHM_SH_NRRXTRANS 0x003E
222#define B43_SHM_SH_KTP 0x0056
223#define B43_SHM_SH_TKIPTSCTTAK 0x0318
224#define B43_SHM_SH_KEYIDXBLOCK 0x05D4
225#define B43_SHM_SH_PSM 0x05F4
226
227#define B43_SHM_SH_EDCFSTAT 0x000E
228#define B43_SHM_SH_TXFCUR 0x0030
229#define B43_SHM_SH_EDCFQ 0x0240
230
231#define B43_SHM_SH_SLOTT 0x0010
232#define B43_SHM_SH_DTIMPER 0x0012
233#define B43_SHM_SH_NOSLPZNATDTIM 0x004C
234
235#define B43_SHM_SH_BTL0 0x0018
236#define B43_SHM_SH_BTL1 0x001A
237#define B43_SHM_SH_BTSFOFF 0x001C
238#define B43_SHM_SH_TIMBPOS 0x001E
239#define B43_SHM_SH_DTIMP 0x0012
240#define B43_SHM_SH_MCASTCOOKIE 0x00A8
241#define B43_SHM_SH_SFFBLIM 0x0044
242#define B43_SHM_SH_LFFBLIM 0x0046
243#define B43_SHM_SH_BEACPHYCTL 0x0054
244#define B43_SHM_SH_EXTNPHYCTL 0x00B0
245
246#define B43_SHM_SH_ACKCTSPHYCTL 0x0022
247
248#define B43_SHM_SH_PRSSID 0x0160
249#define B43_SHM_SH_PRSSIDLEN 0x0048
250#define B43_SHM_SH_PRTLEN 0x004A
251#define B43_SHM_SH_PRMAXTIME 0x0074
252#define B43_SHM_SH_PRPHYCTL 0x0188
253
254#define B43_SHM_SH_OFDMDIRECT 0x01C0
255#define B43_SHM_SH_OFDMBASIC 0x01E0
256#define B43_SHM_SH_CCKDIRECT 0x0200
257#define B43_SHM_SH_CCKBASIC 0x0220
258
259#define B43_SHM_SH_UCODEREV 0x0000
260#define B43_SHM_SH_UCODEPATCH 0x0002
261#define B43_SHM_SH_UCODEDATE 0x0004
262#define B43_SHM_SH_UCODETIME 0x0006
263#define B43_SHM_SH_UCODESTAT 0x0040
264#define B43_SHM_SH_UCODESTAT_INVALID 0
265#define B43_SHM_SH_UCODESTAT_INIT 1
266#define B43_SHM_SH_UCODESTAT_ACTIVE 2
267#define B43_SHM_SH_UCODESTAT_SUSP 3
268#define B43_SHM_SH_UCODESTAT_SLEEP 4
269#define B43_SHM_SH_MAXBFRAMES 0x0080
270#define B43_SHM_SH_SPUWKUP 0x0094
271#define B43_SHM_SH_PRETBTT 0x0096
272
273#define B43_SHM_SH_NPHY_TXIQW0 0x0700
274#define B43_SHM_SH_NPHY_TXIQW1 0x0702
275#define B43_SHM_SH_NPHY_TXIQW2 0x0704
276#define B43_SHM_SH_NPHY_TXIQW3 0x0706
277
278#define B43_SHM_SH_NPHY_TXPWR_INDX0 0x0708
279#define B43_SHM_SH_NPHY_TXPWR_INDX1 0x070E
280
281
282#define B43_SHM_SC_MINCONT 0x0003
283#define B43_SHM_SC_MAXCONT 0x0004
284#define B43_SHM_SC_CURCONT 0x0005
285#define B43_SHM_SC_SRLIMIT 0x0006
286#define B43_SHM_SC_LRLIMIT 0x0007
287#define B43_SHM_SC_DTIMC 0x0008
288#define B43_SHM_SC_BTL0LEN 0x0015
289#define B43_SHM_SC_BTL1LEN 0x0016
290#define B43_SHM_SC_SCFB 0x0017
291#define B43_SHM_SC_LCFB 0x0018
292
293
294#define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
295#define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
296
297
298#define B43_HF_ANTDIVHELP 0x000000000001ULL
299#define B43_HF_SYMW 0x000000000002ULL
300#define B43_HF_RXPULLW 0x000000000004ULL
301#define B43_HF_CCKBOOST 0x000000000008ULL
302#define B43_HF_BTCOEX 0x000000000010ULL
303#define B43_HF_GDCW 0x000000000020ULL
304#define B43_HF_OFDMPABOOST 0x000000000040ULL
305#define B43_HF_ACPR 0x000000000080ULL
306#define B43_HF_EDCF 0x000000000100ULL
307#define B43_HF_TSSIRPSMW 0x000000000200ULL
308#define B43_HF_20IN40IQW 0x000000000200ULL
309#define B43_HF_DSCRQ 0x000000000400ULL
310#define B43_HF_ACIW 0x000000000800ULL
311#define B43_HF_2060W 0x000000001000ULL
312#define B43_HF_RADARW 0x000000002000ULL
313#define B43_HF_USEDEFKEYS 0x000000004000ULL
314#define B43_HF_AFTERBURNER 0x000000008000ULL
315#define B43_HF_BT4PRIOCOEX 0x000000010000ULL
316#define B43_HF_FWKUP 0x000000020000ULL
317#define B43_HF_VCORECALC 0x000000040000ULL
318#define B43_HF_PCISCW 0x000000080000ULL
319#define B43_HF_4318TSSI 0x000000200000ULL
320#define B43_HF_FBCMCFIFO 0x000000400000ULL
321#define B43_HF_HWPCTL 0x000000800000ULL
322#define B43_HF_BTCOEXALT 0x000001000000ULL
323#define B43_HF_TXBTCHECK 0x000002000000ULL
324#define B43_HF_SKCFPUP 0x000004000000ULL
325#define B43_HF_N40W 0x000008000000ULL
326#define B43_HF_ANTSEL 0x000020000000ULL
327#define B43_HF_BT3COEXT 0x000020000000ULL
328#define B43_HF_BTCANT 0x000040000000ULL
329#define B43_HF_ANTSELEN 0x000100000000ULL
330#define B43_HF_ANTSELMODE 0x000200000000ULL
331#define B43_HF_MLADVW 0x001000000000ULL
332#define B43_HF_PR45960W 0x080000000000ULL
333
334
335#define B43_FWCAPA_HWCRYPTO 0x0001
336#define B43_FWCAPA_QOS 0x0002
337
338
339#define B43_MACFILTER_SELF 0x0000
340#define B43_MACFILTER_BSSID 0x0003
341
342
343#define B43_PCTL_IN 0xB0
344#define B43_PCTL_OUT 0xB4
345#define B43_PCTL_OUTENABLE 0xB8
346#define B43_PCTL_XTAL_POWERUP 0x40
347#define B43_PCTL_PLL_POWERDOWN 0x80
348
349
350#define B43_PCTL_CLK_FAST 0x00
351#define B43_PCTL_CLK_SLOW 0x01
352#define B43_PCTL_CLK_DYNAMIC 0x02
353
354#define B43_PCTL_FORCE_SLOW 0x0800
355#define B43_PCTL_FORCE_PLL 0x1000
356#define B43_PCTL_DYN_XTAL 0x2000
357
358
359#define B43_PHYTYPE_A 0x00
360#define B43_PHYTYPE_B 0x01
361#define B43_PHYTYPE_G 0x02
362#define B43_PHYTYPE_N 0x04
363#define B43_PHYTYPE_LP 0x05
364
365
366#define B43_PHY_ILT_A_CTRL 0x0072
367#define B43_PHY_ILT_A_DATA1 0x0073
368#define B43_PHY_ILT_A_DATA2 0x0074
369#define B43_PHY_G_LO_CONTROL 0x0810
370#define B43_PHY_ILT_G_CTRL 0x0472
371#define B43_PHY_ILT_G_DATA1 0x0473
372#define B43_PHY_ILT_G_DATA2 0x0474
373#define B43_PHY_A_PCTL 0x007B
374#define B43_PHY_G_PCTL 0x0029
375#define B43_PHY_A_CRS 0x0029
376#define B43_PHY_RADIO_BITFIELD 0x0401
377#define B43_PHY_G_CRS 0x0429
378#define B43_PHY_NRSSILT_CTRL 0x0803
379#define B43_PHY_NRSSILT_DATA 0x0804
380
381
382#define B43_RADIOCTL_ID 0x01
383
384
385#define B43_MACCTL_ENABLED 0x00000001
386#define B43_MACCTL_PSM_RUN 0x00000002
387#define B43_MACCTL_PSM_JMP0 0x00000004
388#define B43_MACCTL_SHM_ENABLED 0x00000100
389#define B43_MACCTL_SHM_UPPER 0x00000200
390#define B43_MACCTL_IHR_ENABLED 0x00000400
391#define B43_MACCTL_PSM_DBG 0x00002000
392#define B43_MACCTL_GPOUTSMSK 0x0000C000
393#define B43_MACCTL_BE 0x00010000
394#define B43_MACCTL_INFRA 0x00020000
395#define B43_MACCTL_AP 0x00040000
396#define B43_MACCTL_RADIOLOCK 0x00080000
397#define B43_MACCTL_BEACPROMISC 0x00100000
398#define B43_MACCTL_KEEP_BADPLCP 0x00200000
399#define B43_MACCTL_KEEP_CTL 0x00400000
400#define B43_MACCTL_KEEP_BAD 0x00800000
401#define B43_MACCTL_PROMISC 0x01000000
402#define B43_MACCTL_HWPS 0x02000000
403#define B43_MACCTL_AWAKE 0x04000000
404#define B43_MACCTL_CLOSEDNET 0x08000000
405#define B43_MACCTL_TBTTHOLD 0x10000000
406#define B43_MACCTL_DISCTXSTAT 0x20000000
407#define B43_MACCTL_DISCPMQ 0x40000000
408#define B43_MACCTL_GMODE 0x80000000
409
410
411#define B43_MACCMD_BEACON0_VALID 0x00000001
412#define B43_MACCMD_BEACON1_VALID 0x00000002
413#define B43_MACCMD_DFQ_VALID 0x00000004
414#define B43_MACCMD_CCA 0x00000008
415#define B43_MACCMD_BGNOISE 0x00000010
416
417
418#define B43_TMSLOW_GMODE 0x20000000
419#define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000
420#define B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000
421#define B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000
422#define B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000
423#define B43_TMSLOW_PLLREFSEL 0x00200000
424#define B43_TMSLOW_MACPHYCLKEN 0x00100000
425#define B43_TMSLOW_PHYRESET 0x00080000
426#define B43_TMSLOW_PHYCLKEN 0x00040000
427
428
429#define B43_TMSHIGH_DUALBAND_PHY 0x00080000
430#define B43_TMSHIGH_FCLOCK 0x00040000
431#define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000
432#define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000
433
434
435#define B43_IRQ_MAC_SUSPENDED 0x00000001
436#define B43_IRQ_BEACON 0x00000002
437#define B43_IRQ_TBTT_INDI 0x00000004
438#define B43_IRQ_BEACON_TX_OK 0x00000008
439#define B43_IRQ_BEACON_CANCEL 0x00000010
440#define B43_IRQ_ATIM_END 0x00000020
441#define B43_IRQ_PMQ 0x00000040
442#define B43_IRQ_PIO_WORKAROUND 0x00000100
443#define B43_IRQ_MAC_TXERR 0x00000200
444#define B43_IRQ_PHY_TXERR 0x00000800
445#define B43_IRQ_PMEVENT 0x00001000
446#define B43_IRQ_TIMER0 0x00002000
447#define B43_IRQ_TIMER1 0x00004000
448#define B43_IRQ_DMA 0x00008000
449#define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000
450#define B43_IRQ_CCA_MEASURE_OK 0x00020000
451#define B43_IRQ_NOISESAMPLE_OK 0x00040000
452#define B43_IRQ_UCODE_DEBUG 0x08000000
453#define B43_IRQ_RFKILL 0x10000000
454#define B43_IRQ_TX_OK 0x20000000
455#define B43_IRQ_PHY_G_CHANGED 0x40000000
456#define B43_IRQ_TIMEOUT 0x80000000
457
458#define B43_IRQ_ALL 0xFFFFFFFF
459#define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \
460 B43_IRQ_ATIM_END | \
461 B43_IRQ_PMQ | \
462 B43_IRQ_MAC_TXERR | \
463 B43_IRQ_PHY_TXERR | \
464 B43_IRQ_DMA | \
465 B43_IRQ_TXFIFO_FLUSH_OK | \
466 B43_IRQ_NOISESAMPLE_OK | \
467 B43_IRQ_UCODE_DEBUG | \
468 B43_IRQ_RFKILL | \
469 B43_IRQ_TX_OK)
470
471
472#define B43_DEBUGIRQ_REASON_REG 63
473
474#define B43_DEBUGIRQ_PANIC 0
475#define B43_DEBUGIRQ_DUMP_SHM 1
476#define B43_DEBUGIRQ_DUMP_REGS 2
477#define B43_DEBUGIRQ_MARKER 3
478#define B43_DEBUGIRQ_ACK 0xFFFF
479
480
481#define B43_MARKER_ID_REG 2
482#define B43_MARKER_LINE_REG 3
483
484
485#define B43_FWPANIC_REASON_REG 3
486
487#define B43_FWPANIC_DIE 0
488#define B43_FWPANIC_RESTART 1
489
490
491#define B43_WATCHDOG_REG 1
492
493
494
495
496#define B43_CCK_RATE_1MB 0x02
497#define B43_CCK_RATE_2MB 0x04
498#define B43_CCK_RATE_5MB 0x0B
499#define B43_CCK_RATE_11MB 0x16
500#define B43_OFDM_RATE_6MB 0x0C
501#define B43_OFDM_RATE_9MB 0x12
502#define B43_OFDM_RATE_12MB 0x18
503#define B43_OFDM_RATE_18MB 0x24
504#define B43_OFDM_RATE_24MB 0x30
505#define B43_OFDM_RATE_36MB 0x48
506#define B43_OFDM_RATE_48MB 0x60
507#define B43_OFDM_RATE_54MB 0x6C
508
509#define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
510
511#define B43_DEFAULT_SHORT_RETRY_LIMIT 7
512#define B43_DEFAULT_LONG_RETRY_LIMIT 4
513
514#define B43_PHY_TX_BADNESS_LIMIT 1000
515
516
517#define B43_SEC_KEYSIZE 16
518
519#define B43_NR_GROUP_KEYS 4
520
521#define B43_NR_PAIRWISE_KEYS 50
522
523enum {
524 B43_SEC_ALGO_NONE = 0,
525 B43_SEC_ALGO_WEP40,
526 B43_SEC_ALGO_TKIP,
527 B43_SEC_ALGO_AES,
528 B43_SEC_ALGO_WEP104,
529 B43_SEC_ALGO_AES_LEGACY,
530};
531
532struct b43_dmaring;
533
534
535#define B43_FW_TYPE_UCODE 'u'
536#define B43_FW_TYPE_PCM 'p'
537#define B43_FW_TYPE_IV 'i'
538struct b43_fw_header {
539
540 u8 type;
541
542 u8 ver;
543 u8 __padding[2];
544
545
546 __be32 size;
547} __packed;
548
549
550#define B43_IV_OFFSET_MASK 0x7FFF
551#define B43_IV_32BIT 0x8000
552struct b43_iv {
553 __be16 offset_size;
554 union {
555 __be16 d16;
556 __be32 d32;
557 } data __packed;
558} __packed;
559
560
561
562struct b43_dma {
563 struct b43_dmaring *tx_ring_AC_BK;
564 struct b43_dmaring *tx_ring_AC_BE;
565 struct b43_dmaring *tx_ring_AC_VI;
566 struct b43_dmaring *tx_ring_AC_VO;
567 struct b43_dmaring *tx_ring_mcast;
568
569 struct b43_dmaring *rx_ring;
570};
571
572struct b43_pio_txqueue;
573struct b43_pio_rxqueue;
574
575
576struct b43_pio {
577 struct b43_pio_txqueue *tx_queue_AC_BK;
578 struct b43_pio_txqueue *tx_queue_AC_BE;
579 struct b43_pio_txqueue *tx_queue_AC_VI;
580 struct b43_pio_txqueue *tx_queue_AC_VO;
581 struct b43_pio_txqueue *tx_queue_mcast;
582
583 struct b43_pio_rxqueue *rx_queue;
584};
585
586
587struct b43_noise_calculation {
588 bool calculation_running;
589 u8 nr_samples;
590 s8 samples[8][4];
591};
592
593struct b43_stats {
594 u8 link_noise;
595};
596
597struct b43_key {
598
599
600
601 struct ieee80211_key_conf *keyconf;
602 u8 algorithm;
603};
604
605
606#define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \
607 (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
608#define B43_QOS_BACKGROUND B43_QOS_PARAMS(0)
609#define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1)
610#define B43_QOS_VIDEO B43_QOS_PARAMS(2)
611#define B43_QOS_VOICE B43_QOS_PARAMS(3)
612
613
614#define B43_NR_QOSPARAMS 16
615enum {
616 B43_QOSPARAM_TXOP = 0,
617 B43_QOSPARAM_CWMIN,
618 B43_QOSPARAM_CWMAX,
619 B43_QOSPARAM_CWCUR,
620 B43_QOSPARAM_AIFS,
621 B43_QOSPARAM_BSLOTS,
622 B43_QOSPARAM_REGGAP,
623 B43_QOSPARAM_STATUS,
624};
625
626
627struct b43_qos_params {
628
629 struct ieee80211_tx_queue_params p;
630};
631
632struct b43_wl;
633
634
635enum b43_firmware_file_type {
636 B43_FWTYPE_PROPRIETARY,
637 B43_FWTYPE_OPENSOURCE,
638 B43_NR_FWTYPES,
639};
640
641
642struct b43_request_fw_context {
643
644 struct b43_wldev *dev;
645
646 enum b43_firmware_file_type req_type;
647
648 char errors[B43_NR_FWTYPES][128];
649
650 char fwname[64];
651
652
653 int fatal_failure;
654};
655
656
657struct b43_firmware_file {
658 const char *filename;
659 const struct firmware *data;
660
661
662
663
664
665
666 enum b43_firmware_file_type type;
667};
668
669
670struct b43_firmware {
671
672 struct b43_firmware_file ucode;
673
674 struct b43_firmware_file pcm;
675
676 struct b43_firmware_file initvals;
677
678 struct b43_firmware_file initvals_band;
679
680
681 u16 rev;
682
683 u16 patch;
684
685
686
687 bool opensource;
688
689
690
691 bool pcm_request_failed;
692};
693
694
695enum {
696 B43_STAT_UNINIT = 0,
697 B43_STAT_INITIALIZED = 1,
698 B43_STAT_STARTED = 2,
699};
700#define b43_status(wldev) atomic_read(&(wldev)->__init_status)
701#define b43_set_status(wldev, stat) do { \
702 atomic_set(&(wldev)->__init_status, (stat)); \
703 smp_wmb(); \
704 } while (0)
705
706
707struct b43_wldev {
708 struct ssb_device *dev;
709 struct b43_wl *wl;
710
711
712
713 atomic_t __init_status;
714
715 bool bad_frames_preempt;
716 bool dfq_valid;
717 bool radio_hw_enable;
718 bool qos_enabled;
719 bool hwcrypto_enabled;
720 bool use_pio;
721
722
723 struct b43_phy phy;
724
725 union {
726
727 struct b43_dma dma;
728
729 struct b43_pio pio;
730 };
731
732
733 bool __using_pio_transfers;
734
735
736 struct b43_stats stats;
737
738
739 u32 irq_reason;
740 u32 dma_reason[6];
741
742 u32 irq_mask;
743
744
745 struct b43_noise_calculation noisecalc;
746
747 int mac_suspended;
748
749
750 struct delayed_work periodic_work;
751 unsigned int periodic_state;
752
753 struct work_struct restart_work;
754
755
756 u16 ktp;
757 struct b43_key key[B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS];
758
759
760 struct b43_firmware fw;
761
762
763 struct list_head list;
764
765
766#ifdef CONFIG_B43_DEBUG
767 struct b43_dfsentry *dfsentry;
768 unsigned int irq_count;
769 unsigned int irq_bit_count[32];
770 unsigned int tx_count;
771 unsigned int rx_count;
772#endif
773};
774
775
776struct b43_wl {
777
778 struct b43_wldev *current_dev;
779
780 struct ieee80211_hw *hw;
781
782
783 struct mutex mutex;
784
785
786 spinlock_t hardirq_lock;
787
788
789
790
791
792
793 u16 mac80211_initially_registered_queues;
794
795
796
797
798
799 struct ieee80211_vif *vif;
800
801 u8 mac_addr[ETH_ALEN];
802
803 u8 bssid[ETH_ALEN];
804
805 int if_type;
806
807 bool operating;
808
809 unsigned int filter_flags;
810
811 struct ieee80211_low_level_stats ieee_stats;
812
813#ifdef CONFIG_B43_HWRNG
814 struct hwrng rng;
815 bool rng_initialized;
816 char rng_name[30 + 1];
817#endif
818
819
820 struct list_head devlist;
821 u8 nr_devs;
822
823 bool radiotap_enabled;
824 bool radio_enabled;
825
826
827 struct sk_buff *current_beacon;
828 bool beacon0_uploaded;
829 bool beacon1_uploaded;
830 bool beacon_templates_virgin;
831 struct work_struct beacon_update_trigger;
832
833
834 struct b43_qos_params qos_params[4];
835
836
837
838
839 struct work_struct txpower_adjust_work;
840
841
842 struct work_struct tx_work;
843
844 struct sk_buff_head tx_queue;
845
846
847 struct b43_leds leds;
848
849
850 u8 pio_scratchspace[110] __attribute__((__aligned__(8)));
851 u8 pio_tailspace[4] __attribute__((__aligned__(8)));
852};
853
854static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
855{
856 return hw->priv;
857}
858
859static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
860{
861 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
862 return ssb_get_drvdata(ssb_dev);
863}
864
865
866static inline int b43_is_mode(struct b43_wl *wl, int type)
867{
868 return (wl->operating && wl->if_type == type);
869}
870
871
872
873
874
875static inline enum ieee80211_band b43_current_band(struct b43_wl *wl)
876{
877 return wl->hw->conf.channel->band;
878}
879
880static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
881{
882 return ssb_read16(dev->dev, offset);
883}
884
885static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
886{
887 ssb_write16(dev->dev, offset, value);
888}
889
890static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
891{
892 return ssb_read32(dev->dev, offset);
893}
894
895static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
896{
897 ssb_write32(dev->dev, offset, value);
898}
899
900static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
901{
902 return dev->__using_pio_transfers;
903}
904
905#ifdef CONFIG_B43_FORCE_PIO
906# define B43_PIO_DEFAULT 1
907#else
908# define B43_PIO_DEFAULT 0
909#endif
910
911
912void b43info(struct b43_wl *wl, const char *fmt, ...)
913 __attribute__ ((format(printf, 2, 3)));
914void b43err(struct b43_wl *wl, const char *fmt, ...)
915 __attribute__ ((format(printf, 2, 3)));
916void b43warn(struct b43_wl *wl, const char *fmt, ...)
917 __attribute__ ((format(printf, 2, 3)));
918void b43dbg(struct b43_wl *wl, const char *fmt, ...)
919 __attribute__ ((format(printf, 2, 3)));
920
921
922
923
924#if B43_DEBUG
925# define B43_WARN_ON(x) WARN_ON(x)
926#else
927static inline bool __b43_warn_on_dummy(bool x) { return x; }
928# define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
929#endif
930
931
932#define INT_TO_Q52(i) ((i) << 2)
933
934#define Q52_TO_INT(q52) ((q52) >> 2)
935
936#define Q52_FMT "%u.%u"
937#define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
938
939#endif
940