linux/drivers/net/wireless/iwlwifi/iwl-agn.c
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   1/******************************************************************************
   2 *
   3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4 *
   5 * Portions of this file are derived from the ipw3945 project, as well
   6 * as portions of the ieee80211 subsystem header files.
   7 *
   8 * This program is free software; you can redistribute it and/or modify it
   9 * under the terms of version 2 of the GNU General Public License as
  10 * published by the Free Software Foundation.
  11 *
  12 * This program is distributed in the hope that it will be useful, but WITHOUT
  13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15 * more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along with
  18 * this program; if not, write to the Free Software Foundation, Inc.,
  19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20 *
  21 * The full GNU General Public License is included in this distribution in the
  22 * file called LICENSE.
  23 *
  24 * Contact Information:
  25 *  Intel Linux Wireless <ilw@linux.intel.com>
  26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27 *
  28 *****************************************************************************/
  29
  30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32#include <linux/kernel.h>
  33#include <linux/module.h>
  34#include <linux/init.h>
  35#include <linux/pci.h>
  36#include <linux/pci-aspm.h>
  37#include <linux/slab.h>
  38#include <linux/dma-mapping.h>
  39#include <linux/delay.h>
  40#include <linux/sched.h>
  41#include <linux/skbuff.h>
  42#include <linux/netdevice.h>
  43#include <linux/wireless.h>
  44#include <linux/firmware.h>
  45#include <linux/etherdevice.h>
  46#include <linux/if_arp.h>
  47
  48#include <net/mac80211.h>
  49
  50#include <asm/div64.h>
  51
  52#define DRV_NAME        "iwlagn"
  53
  54#include "iwl-eeprom.h"
  55#include "iwl-dev.h"
  56#include "iwl-core.h"
  57#include "iwl-io.h"
  58#include "iwl-helpers.h"
  59#include "iwl-sta.h"
  60#include "iwl-agn-calib.h"
  61#include "iwl-agn.h"
  62
  63
  64/******************************************************************************
  65 *
  66 * module boiler plate
  67 *
  68 ******************************************************************************/
  69
  70/*
  71 * module name, copyright, version, etc.
  72 */
  73#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  74
  75#ifdef CONFIG_IWLWIFI_DEBUG
  76#define VD "d"
  77#else
  78#define VD
  79#endif
  80
  81#define DRV_VERSION     IWLWIFI_VERSION VD
  82
  83
  84MODULE_DESCRIPTION(DRV_DESCRIPTION);
  85MODULE_VERSION(DRV_VERSION);
  86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  87MODULE_LICENSE("GPL");
  88MODULE_ALIAS("iwl4965");
  89
  90static int iwlagn_ant_coupling;
  91static bool iwlagn_bt_ch_announce = 1;
  92
  93void iwl_update_chain_flags(struct iwl_priv *priv)
  94{
  95        struct iwl_rxon_context *ctx;
  96
  97        if (priv->cfg->ops->hcmd->set_rxon_chain) {
  98                for_each_context(priv, ctx) {
  99                        priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 100                        if (ctx->active.rx_chain != ctx->staging.rx_chain)
 101                                iwlcore_commit_rxon(priv, ctx);
 102                }
 103        }
 104}
 105
 106static void iwl_clear_free_frames(struct iwl_priv *priv)
 107{
 108        struct list_head *element;
 109
 110        IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 111                       priv->frames_count);
 112
 113        while (!list_empty(&priv->free_frames)) {
 114                element = priv->free_frames.next;
 115                list_del(element);
 116                kfree(list_entry(element, struct iwl_frame, list));
 117                priv->frames_count--;
 118        }
 119
 120        if (priv->frames_count) {
 121                IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 122                            priv->frames_count);
 123                priv->frames_count = 0;
 124        }
 125}
 126
 127static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 128{
 129        struct iwl_frame *frame;
 130        struct list_head *element;
 131        if (list_empty(&priv->free_frames)) {
 132                frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 133                if (!frame) {
 134                        IWL_ERR(priv, "Could not allocate frame!\n");
 135                        return NULL;
 136                }
 137
 138                priv->frames_count++;
 139                return frame;
 140        }
 141
 142        element = priv->free_frames.next;
 143        list_del(element);
 144        return list_entry(element, struct iwl_frame, list);
 145}
 146
 147static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 148{
 149        memset(frame, 0, sizeof(*frame));
 150        list_add(&frame->list, &priv->free_frames);
 151}
 152
 153static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 154                                 struct ieee80211_hdr *hdr,
 155                                 int left)
 156{
 157        lockdep_assert_held(&priv->mutex);
 158
 159        if (!priv->beacon_skb)
 160                return 0;
 161
 162        if (priv->beacon_skb->len > left)
 163                return 0;
 164
 165        memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 166
 167        return priv->beacon_skb->len;
 168}
 169
 170/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 171static void iwl_set_beacon_tim(struct iwl_priv *priv,
 172                               struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 173                               u8 *beacon, u32 frame_size)
 174{
 175        u16 tim_idx;
 176        struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 177
 178        /*
 179         * The index is relative to frame start but we start looking at the
 180         * variable-length part of the beacon.
 181         */
 182        tim_idx = mgmt->u.beacon.variable - beacon;
 183
 184        /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 185        while ((tim_idx < (frame_size - 2)) &&
 186                        (beacon[tim_idx] != WLAN_EID_TIM))
 187                tim_idx += beacon[tim_idx+1] + 2;
 188
 189        /* If TIM field was found, set variables */
 190        if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 191                tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 192                tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 193        } else
 194                IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 195}
 196
 197static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 198                                       struct iwl_frame *frame)
 199{
 200        struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 201        u32 frame_size;
 202        u32 rate_flags;
 203        u32 rate;
 204        /*
 205         * We have to set up the TX command, the TX Beacon command, and the
 206         * beacon contents.
 207         */
 208
 209        lockdep_assert_held(&priv->mutex);
 210
 211        if (!priv->beacon_ctx) {
 212                IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 213                return 0;
 214        }
 215
 216        /* Initialize memory */
 217        tx_beacon_cmd = &frame->u.beacon;
 218        memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 219
 220        /* Set up TX beacon contents */
 221        frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 222                                sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 223        if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 224                return 0;
 225        if (!frame_size)
 226                return 0;
 227
 228        /* Set up TX command fields */
 229        tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 230        tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 231        tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 232        tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 233                TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 234
 235        /* Set up TX beacon command fields */
 236        iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 237                           frame_size);
 238
 239        /* Set up packet rate and flags */
 240        rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 241        priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 242                                              priv->hw_params.valid_tx_ant);
 243        rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 244        if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 245                rate_flags |= RATE_MCS_CCK_MSK;
 246        tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 247                        rate_flags);
 248
 249        return sizeof(*tx_beacon_cmd) + frame_size;
 250}
 251
 252int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 253{
 254        struct iwl_frame *frame;
 255        unsigned int frame_size;
 256        int rc;
 257
 258        frame = iwl_get_free_frame(priv);
 259        if (!frame) {
 260                IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 261                          "command.\n");
 262                return -ENOMEM;
 263        }
 264
 265        frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 266        if (!frame_size) {
 267                IWL_ERR(priv, "Error configuring the beacon command\n");
 268                iwl_free_frame(priv, frame);
 269                return -EINVAL;
 270        }
 271
 272        rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 273                              &frame->u.cmd[0]);
 274
 275        iwl_free_frame(priv, frame);
 276
 277        return rc;
 278}
 279
 280static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 281{
 282        struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 283
 284        dma_addr_t addr = get_unaligned_le32(&tb->lo);
 285        if (sizeof(dma_addr_t) > sizeof(u32))
 286                addr |=
 287                ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 288
 289        return addr;
 290}
 291
 292static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 293{
 294        struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 295
 296        return le16_to_cpu(tb->hi_n_len) >> 4;
 297}
 298
 299static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 300                                  dma_addr_t addr, u16 len)
 301{
 302        struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 303        u16 hi_n_len = len << 4;
 304
 305        put_unaligned_le32(addr, &tb->lo);
 306        if (sizeof(dma_addr_t) > sizeof(u32))
 307                hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 308
 309        tb->hi_n_len = cpu_to_le16(hi_n_len);
 310
 311        tfd->num_tbs = idx + 1;
 312}
 313
 314static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 315{
 316        return tfd->num_tbs & 0x1f;
 317}
 318
 319/**
 320 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 321 * @priv - driver private data
 322 * @txq - tx queue
 323 *
 324 * Does NOT advance any TFD circular buffer read/write indexes
 325 * Does NOT free the TFD itself (which is within circular buffer)
 326 */
 327void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 328{
 329        struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 330        struct iwl_tfd *tfd;
 331        struct pci_dev *dev = priv->pci_dev;
 332        int index = txq->q.read_ptr;
 333        int i;
 334        int num_tbs;
 335
 336        tfd = &tfd_tmp[index];
 337
 338        /* Sanity check on number of chunks */
 339        num_tbs = iwl_tfd_get_num_tbs(tfd);
 340
 341        if (num_tbs >= IWL_NUM_OF_TBS) {
 342                IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 343                /* @todo issue fatal error, it is quite serious situation */
 344                return;
 345        }
 346
 347        /* Unmap tx_cmd */
 348        if (num_tbs)
 349                pci_unmap_single(dev,
 350                                dma_unmap_addr(&txq->meta[index], mapping),
 351                                dma_unmap_len(&txq->meta[index], len),
 352                                PCI_DMA_BIDIRECTIONAL);
 353
 354        /* Unmap chunks, if any. */
 355        for (i = 1; i < num_tbs; i++)
 356                pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 357                                iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 358
 359        /* free SKB */
 360        if (txq->txb) {
 361                struct sk_buff *skb;
 362
 363                skb = txq->txb[txq->q.read_ptr].skb;
 364
 365                /* can be called from irqs-disabled context */
 366                if (skb) {
 367                        dev_kfree_skb_any(skb);
 368                        txq->txb[txq->q.read_ptr].skb = NULL;
 369                }
 370        }
 371}
 372
 373int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 374                                 struct iwl_tx_queue *txq,
 375                                 dma_addr_t addr, u16 len,
 376                                 u8 reset, u8 pad)
 377{
 378        struct iwl_queue *q;
 379        struct iwl_tfd *tfd, *tfd_tmp;
 380        u32 num_tbs;
 381
 382        q = &txq->q;
 383        tfd_tmp = (struct iwl_tfd *)txq->tfds;
 384        tfd = &tfd_tmp[q->write_ptr];
 385
 386        if (reset)
 387                memset(tfd, 0, sizeof(*tfd));
 388
 389        num_tbs = iwl_tfd_get_num_tbs(tfd);
 390
 391        /* Each TFD can point to a maximum 20 Tx buffers */
 392        if (num_tbs >= IWL_NUM_OF_TBS) {
 393                IWL_ERR(priv, "Error can not send more than %d chunks\n",
 394                          IWL_NUM_OF_TBS);
 395                return -EINVAL;
 396        }
 397
 398        BUG_ON(addr & ~DMA_BIT_MASK(36));
 399        if (unlikely(addr & ~IWL_TX_DMA_MASK))
 400                IWL_ERR(priv, "Unaligned address = %llx\n",
 401                          (unsigned long long)addr);
 402
 403        iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 404
 405        return 0;
 406}
 407
 408/*
 409 * Tell nic where to find circular buffer of Tx Frame Descriptors for
 410 * given Tx queue, and enable the DMA channel used for that queue.
 411 *
 412 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 413 * channels supported in hardware.
 414 */
 415int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 416                         struct iwl_tx_queue *txq)
 417{
 418        int txq_id = txq->q.id;
 419
 420        /* Circular buffer (TFD queue in DRAM) physical base address */
 421        iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 422                             txq->q.dma_addr >> 8);
 423
 424        return 0;
 425}
 426
 427/******************************************************************************
 428 *
 429 * Generic RX handler implementations
 430 *
 431 ******************************************************************************/
 432static void iwl_rx_reply_alive(struct iwl_priv *priv,
 433                                struct iwl_rx_mem_buffer *rxb)
 434{
 435        struct iwl_rx_packet *pkt = rxb_addr(rxb);
 436        struct iwl_alive_resp *palive;
 437        struct delayed_work *pwork;
 438
 439        palive = &pkt->u.alive_frame;
 440
 441        IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 442                       "0x%01X 0x%01X\n",
 443                       palive->is_valid, palive->ver_type,
 444                       palive->ver_subtype);
 445
 446        if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
 447                IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 448                memcpy(&priv->card_alive_init,
 449                       &pkt->u.alive_frame,
 450                       sizeof(struct iwl_init_alive_resp));
 451                pwork = &priv->init_alive_start;
 452        } else {
 453                IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
 454                memcpy(&priv->card_alive, &pkt->u.alive_frame,
 455                       sizeof(struct iwl_alive_resp));
 456                pwork = &priv->alive_start;
 457        }
 458
 459        /* We delay the ALIVE response by 5ms to
 460         * give the HW RF Kill time to activate... */
 461        if (palive->is_valid == UCODE_VALID_OK)
 462                queue_delayed_work(priv->workqueue, pwork,
 463                                   msecs_to_jiffies(5));
 464        else
 465                IWL_WARN(priv, "uCode did not respond OK.\n");
 466}
 467
 468static void iwl_bg_beacon_update(struct work_struct *work)
 469{
 470        struct iwl_priv *priv =
 471                container_of(work, struct iwl_priv, beacon_update);
 472        struct sk_buff *beacon;
 473
 474        mutex_lock(&priv->mutex);
 475        if (!priv->beacon_ctx) {
 476                IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 477                goto out;
 478        }
 479
 480        if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 481                /*
 482                 * The ucode will send beacon notifications even in
 483                 * IBSS mode, but we don't want to process them. But
 484                 * we need to defer the type check to here due to
 485                 * requiring locking around the beacon_ctx access.
 486                 */
 487                goto out;
 488        }
 489
 490        /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 491        beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 492        if (!beacon) {
 493                IWL_ERR(priv, "update beacon failed -- keeping old\n");
 494                goto out;
 495        }
 496
 497        /* new beacon skb is allocated every time; dispose previous.*/
 498        dev_kfree_skb(priv->beacon_skb);
 499
 500        priv->beacon_skb = beacon;
 501
 502        iwlagn_send_beacon_cmd(priv);
 503 out:
 504        mutex_unlock(&priv->mutex);
 505}
 506
 507static void iwl_bg_bt_runtime_config(struct work_struct *work)
 508{
 509        struct iwl_priv *priv =
 510                container_of(work, struct iwl_priv, bt_runtime_config);
 511
 512        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 513                return;
 514
 515        /* dont send host command if rf-kill is on */
 516        if (!iwl_is_ready_rf(priv))
 517                return;
 518        priv->cfg->ops->hcmd->send_bt_config(priv);
 519}
 520
 521static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 522{
 523        struct iwl_priv *priv =
 524                container_of(work, struct iwl_priv, bt_full_concurrency);
 525        struct iwl_rxon_context *ctx;
 526
 527        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 528                return;
 529
 530        /* dont send host command if rf-kill is on */
 531        if (!iwl_is_ready_rf(priv))
 532                return;
 533
 534        IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 535                       priv->bt_full_concurrent ?
 536                       "full concurrency" : "3-wire");
 537
 538        /*
 539         * LQ & RXON updated cmds must be sent before BT Config cmd
 540         * to avoid 3-wire collisions
 541         */
 542        mutex_lock(&priv->mutex);
 543        for_each_context(priv, ctx) {
 544                if (priv->cfg->ops->hcmd->set_rxon_chain)
 545                        priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 546                iwlcore_commit_rxon(priv, ctx);
 547        }
 548        mutex_unlock(&priv->mutex);
 549
 550        priv->cfg->ops->hcmd->send_bt_config(priv);
 551}
 552
 553/**
 554 * iwl_bg_statistics_periodic - Timer callback to queue statistics
 555 *
 556 * This callback is provided in order to send a statistics request.
 557 *
 558 * This timer function is continually reset to execute within
 559 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 560 * was received.  We need to ensure we receive the statistics in order
 561 * to update the temperature used for calibrating the TXPOWER.
 562 */
 563static void iwl_bg_statistics_periodic(unsigned long data)
 564{
 565        struct iwl_priv *priv = (struct iwl_priv *)data;
 566
 567        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 568                return;
 569
 570        /* dont send host command if rf-kill is on */
 571        if (!iwl_is_ready_rf(priv))
 572                return;
 573
 574        iwl_send_statistics_request(priv, CMD_ASYNC, false);
 575}
 576
 577
 578static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 579                                        u32 start_idx, u32 num_events,
 580                                        u32 mode)
 581{
 582        u32 i;
 583        u32 ptr;        /* SRAM byte address of log data */
 584        u32 ev, time, data; /* event log data */
 585        unsigned long reg_flags;
 586
 587        if (mode == 0)
 588                ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 589        else
 590                ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 591
 592        /* Make sure device is powered up for SRAM reads */
 593        spin_lock_irqsave(&priv->reg_lock, reg_flags);
 594        if (iwl_grab_nic_access(priv)) {
 595                spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 596                return;
 597        }
 598
 599        /* Set starting address; reads will auto-increment */
 600        _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 601        rmb();
 602
 603        /*
 604         * "time" is actually "data" for mode 0 (no timestamp).
 605         * place event id # at far right for easier visual parsing.
 606         */
 607        for (i = 0; i < num_events; i++) {
 608                ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 609                time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 610                if (mode == 0) {
 611                        trace_iwlwifi_dev_ucode_cont_event(priv,
 612                                                        0, time, ev);
 613                } else {
 614                        data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 615                        trace_iwlwifi_dev_ucode_cont_event(priv,
 616                                                time, data, ev);
 617                }
 618        }
 619        /* Allow device to power down */
 620        iwl_release_nic_access(priv);
 621        spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 622}
 623
 624static void iwl_continuous_event_trace(struct iwl_priv *priv)
 625{
 626        u32 capacity;   /* event log capacity in # entries */
 627        u32 base;       /* SRAM byte address of event log header */
 628        u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 629        u32 num_wraps;  /* # times uCode wrapped to top of log */
 630        u32 next_entry; /* index of next entry to be written by uCode */
 631
 632        if (priv->ucode_type == UCODE_INIT)
 633                base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 634        else
 635                base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 636        if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 637                capacity = iwl_read_targ_mem(priv, base);
 638                num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 639                mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 640                next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 641        } else
 642                return;
 643
 644        if (num_wraps == priv->event_log.num_wraps) {
 645                iwl_print_cont_event_trace(priv,
 646                                       base, priv->event_log.next_entry,
 647                                       next_entry - priv->event_log.next_entry,
 648                                       mode);
 649                priv->event_log.non_wraps_count++;
 650        } else {
 651                if ((num_wraps - priv->event_log.num_wraps) > 1)
 652                        priv->event_log.wraps_more_count++;
 653                else
 654                        priv->event_log.wraps_once_count++;
 655                trace_iwlwifi_dev_ucode_wrap_event(priv,
 656                                num_wraps - priv->event_log.num_wraps,
 657                                next_entry, priv->event_log.next_entry);
 658                if (next_entry < priv->event_log.next_entry) {
 659                        iwl_print_cont_event_trace(priv, base,
 660                               priv->event_log.next_entry,
 661                               capacity - priv->event_log.next_entry,
 662                               mode);
 663
 664                        iwl_print_cont_event_trace(priv, base, 0,
 665                                next_entry, mode);
 666                } else {
 667                        iwl_print_cont_event_trace(priv, base,
 668                               next_entry, capacity - next_entry,
 669                               mode);
 670
 671                        iwl_print_cont_event_trace(priv, base, 0,
 672                                next_entry, mode);
 673                }
 674        }
 675        priv->event_log.num_wraps = num_wraps;
 676        priv->event_log.next_entry = next_entry;
 677}
 678
 679/**
 680 * iwl_bg_ucode_trace - Timer callback to log ucode event
 681 *
 682 * The timer is continually set to execute every
 683 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 684 * this function is to perform continuous uCode event logging operation
 685 * if enabled
 686 */
 687static void iwl_bg_ucode_trace(unsigned long data)
 688{
 689        struct iwl_priv *priv = (struct iwl_priv *)data;
 690
 691        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 692                return;
 693
 694        if (priv->event_log.ucode_trace) {
 695                iwl_continuous_event_trace(priv);
 696                /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 697                mod_timer(&priv->ucode_trace,
 698                         jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 699        }
 700}
 701
 702static void iwl_rx_beacon_notif(struct iwl_priv *priv,
 703                                struct iwl_rx_mem_buffer *rxb)
 704{
 705        struct iwl_rx_packet *pkt = rxb_addr(rxb);
 706        struct iwl4965_beacon_notif *beacon =
 707                (struct iwl4965_beacon_notif *)pkt->u.raw;
 708#ifdef CONFIG_IWLWIFI_DEBUG
 709        u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
 710
 711        IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
 712                "tsf %d %d rate %d\n",
 713                le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
 714                beacon->beacon_notify_hdr.failure_frame,
 715                le32_to_cpu(beacon->ibss_mgr_status),
 716                le32_to_cpu(beacon->high_tsf),
 717                le32_to_cpu(beacon->low_tsf), rate);
 718#endif
 719
 720        priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
 721
 722        if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 723                queue_work(priv->workqueue, &priv->beacon_update);
 724}
 725
 726/* Handle notification from uCode that card's power state is changing
 727 * due to software, hardware, or critical temperature RFKILL */
 728static void iwl_rx_card_state_notif(struct iwl_priv *priv,
 729                                    struct iwl_rx_mem_buffer *rxb)
 730{
 731        struct iwl_rx_packet *pkt = rxb_addr(rxb);
 732        u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
 733        unsigned long status = priv->status;
 734
 735        IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
 736                          (flags & HW_CARD_DISABLED) ? "Kill" : "On",
 737                          (flags & SW_CARD_DISABLED) ? "Kill" : "On",
 738                          (flags & CT_CARD_DISABLED) ?
 739                          "Reached" : "Not reached");
 740
 741        if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 742                     CT_CARD_DISABLED)) {
 743
 744                iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
 745                            CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 746
 747                iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 748                                        HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 749
 750                if (!(flags & RXON_CARD_DISABLED)) {
 751                        iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 752                                    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 753                        iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 754                                        HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 755                }
 756                if (flags & CT_CARD_DISABLED)
 757                        iwl_tt_enter_ct_kill(priv);
 758        }
 759        if (!(flags & CT_CARD_DISABLED))
 760                iwl_tt_exit_ct_kill(priv);
 761
 762        if (flags & HW_CARD_DISABLED)
 763                set_bit(STATUS_RF_KILL_HW, &priv->status);
 764        else
 765                clear_bit(STATUS_RF_KILL_HW, &priv->status);
 766
 767
 768        if (!(flags & RXON_CARD_DISABLED))
 769                iwl_scan_cancel(priv);
 770
 771        if ((test_bit(STATUS_RF_KILL_HW, &status) !=
 772             test_bit(STATUS_RF_KILL_HW, &priv->status)))
 773                wiphy_rfkill_set_hw_state(priv->hw->wiphy,
 774                        test_bit(STATUS_RF_KILL_HW, &priv->status));
 775        else
 776                wake_up_interruptible(&priv->wait_command_queue);
 777}
 778
 779static void iwl_bg_tx_flush(struct work_struct *work)
 780{
 781        struct iwl_priv *priv =
 782                container_of(work, struct iwl_priv, tx_flush);
 783
 784        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 785                return;
 786
 787        /* do nothing if rf-kill is on */
 788        if (!iwl_is_ready_rf(priv))
 789                return;
 790
 791        if (priv->cfg->ops->lib->txfifo_flush) {
 792                IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 793                iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 794        }
 795}
 796
 797/**
 798 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
 799 *
 800 * Setup the RX handlers for each of the reply types sent from the uCode
 801 * to the host.
 802 *
 803 * This function chains into the hardware specific files for them to setup
 804 * any hardware specific handlers as well.
 805 */
 806static void iwl_setup_rx_handlers(struct iwl_priv *priv)
 807{
 808        priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
 809        priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
 810        priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
 811        priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
 812                        iwl_rx_spectrum_measure_notif;
 813        priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
 814        priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
 815            iwl_rx_pm_debug_statistics_notif;
 816        priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
 817
 818        /*
 819         * The same handler is used for both the REPLY to a discrete
 820         * statistics request from the host as well as for the periodic
 821         * statistics notifications (after received beacons) from the uCode.
 822         */
 823        priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
 824        priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
 825
 826        iwl_setup_rx_scan_handlers(priv);
 827
 828        /* status change handler */
 829        priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
 830
 831        priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
 832            iwl_rx_missed_beacon_notif;
 833        /* Rx handlers */
 834        priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
 835        priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
 836        /* block ack */
 837        priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
 838        /* Set up hardware specific Rx handlers */
 839        priv->cfg->ops->lib->rx_handler_setup(priv);
 840}
 841
 842/**
 843 * iwl_rx_handle - Main entry function for receiving responses from uCode
 844 *
 845 * Uses the priv->rx_handlers callback function array to invoke
 846 * the appropriate handlers, including command responses,
 847 * frame-received notifications, and other notifications.
 848 */
 849void iwl_rx_handle(struct iwl_priv *priv)
 850{
 851        struct iwl_rx_mem_buffer *rxb;
 852        struct iwl_rx_packet *pkt;
 853        struct iwl_rx_queue *rxq = &priv->rxq;
 854        u32 r, i;
 855        int reclaim;
 856        unsigned long flags;
 857        u8 fill_rx = 0;
 858        u32 count = 8;
 859        int total_empty;
 860
 861        /* uCode's read index (stored in shared DRAM) indicates the last Rx
 862         * buffer that the driver may process (last buffer filled by ucode). */
 863        r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 864        i = rxq->read;
 865
 866        /* Rx interrupt, but nothing sent from uCode */
 867        if (i == r)
 868                IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
 869
 870        /* calculate total frames need to be restock after handling RX */
 871        total_empty = r - rxq->write_actual;
 872        if (total_empty < 0)
 873                total_empty += RX_QUEUE_SIZE;
 874
 875        if (total_empty > (RX_QUEUE_SIZE / 2))
 876                fill_rx = 1;
 877
 878        while (i != r) {
 879                int len;
 880
 881                rxb = rxq->queue[i];
 882
 883                /* If an RXB doesn't have a Rx queue slot associated with it,
 884                 * then a bug has been introduced in the queue refilling
 885                 * routines -- catch it here */
 886                BUG_ON(rxb == NULL);
 887
 888                rxq->queue[i] = NULL;
 889
 890                pci_unmap_page(priv->pci_dev, rxb->page_dma,
 891                               PAGE_SIZE << priv->hw_params.rx_page_order,
 892                               PCI_DMA_FROMDEVICE);
 893                pkt = rxb_addr(rxb);
 894
 895                len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 896                len += sizeof(u32); /* account for status word */
 897                trace_iwlwifi_dev_rx(priv, pkt, len);
 898
 899                /* Reclaim a command buffer only if this packet is a response
 900                 *   to a (driver-originated) command.
 901                 * If the packet (e.g. Rx frame) originated from uCode,
 902                 *   there is no command buffer to reclaim.
 903                 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 904                 *   but apparently a few don't get set; catch them here. */
 905                reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 906                        (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 907                        (pkt->hdr.cmd != REPLY_RX) &&
 908                        (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 909                        (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 910                        (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 911                        (pkt->hdr.cmd != REPLY_TX);
 912
 913                /* Based on type of command response or notification,
 914                 *   handle those that need handling via function in
 915                 *   rx_handlers table.  See iwl_setup_rx_handlers() */
 916                if (priv->rx_handlers[pkt->hdr.cmd]) {
 917                        IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
 918                                i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 919                        priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
 920                        priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
 921                } else {
 922                        /* No handling needed */
 923                        IWL_DEBUG_RX(priv,
 924                                "r %d i %d No handler needed for %s, 0x%02x\n",
 925                                r, i, get_cmd_string(pkt->hdr.cmd),
 926                                pkt->hdr.cmd);
 927                }
 928
 929                /*
 930                 * XXX: After here, we should always check rxb->page
 931                 * against NULL before touching it or its virtual
 932                 * memory (pkt). Because some rx_handler might have
 933                 * already taken or freed the pages.
 934                 */
 935
 936                if (reclaim) {
 937                        /* Invoke any callbacks, transfer the buffer to caller,
 938                         * and fire off the (possibly) blocking iwl_send_cmd()
 939                         * as we reclaim the driver command queue */
 940                        if (rxb->page)
 941                                iwl_tx_cmd_complete(priv, rxb);
 942                        else
 943                                IWL_WARN(priv, "Claim null rxb?\n");
 944                }
 945
 946                /* Reuse the page if possible. For notification packets and
 947                 * SKBs that fail to Rx correctly, add them back into the
 948                 * rx_free list for reuse later. */
 949                spin_lock_irqsave(&rxq->lock, flags);
 950                if (rxb->page != NULL) {
 951                        rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
 952                                0, PAGE_SIZE << priv->hw_params.rx_page_order,
 953                                PCI_DMA_FROMDEVICE);
 954                        list_add_tail(&rxb->list, &rxq->rx_free);
 955                        rxq->free_count++;
 956                } else
 957                        list_add_tail(&rxb->list, &rxq->rx_used);
 958
 959                spin_unlock_irqrestore(&rxq->lock, flags);
 960
 961                i = (i + 1) & RX_QUEUE_MASK;
 962                /* If there are a lot of unused frames,
 963                 * restock the Rx queue so ucode wont assert. */
 964                if (fill_rx) {
 965                        count++;
 966                        if (count >= 8) {
 967                                rxq->read = i;
 968                                iwlagn_rx_replenish_now(priv);
 969                                count = 0;
 970                        }
 971                }
 972        }
 973
 974        /* Backtrack one entry */
 975        rxq->read = i;
 976        if (fill_rx)
 977                iwlagn_rx_replenish_now(priv);
 978        else
 979                iwlagn_rx_queue_restock(priv);
 980}
 981
 982/* call this function to flush any scheduled tasklet */
 983static inline void iwl_synchronize_irq(struct iwl_priv *priv)
 984{
 985        /* wait to make sure we flush pending tasklet*/
 986        synchronize_irq(priv->pci_dev->irq);
 987        tasklet_kill(&priv->irq_tasklet);
 988}
 989
 990static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
 991{
 992        u32 inta, handled = 0;
 993        u32 inta_fh;
 994        unsigned long flags;
 995        u32 i;
 996#ifdef CONFIG_IWLWIFI_DEBUG
 997        u32 inta_mask;
 998#endif
 999
1000        spin_lock_irqsave(&priv->lock, flags);
1001
1002        /* Ack/clear/reset pending uCode interrupts.
1003         * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1004         *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1005        inta = iwl_read32(priv, CSR_INT);
1006        iwl_write32(priv, CSR_INT, inta);
1007
1008        /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1009         * Any new interrupts that happen after this, either while we're
1010         * in this tasklet, or later, will show up in next ISR/tasklet. */
1011        inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1012        iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1013
1014#ifdef CONFIG_IWLWIFI_DEBUG
1015        if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1016                /* just for debug */
1017                inta_mask = iwl_read32(priv, CSR_INT_MASK);
1018                IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1019                              inta, inta_mask, inta_fh);
1020        }
1021#endif
1022
1023        spin_unlock_irqrestore(&priv->lock, flags);
1024
1025        /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1026         * atomic, make sure that inta covers all the interrupts that
1027         * we've discovered, even if FH interrupt came in just after
1028         * reading CSR_INT. */
1029        if (inta_fh & CSR49_FH_INT_RX_MASK)
1030                inta |= CSR_INT_BIT_FH_RX;
1031        if (inta_fh & CSR49_FH_INT_TX_MASK)
1032                inta |= CSR_INT_BIT_FH_TX;
1033
1034        /* Now service all interrupt bits discovered above. */
1035        if (inta & CSR_INT_BIT_HW_ERR) {
1036                IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1037
1038                /* Tell the device to stop sending interrupts */
1039                iwl_disable_interrupts(priv);
1040
1041                priv->isr_stats.hw++;
1042                iwl_irq_handle_error(priv);
1043
1044                handled |= CSR_INT_BIT_HW_ERR;
1045
1046                return;
1047        }
1048
1049#ifdef CONFIG_IWLWIFI_DEBUG
1050        if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1051                /* NIC fires this, but we don't use it, redundant with WAKEUP */
1052                if (inta & CSR_INT_BIT_SCD) {
1053                        IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1054                                      "the frame/frames.\n");
1055                        priv->isr_stats.sch++;
1056                }
1057
1058                /* Alive notification via Rx interrupt will do the real work */
1059                if (inta & CSR_INT_BIT_ALIVE) {
1060                        IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1061                        priv->isr_stats.alive++;
1062                }
1063        }
1064#endif
1065        /* Safely ignore these bits for debug checks below */
1066        inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1067
1068        /* HW RF KILL switch toggled */
1069        if (inta & CSR_INT_BIT_RF_KILL) {
1070                int hw_rf_kill = 0;
1071                if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1072                                CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1073                        hw_rf_kill = 1;
1074
1075                IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1076                                hw_rf_kill ? "disable radio" : "enable radio");
1077
1078                priv->isr_stats.rfkill++;
1079
1080                /* driver only loads ucode once setting the interface up.
1081                 * the driver allows loading the ucode even if the radio
1082                 * is killed. Hence update the killswitch state here. The
1083                 * rfkill handler will care about restarting if needed.
1084                 */
1085                if (!test_bit(STATUS_ALIVE, &priv->status)) {
1086                        if (hw_rf_kill)
1087                                set_bit(STATUS_RF_KILL_HW, &priv->status);
1088                        else
1089                                clear_bit(STATUS_RF_KILL_HW, &priv->status);
1090                        wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1091                }
1092
1093                handled |= CSR_INT_BIT_RF_KILL;
1094        }
1095
1096        /* Chip got too hot and stopped itself */
1097        if (inta & CSR_INT_BIT_CT_KILL) {
1098                IWL_ERR(priv, "Microcode CT kill error detected.\n");
1099                priv->isr_stats.ctkill++;
1100                handled |= CSR_INT_BIT_CT_KILL;
1101        }
1102
1103        /* Error detected by uCode */
1104        if (inta & CSR_INT_BIT_SW_ERR) {
1105                IWL_ERR(priv, "Microcode SW error detected. "
1106                        " Restarting 0x%X.\n", inta);
1107                priv->isr_stats.sw++;
1108                iwl_irq_handle_error(priv);
1109                handled |= CSR_INT_BIT_SW_ERR;
1110        }
1111
1112        /*
1113         * uCode wakes up after power-down sleep.
1114         * Tell device about any new tx or host commands enqueued,
1115         * and about any Rx buffers made available while asleep.
1116         */
1117        if (inta & CSR_INT_BIT_WAKEUP) {
1118                IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1119                iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1120                for (i = 0; i < priv->hw_params.max_txq_num; i++)
1121                        iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1122                priv->isr_stats.wakeup++;
1123                handled |= CSR_INT_BIT_WAKEUP;
1124        }
1125
1126        /* All uCode command responses, including Tx command responses,
1127         * Rx "responses" (frame-received notification), and other
1128         * notifications from uCode come through here*/
1129        if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1130                iwl_rx_handle(priv);
1131                priv->isr_stats.rx++;
1132                handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1133        }
1134
1135        /* This "Tx" DMA channel is used only for loading uCode */
1136        if (inta & CSR_INT_BIT_FH_TX) {
1137                IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1138                priv->isr_stats.tx++;
1139                handled |= CSR_INT_BIT_FH_TX;
1140                /* Wake up uCode load routine, now that load is complete */
1141                priv->ucode_write_complete = 1;
1142                wake_up_interruptible(&priv->wait_command_queue);
1143        }
1144
1145        if (inta & ~handled) {
1146                IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1147                priv->isr_stats.unhandled++;
1148        }
1149
1150        if (inta & ~(priv->inta_mask)) {
1151                IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1152                         inta & ~priv->inta_mask);
1153                IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1154        }
1155
1156        /* Re-enable all interrupts */
1157        /* only Re-enable if disabled by irq */
1158        if (test_bit(STATUS_INT_ENABLED, &priv->status))
1159                iwl_enable_interrupts(priv);
1160        /* Re-enable RF_KILL if it occurred */
1161        else if (handled & CSR_INT_BIT_RF_KILL)
1162                iwl_enable_rfkill_int(priv);
1163
1164#ifdef CONFIG_IWLWIFI_DEBUG
1165        if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1166                inta = iwl_read32(priv, CSR_INT);
1167                inta_mask = iwl_read32(priv, CSR_INT_MASK);
1168                inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1169                IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1170                        "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1171        }
1172#endif
1173}
1174
1175/* tasklet for iwlagn interrupt */
1176static void iwl_irq_tasklet(struct iwl_priv *priv)
1177{
1178        u32 inta = 0;
1179        u32 handled = 0;
1180        unsigned long flags;
1181        u32 i;
1182#ifdef CONFIG_IWLWIFI_DEBUG
1183        u32 inta_mask;
1184#endif
1185
1186        spin_lock_irqsave(&priv->lock, flags);
1187
1188        /* Ack/clear/reset pending uCode interrupts.
1189         * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1190         */
1191        /* There is a hardware bug in the interrupt mask function that some
1192         * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1193         * they are disabled in the CSR_INT_MASK register. Furthermore the
1194         * ICT interrupt handling mechanism has another bug that might cause
1195         * these unmasked interrupts fail to be detected. We workaround the
1196         * hardware bugs here by ACKing all the possible interrupts so that
1197         * interrupt coalescing can still be achieved.
1198         */
1199        iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1200
1201        inta = priv->_agn.inta;
1202
1203#ifdef CONFIG_IWLWIFI_DEBUG
1204        if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1205                /* just for debug */
1206                inta_mask = iwl_read32(priv, CSR_INT_MASK);
1207                IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1208                                inta, inta_mask);
1209        }
1210#endif
1211
1212        spin_unlock_irqrestore(&priv->lock, flags);
1213
1214        /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1215        priv->_agn.inta = 0;
1216
1217        /* Now service all interrupt bits discovered above. */
1218        if (inta & CSR_INT_BIT_HW_ERR) {
1219                IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1220
1221                /* Tell the device to stop sending interrupts */
1222                iwl_disable_interrupts(priv);
1223
1224                priv->isr_stats.hw++;
1225                iwl_irq_handle_error(priv);
1226
1227                handled |= CSR_INT_BIT_HW_ERR;
1228
1229                return;
1230        }
1231
1232#ifdef CONFIG_IWLWIFI_DEBUG
1233        if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1234                /* NIC fires this, but we don't use it, redundant with WAKEUP */
1235                if (inta & CSR_INT_BIT_SCD) {
1236                        IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1237                                      "the frame/frames.\n");
1238                        priv->isr_stats.sch++;
1239                }
1240
1241                /* Alive notification via Rx interrupt will do the real work */
1242                if (inta & CSR_INT_BIT_ALIVE) {
1243                        IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1244                        priv->isr_stats.alive++;
1245                }
1246        }
1247#endif
1248        /* Safely ignore these bits for debug checks below */
1249        inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1250
1251        /* HW RF KILL switch toggled */
1252        if (inta & CSR_INT_BIT_RF_KILL) {
1253                int hw_rf_kill = 0;
1254                if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1255                                CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1256                        hw_rf_kill = 1;
1257
1258                IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1259                                hw_rf_kill ? "disable radio" : "enable radio");
1260
1261                priv->isr_stats.rfkill++;
1262
1263                /* driver only loads ucode once setting the interface up.
1264                 * the driver allows loading the ucode even if the radio
1265                 * is killed. Hence update the killswitch state here. The
1266                 * rfkill handler will care about restarting if needed.
1267                 */
1268                if (!test_bit(STATUS_ALIVE, &priv->status)) {
1269                        if (hw_rf_kill)
1270                                set_bit(STATUS_RF_KILL_HW, &priv->status);
1271                        else
1272                                clear_bit(STATUS_RF_KILL_HW, &priv->status);
1273                        wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1274                }
1275
1276                handled |= CSR_INT_BIT_RF_KILL;
1277        }
1278
1279        /* Chip got too hot and stopped itself */
1280        if (inta & CSR_INT_BIT_CT_KILL) {
1281                IWL_ERR(priv, "Microcode CT kill error detected.\n");
1282                priv->isr_stats.ctkill++;
1283                handled |= CSR_INT_BIT_CT_KILL;
1284        }
1285
1286        /* Error detected by uCode */
1287        if (inta & CSR_INT_BIT_SW_ERR) {
1288                IWL_ERR(priv, "Microcode SW error detected. "
1289                        " Restarting 0x%X.\n", inta);
1290                priv->isr_stats.sw++;
1291                iwl_irq_handle_error(priv);
1292                handled |= CSR_INT_BIT_SW_ERR;
1293        }
1294
1295        /* uCode wakes up after power-down sleep */
1296        if (inta & CSR_INT_BIT_WAKEUP) {
1297                IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1298                iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1299                for (i = 0; i < priv->hw_params.max_txq_num; i++)
1300                        iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1301
1302                priv->isr_stats.wakeup++;
1303
1304                handled |= CSR_INT_BIT_WAKEUP;
1305        }
1306
1307        /* All uCode command responses, including Tx command responses,
1308         * Rx "responses" (frame-received notification), and other
1309         * notifications from uCode come through here*/
1310        if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1311                        CSR_INT_BIT_RX_PERIODIC)) {
1312                IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1313                if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1314                        handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1315                        iwl_write32(priv, CSR_FH_INT_STATUS,
1316                                        CSR49_FH_INT_RX_MASK);
1317                }
1318                if (inta & CSR_INT_BIT_RX_PERIODIC) {
1319                        handled |= CSR_INT_BIT_RX_PERIODIC;
1320                        iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1321                }
1322                /* Sending RX interrupt require many steps to be done in the
1323                 * the device:
1324                 * 1- write interrupt to current index in ICT table.
1325                 * 2- dma RX frame.
1326                 * 3- update RX shared data to indicate last write index.
1327                 * 4- send interrupt.
1328                 * This could lead to RX race, driver could receive RX interrupt
1329                 * but the shared data changes does not reflect this;
1330                 * periodic interrupt will detect any dangling Rx activity.
1331                 */
1332
1333                /* Disable periodic interrupt; we use it as just a one-shot. */
1334                iwl_write8(priv, CSR_INT_PERIODIC_REG,
1335                            CSR_INT_PERIODIC_DIS);
1336                iwl_rx_handle(priv);
1337
1338                /*
1339                 * Enable periodic interrupt in 8 msec only if we received
1340                 * real RX interrupt (instead of just periodic int), to catch
1341                 * any dangling Rx interrupt.  If it was just the periodic
1342                 * interrupt, there was no dangling Rx activity, and no need
1343                 * to extend the periodic interrupt; one-shot is enough.
1344                 */
1345                if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1346                        iwl_write8(priv, CSR_INT_PERIODIC_REG,
1347                                    CSR_INT_PERIODIC_ENA);
1348
1349                priv->isr_stats.rx++;
1350        }
1351
1352        /* This "Tx" DMA channel is used only for loading uCode */
1353        if (inta & CSR_INT_BIT_FH_TX) {
1354                iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1355                IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1356                priv->isr_stats.tx++;
1357                handled |= CSR_INT_BIT_FH_TX;
1358                /* Wake up uCode load routine, now that load is complete */
1359                priv->ucode_write_complete = 1;
1360                wake_up_interruptible(&priv->wait_command_queue);
1361        }
1362
1363        if (inta & ~handled) {
1364                IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1365                priv->isr_stats.unhandled++;
1366        }
1367
1368        if (inta & ~(priv->inta_mask)) {
1369                IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1370                         inta & ~priv->inta_mask);
1371        }
1372
1373        /* Re-enable all interrupts */
1374        /* only Re-enable if disabled by irq */
1375        if (test_bit(STATUS_INT_ENABLED, &priv->status))
1376                iwl_enable_interrupts(priv);
1377        /* Re-enable RF_KILL if it occurred */
1378        else if (handled & CSR_INT_BIT_RF_KILL)
1379                iwl_enable_rfkill_int(priv);
1380}
1381
1382/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1383#define ACK_CNT_RATIO (50)
1384#define BA_TIMEOUT_CNT (5)
1385#define BA_TIMEOUT_MAX (16)
1386
1387/**
1388 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1389 *
1390 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1391 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1392 * operation state.
1393 */
1394bool iwl_good_ack_health(struct iwl_priv *priv,
1395                                struct iwl_rx_packet *pkt)
1396{
1397        bool rc = true;
1398        int actual_ack_cnt_delta, expected_ack_cnt_delta;
1399        int ba_timeout_delta;
1400
1401        actual_ack_cnt_delta =
1402                le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1403                le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1404        expected_ack_cnt_delta =
1405                le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1406                le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1407        ba_timeout_delta =
1408                le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1409                le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1410        if ((priv->_agn.agg_tids_count > 0) &&
1411            (expected_ack_cnt_delta > 0) &&
1412            (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1413                < ACK_CNT_RATIO) &&
1414            (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1415                IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1416                                " expected_ack_cnt = %d\n",
1417                                actual_ack_cnt_delta, expected_ack_cnt_delta);
1418
1419#ifdef CONFIG_IWLWIFI_DEBUGFS
1420                /*
1421                 * This is ifdef'ed on DEBUGFS because otherwise the
1422                 * statistics aren't available. If DEBUGFS is set but
1423                 * DEBUG is not, these will just compile out.
1424                 */
1425                IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1426                                priv->_agn.delta_statistics.tx.rx_detected_cnt);
1427                IWL_DEBUG_RADIO(priv,
1428                                "ack_or_ba_timeout_collision delta = %d\n",
1429                                priv->_agn.delta_statistics.tx.
1430                                ack_or_ba_timeout_collision);
1431#endif
1432                IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1433                                ba_timeout_delta);
1434                if (!actual_ack_cnt_delta &&
1435                    (ba_timeout_delta >= BA_TIMEOUT_MAX))
1436                        rc = false;
1437        }
1438        return rc;
1439}
1440
1441
1442/*****************************************************************************
1443 *
1444 * sysfs attributes
1445 *
1446 *****************************************************************************/
1447
1448#ifdef CONFIG_IWLWIFI_DEBUG
1449
1450/*
1451 * The following adds a new attribute to the sysfs representation
1452 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1453 * used for controlling the debug level.
1454 *
1455 * See the level definitions in iwl for details.
1456 *
1457 * The debug_level being managed using sysfs below is a per device debug
1458 * level that is used instead of the global debug level if it (the per
1459 * device debug level) is set.
1460 */
1461static ssize_t show_debug_level(struct device *d,
1462                                struct device_attribute *attr, char *buf)
1463{
1464        struct iwl_priv *priv = dev_get_drvdata(d);
1465        return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1466}
1467static ssize_t store_debug_level(struct device *d,
1468                                struct device_attribute *attr,
1469                                 const char *buf, size_t count)
1470{
1471        struct iwl_priv *priv = dev_get_drvdata(d);
1472        unsigned long val;
1473        int ret;
1474
1475        ret = strict_strtoul(buf, 0, &val);
1476        if (ret)
1477                IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1478        else {
1479                priv->debug_level = val;
1480                if (iwl_alloc_traffic_mem(priv))
1481                        IWL_ERR(priv,
1482                                "Not enough memory to generate traffic log\n");
1483        }
1484        return strnlen(buf, count);
1485}
1486
1487static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1488                        show_debug_level, store_debug_level);
1489
1490
1491#endif /* CONFIG_IWLWIFI_DEBUG */
1492
1493
1494static ssize_t show_temperature(struct device *d,
1495                                struct device_attribute *attr, char *buf)
1496{
1497        struct iwl_priv *priv = dev_get_drvdata(d);
1498
1499        if (!iwl_is_alive(priv))
1500                return -EAGAIN;
1501
1502        return sprintf(buf, "%d\n", priv->temperature);
1503}
1504
1505static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1506
1507static ssize_t show_tx_power(struct device *d,
1508                             struct device_attribute *attr, char *buf)
1509{
1510        struct iwl_priv *priv = dev_get_drvdata(d);
1511
1512        if (!iwl_is_ready_rf(priv))
1513                return sprintf(buf, "off\n");
1514        else
1515                return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1516}
1517
1518static ssize_t store_tx_power(struct device *d,
1519                              struct device_attribute *attr,
1520                              const char *buf, size_t count)
1521{
1522        struct iwl_priv *priv = dev_get_drvdata(d);
1523        unsigned long val;
1524        int ret;
1525
1526        ret = strict_strtoul(buf, 10, &val);
1527        if (ret)
1528                IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1529        else {
1530                ret = iwl_set_tx_power(priv, val, false);
1531                if (ret)
1532                        IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1533                                ret);
1534                else
1535                        ret = count;
1536        }
1537        return ret;
1538}
1539
1540static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1541
1542static struct attribute *iwl_sysfs_entries[] = {
1543        &dev_attr_temperature.attr,
1544        &dev_attr_tx_power.attr,
1545#ifdef CONFIG_IWLWIFI_DEBUG
1546        &dev_attr_debug_level.attr,
1547#endif
1548        NULL
1549};
1550
1551static struct attribute_group iwl_attribute_group = {
1552        .name = NULL,           /* put in device directory */
1553        .attrs = iwl_sysfs_entries,
1554};
1555
1556/******************************************************************************
1557 *
1558 * uCode download functions
1559 *
1560 ******************************************************************************/
1561
1562static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1563{
1564        iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1565        iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1566        iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1567        iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1568        iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1569        iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1570}
1571
1572static void iwl_nic_start(struct iwl_priv *priv)
1573{
1574        /* Remove all resets to allow NIC to operate */
1575        iwl_write32(priv, CSR_RESET, 0);
1576}
1577
1578struct iwlagn_ucode_capabilities {
1579        u32 max_probe_length;
1580        u32 standard_phy_calibration_size;
1581        bool pan;
1582};
1583
1584static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1585static int iwl_mac_setup_register(struct iwl_priv *priv,
1586                                  struct iwlagn_ucode_capabilities *capa);
1587
1588#define UCODE_EXPERIMENTAL_INDEX        100
1589#define UCODE_EXPERIMENTAL_TAG          "exp"
1590
1591static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1592{
1593        const char *name_pre = priv->cfg->fw_name_pre;
1594        char tag[8];
1595
1596        if (first) {
1597#ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1598                priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1599                strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1600        } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1601#endif
1602                priv->fw_index = priv->cfg->ucode_api_max;
1603                sprintf(tag, "%d", priv->fw_index);
1604        } else {
1605                priv->fw_index--;
1606                sprintf(tag, "%d", priv->fw_index);
1607        }
1608
1609        if (priv->fw_index < priv->cfg->ucode_api_min) {
1610                IWL_ERR(priv, "no suitable firmware found!\n");
1611                return -ENOENT;
1612        }
1613
1614        sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1615
1616        IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1617                       (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1618                                ? "EXPERIMENTAL " : "",
1619                       priv->firmware_name);
1620
1621        return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1622                                       &priv->pci_dev->dev, GFP_KERNEL, priv,
1623                                       iwl_ucode_callback);
1624}
1625
1626struct iwlagn_firmware_pieces {
1627        const void *inst, *data, *init, *init_data, *boot;
1628        size_t inst_size, data_size, init_size, init_data_size, boot_size;
1629
1630        u32 build;
1631
1632        u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1633        u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1634};
1635
1636static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1637                                       const struct firmware *ucode_raw,
1638                                       struct iwlagn_firmware_pieces *pieces)
1639{
1640        struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1641        u32 api_ver, hdr_size;
1642        const u8 *src;
1643
1644        priv->ucode_ver = le32_to_cpu(ucode->ver);
1645        api_ver = IWL_UCODE_API(priv->ucode_ver);
1646
1647        switch (api_ver) {
1648        default:
1649                /*
1650                 * 4965 doesn't revision the firmware file format
1651                 * along with the API version, it always uses v1
1652                 * file format.
1653                 */
1654                if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1655                                CSR_HW_REV_TYPE_4965) {
1656                        hdr_size = 28;
1657                        if (ucode_raw->size < hdr_size) {
1658                                IWL_ERR(priv, "File size too small!\n");
1659                                return -EINVAL;
1660                        }
1661                        pieces->build = le32_to_cpu(ucode->u.v2.build);
1662                        pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1663                        pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1664                        pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1665                        pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1666                        pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1667                        src = ucode->u.v2.data;
1668                        break;
1669                }
1670                /* fall through for 4965 */
1671        case 0:
1672        case 1:
1673        case 2:
1674                hdr_size = 24;
1675                if (ucode_raw->size < hdr_size) {
1676                        IWL_ERR(priv, "File size too small!\n");
1677                        return -EINVAL;
1678                }
1679                pieces->build = 0;
1680                pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1681                pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1682                pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1683                pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1684                pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1685                src = ucode->u.v1.data;
1686                break;
1687        }
1688
1689        /* Verify size of file vs. image size info in file's header */
1690        if (ucode_raw->size != hdr_size + pieces->inst_size +
1691                                pieces->data_size + pieces->init_size +
1692                                pieces->init_data_size + pieces->boot_size) {
1693
1694                IWL_ERR(priv,
1695                        "uCode file size %d does not match expected size\n",
1696                        (int)ucode_raw->size);
1697                return -EINVAL;
1698        }
1699
1700        pieces->inst = src;
1701        src += pieces->inst_size;
1702        pieces->data = src;
1703        src += pieces->data_size;
1704        pieces->init = src;
1705        src += pieces->init_size;
1706        pieces->init_data = src;
1707        src += pieces->init_data_size;
1708        pieces->boot = src;
1709        src += pieces->boot_size;
1710
1711        return 0;
1712}
1713
1714static int iwlagn_wanted_ucode_alternative = 1;
1715
1716static int iwlagn_load_firmware(struct iwl_priv *priv,
1717                                const struct firmware *ucode_raw,
1718                                struct iwlagn_firmware_pieces *pieces,
1719                                struct iwlagn_ucode_capabilities *capa)
1720{
1721        struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1722        struct iwl_ucode_tlv *tlv;
1723        size_t len = ucode_raw->size;
1724        const u8 *data;
1725        int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1726        u64 alternatives;
1727        u32 tlv_len;
1728        enum iwl_ucode_tlv_type tlv_type;
1729        const u8 *tlv_data;
1730
1731        if (len < sizeof(*ucode)) {
1732                IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1733                return -EINVAL;
1734        }
1735
1736        if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1737                IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1738                        le32_to_cpu(ucode->magic));
1739                return -EINVAL;
1740        }
1741
1742        /*
1743         * Check which alternatives are present, and "downgrade"
1744         * when the chosen alternative is not present, warning
1745         * the user when that happens. Some files may not have
1746         * any alternatives, so don't warn in that case.
1747         */
1748        alternatives = le64_to_cpu(ucode->alternatives);
1749        tmp = wanted_alternative;
1750        if (wanted_alternative > 63)
1751                wanted_alternative = 63;
1752        while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1753                wanted_alternative--;
1754        if (wanted_alternative && wanted_alternative != tmp)
1755                IWL_WARN(priv,
1756                         "uCode alternative %d not available, choosing %d\n",
1757                         tmp, wanted_alternative);
1758
1759        priv->ucode_ver = le32_to_cpu(ucode->ver);
1760        pieces->build = le32_to_cpu(ucode->build);
1761        data = ucode->data;
1762
1763        len -= sizeof(*ucode);
1764
1765        while (len >= sizeof(*tlv)) {
1766                u16 tlv_alt;
1767
1768                len -= sizeof(*tlv);
1769                tlv = (void *)data;
1770
1771                tlv_len = le32_to_cpu(tlv->length);
1772                tlv_type = le16_to_cpu(tlv->type);
1773                tlv_alt = le16_to_cpu(tlv->alternative);
1774                tlv_data = tlv->data;
1775
1776                if (len < tlv_len) {
1777                        IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1778                                len, tlv_len);
1779                        return -EINVAL;
1780                }
1781                len -= ALIGN(tlv_len, 4);
1782                data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1783
1784                /*
1785                 * Alternative 0 is always valid.
1786                 *
1787                 * Skip alternative TLVs that are not selected.
1788                 */
1789                if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1790                        continue;
1791
1792                switch (tlv_type) {
1793                case IWL_UCODE_TLV_INST:
1794                        pieces->inst = tlv_data;
1795                        pieces->inst_size = tlv_len;
1796                        break;
1797                case IWL_UCODE_TLV_DATA:
1798                        pieces->data = tlv_data;
1799                        pieces->data_size = tlv_len;
1800                        break;
1801                case IWL_UCODE_TLV_INIT:
1802                        pieces->init = tlv_data;
1803                        pieces->init_size = tlv_len;
1804                        break;
1805                case IWL_UCODE_TLV_INIT_DATA:
1806                        pieces->init_data = tlv_data;
1807                        pieces->init_data_size = tlv_len;
1808                        break;
1809                case IWL_UCODE_TLV_BOOT:
1810                        pieces->boot = tlv_data;
1811                        pieces->boot_size = tlv_len;
1812                        break;
1813                case IWL_UCODE_TLV_PROBE_MAX_LEN:
1814                        if (tlv_len != sizeof(u32))
1815                                goto invalid_tlv_len;
1816                        capa->max_probe_length =
1817                                        le32_to_cpup((__le32 *)tlv_data);
1818                        break;
1819                case IWL_UCODE_TLV_PAN:
1820                        if (tlv_len)
1821                                goto invalid_tlv_len;
1822                        capa->pan = true;
1823                        break;
1824                case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1825                        if (tlv_len != sizeof(u32))
1826                                goto invalid_tlv_len;
1827                        pieces->init_evtlog_ptr =
1828                                        le32_to_cpup((__le32 *)tlv_data);
1829                        break;
1830                case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1831                        if (tlv_len != sizeof(u32))
1832                                goto invalid_tlv_len;
1833                        pieces->init_evtlog_size =
1834                                        le32_to_cpup((__le32 *)tlv_data);
1835                        break;
1836                case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1837                        if (tlv_len != sizeof(u32))
1838                                goto invalid_tlv_len;
1839                        pieces->init_errlog_ptr =
1840                                        le32_to_cpup((__le32 *)tlv_data);
1841                        break;
1842                case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1843                        if (tlv_len != sizeof(u32))
1844                                goto invalid_tlv_len;
1845                        pieces->inst_evtlog_ptr =
1846                                        le32_to_cpup((__le32 *)tlv_data);
1847                        break;
1848                case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1849                        if (tlv_len != sizeof(u32))
1850                                goto invalid_tlv_len;
1851                        pieces->inst_evtlog_size =
1852                                        le32_to_cpup((__le32 *)tlv_data);
1853                        break;
1854                case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1855                        if (tlv_len != sizeof(u32))
1856                                goto invalid_tlv_len;
1857                        pieces->inst_errlog_ptr =
1858                                        le32_to_cpup((__le32 *)tlv_data);
1859                        break;
1860                case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1861                        if (tlv_len)
1862                                goto invalid_tlv_len;
1863                        priv->enhance_sensitivity_table = true;
1864                        break;
1865                case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1866                        if (tlv_len != sizeof(u32))
1867                                goto invalid_tlv_len;
1868                        capa->standard_phy_calibration_size =
1869                                        le32_to_cpup((__le32 *)tlv_data);
1870                        break;
1871                default:
1872                        IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1873                        break;
1874                }
1875        }
1876
1877        if (len) {
1878                IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1879                iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1880                return -EINVAL;
1881        }
1882
1883        return 0;
1884
1885 invalid_tlv_len:
1886        IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1887        iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1888
1889        return -EINVAL;
1890}
1891
1892/**
1893 * iwl_ucode_callback - callback when firmware was loaded
1894 *
1895 * If loaded successfully, copies the firmware into buffers
1896 * for the card to fetch (via DMA).
1897 */
1898static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1899{
1900        struct iwl_priv *priv = context;
1901        struct iwl_ucode_header *ucode;
1902        int err;
1903        struct iwlagn_firmware_pieces pieces;
1904        const unsigned int api_max = priv->cfg->ucode_api_max;
1905        const unsigned int api_min = priv->cfg->ucode_api_min;
1906        u32 api_ver;
1907        char buildstr[25];
1908        u32 build;
1909        struct iwlagn_ucode_capabilities ucode_capa = {
1910                .max_probe_length = 200,
1911                .standard_phy_calibration_size =
1912                        IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1913        };
1914
1915        memset(&pieces, 0, sizeof(pieces));
1916
1917        if (!ucode_raw) {
1918                if (priv->fw_index <= priv->cfg->ucode_api_max)
1919                        IWL_ERR(priv,
1920                                "request for firmware file '%s' failed.\n",
1921                                priv->firmware_name);
1922                goto try_again;
1923        }
1924
1925        IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1926                       priv->firmware_name, ucode_raw->size);
1927
1928        /* Make sure that we got at least the API version number */
1929        if (ucode_raw->size < 4) {
1930                IWL_ERR(priv, "File size way too small!\n");
1931                goto try_again;
1932        }
1933
1934        /* Data from ucode file:  header followed by uCode images */
1935        ucode = (struct iwl_ucode_header *)ucode_raw->data;
1936
1937        if (ucode->ver)
1938                err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1939        else
1940                err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1941                                           &ucode_capa);
1942
1943        if (err)
1944                goto try_again;
1945
1946        api_ver = IWL_UCODE_API(priv->ucode_ver);
1947        build = pieces.build;
1948
1949        /*
1950         * api_ver should match the api version forming part of the
1951         * firmware filename ... but we don't check for that and only rely
1952         * on the API version read from firmware header from here on forward
1953         */
1954        /* no api version check required for experimental uCode */
1955        if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1956                if (api_ver < api_min || api_ver > api_max) {
1957                        IWL_ERR(priv,
1958                                "Driver unable to support your firmware API. "
1959                                "Driver supports v%u, firmware is v%u.\n",
1960                                api_max, api_ver);
1961                        goto try_again;
1962                }
1963
1964                if (api_ver != api_max)
1965                        IWL_ERR(priv,
1966                                "Firmware has old API version. Expected v%u, "
1967                                "got v%u. New firmware can be obtained "
1968                                "from http://www.intellinuxwireless.org.\n",
1969                                api_max, api_ver);
1970        }
1971
1972        if (build)
1973                sprintf(buildstr, " build %u%s", build,
1974                       (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1975                                ? " (EXP)" : "");
1976        else
1977                buildstr[0] = '\0';
1978
1979        IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1980                 IWL_UCODE_MAJOR(priv->ucode_ver),
1981                 IWL_UCODE_MINOR(priv->ucode_ver),
1982                 IWL_UCODE_API(priv->ucode_ver),
1983                 IWL_UCODE_SERIAL(priv->ucode_ver),
1984                 buildstr);
1985
1986        snprintf(priv->hw->wiphy->fw_version,
1987                 sizeof(priv->hw->wiphy->fw_version),
1988                 "%u.%u.%u.%u%s",
1989                 IWL_UCODE_MAJOR(priv->ucode_ver),
1990                 IWL_UCODE_MINOR(priv->ucode_ver),
1991                 IWL_UCODE_API(priv->ucode_ver),
1992                 IWL_UCODE_SERIAL(priv->ucode_ver),
1993                 buildstr);
1994
1995        /*
1996         * For any of the failures below (before allocating pci memory)
1997         * we will try to load a version with a smaller API -- maybe the
1998         * user just got a corrupted version of the latest API.
1999         */
2000
2001        IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2002                       priv->ucode_ver);
2003        IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2004                       pieces.inst_size);
2005        IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2006                       pieces.data_size);
2007        IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2008                       pieces.init_size);
2009        IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2010                       pieces.init_data_size);
2011        IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2012                       pieces.boot_size);
2013
2014        /* Verify that uCode images will fit in card's SRAM */
2015        if (pieces.inst_size > priv->hw_params.max_inst_size) {
2016                IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2017                        pieces.inst_size);
2018                goto try_again;
2019        }
2020
2021        if (pieces.data_size > priv->hw_params.max_data_size) {
2022                IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2023                        pieces.data_size);
2024                goto try_again;
2025        }
2026
2027        if (pieces.init_size > priv->hw_params.max_inst_size) {
2028                IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2029                        pieces.init_size);
2030                goto try_again;
2031        }
2032
2033        if (pieces.init_data_size > priv->hw_params.max_data_size) {
2034                IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2035                        pieces.init_data_size);
2036                goto try_again;
2037        }
2038
2039        if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2040                IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2041                        pieces.boot_size);
2042                goto try_again;
2043        }
2044
2045        /* Allocate ucode buffers for card's bus-master loading ... */
2046
2047        /* Runtime instructions and 2 copies of data:
2048         * 1) unmodified from disk
2049         * 2) backup cache for save/restore during power-downs */
2050        priv->ucode_code.len = pieces.inst_size;
2051        iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2052
2053        priv->ucode_data.len = pieces.data_size;
2054        iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2055
2056        priv->ucode_data_backup.len = pieces.data_size;
2057        iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2058
2059        if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2060            !priv->ucode_data_backup.v_addr)
2061                goto err_pci_alloc;
2062
2063        /* Initialization instructions and data */
2064        if (pieces.init_size && pieces.init_data_size) {
2065                priv->ucode_init.len = pieces.init_size;
2066                iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2067
2068                priv->ucode_init_data.len = pieces.init_data_size;
2069                iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2070
2071                if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2072                        goto err_pci_alloc;
2073        }
2074
2075        /* Bootstrap (instructions only, no data) */
2076        if (pieces.boot_size) {
2077                priv->ucode_boot.len = pieces.boot_size;
2078                iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2079
2080                if (!priv->ucode_boot.v_addr)
2081                        goto err_pci_alloc;
2082        }
2083
2084        /* Now that we can no longer fail, copy information */
2085
2086        /*
2087         * The (size - 16) / 12 formula is based on the information recorded
2088         * for each event, which is of mode 1 (including timestamp) for all
2089         * new microcodes that include this information.
2090         */
2091        priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2092        if (pieces.init_evtlog_size)
2093                priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2094        else
2095                priv->_agn.init_evtlog_size =
2096                        priv->cfg->base_params->max_event_log_size;
2097        priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2098        priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2099        if (pieces.inst_evtlog_size)
2100                priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2101        else
2102                priv->_agn.inst_evtlog_size =
2103                        priv->cfg->base_params->max_event_log_size;
2104        priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2105
2106        if (ucode_capa.pan) {
2107                priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2108                priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2109        } else
2110                priv->sta_key_max_num = STA_KEY_MAX_NUM;
2111
2112        /* Copy images into buffers for card's bus-master reads ... */
2113
2114        /* Runtime instructions (first block of data in file) */
2115        IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2116                        pieces.inst_size);
2117        memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2118
2119        IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2120                priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2121
2122        /*
2123         * Runtime data
2124         * NOTE:  Copy into backup buffer will be done in iwl_up()
2125         */
2126        IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2127                        pieces.data_size);
2128        memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2129        memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2130
2131        /* Initialization instructions */
2132        if (pieces.init_size) {
2133                IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2134                                pieces.init_size);
2135                memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2136        }
2137
2138        /* Initialization data */
2139        if (pieces.init_data_size) {
2140                IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2141                               pieces.init_data_size);
2142                memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2143                       pieces.init_data_size);
2144        }
2145
2146        /* Bootstrap instructions */
2147        IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2148                        pieces.boot_size);
2149        memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2150
2151        /*
2152         * figure out the offset of chain noise reset and gain commands
2153         * base on the size of standard phy calibration commands table size
2154         */
2155        if (ucode_capa.standard_phy_calibration_size >
2156            IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2157                ucode_capa.standard_phy_calibration_size =
2158                        IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2159
2160        priv->_agn.phy_calib_chain_noise_reset_cmd =
2161                ucode_capa.standard_phy_calibration_size;
2162        priv->_agn.phy_calib_chain_noise_gain_cmd =
2163                ucode_capa.standard_phy_calibration_size + 1;
2164
2165        /**************************************************
2166         * This is still part of probe() in a sense...
2167         *
2168         * 9. Setup and register with mac80211 and debugfs
2169         **************************************************/
2170        err = iwl_mac_setup_register(priv, &ucode_capa);
2171        if (err)
2172                goto out_unbind;
2173
2174        err = iwl_dbgfs_register(priv, DRV_NAME);
2175        if (err)
2176                IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2177
2178        err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2179                                        &iwl_attribute_group);
2180        if (err) {
2181                IWL_ERR(priv, "failed to create sysfs device attributes\n");
2182                goto out_unbind;
2183        }
2184
2185        /* We have our copies now, allow OS release its copies */
2186        release_firmware(ucode_raw);
2187        complete(&priv->_agn.firmware_loading_complete);
2188        return;
2189
2190 try_again:
2191        /* try next, if any */
2192        if (iwl_request_firmware(priv, false))
2193                goto out_unbind;
2194        release_firmware(ucode_raw);
2195        return;
2196
2197 err_pci_alloc:
2198        IWL_ERR(priv, "failed to allocate pci memory\n");
2199        iwl_dealloc_ucode_pci(priv);
2200 out_unbind:
2201        complete(&priv->_agn.firmware_loading_complete);
2202        device_release_driver(&priv->pci_dev->dev);
2203        release_firmware(ucode_raw);
2204}
2205
2206static const char *desc_lookup_text[] = {
2207        "OK",
2208        "FAIL",
2209        "BAD_PARAM",
2210        "BAD_CHECKSUM",
2211        "NMI_INTERRUPT_WDG",
2212        "SYSASSERT",
2213        "FATAL_ERROR",
2214        "BAD_COMMAND",
2215        "HW_ERROR_TUNE_LOCK",
2216        "HW_ERROR_TEMPERATURE",
2217        "ILLEGAL_CHAN_FREQ",
2218        "VCC_NOT_STABLE",
2219        "FH_ERROR",
2220        "NMI_INTERRUPT_HOST",
2221        "NMI_INTERRUPT_ACTION_PT",
2222        "NMI_INTERRUPT_UNKNOWN",
2223        "UCODE_VERSION_MISMATCH",
2224        "HW_ERROR_ABS_LOCK",
2225        "HW_ERROR_CAL_LOCK_FAIL",
2226        "NMI_INTERRUPT_INST_ACTION_PT",
2227        "NMI_INTERRUPT_DATA_ACTION_PT",
2228        "NMI_TRM_HW_ER",
2229        "NMI_INTERRUPT_TRM",
2230        "NMI_INTERRUPT_BREAK_POINT"
2231        "DEBUG_0",
2232        "DEBUG_1",
2233        "DEBUG_2",
2234        "DEBUG_3",
2235};
2236
2237static struct { char *name; u8 num; } advanced_lookup[] = {
2238        { "NMI_INTERRUPT_WDG", 0x34 },
2239        { "SYSASSERT", 0x35 },
2240        { "UCODE_VERSION_MISMATCH", 0x37 },
2241        { "BAD_COMMAND", 0x38 },
2242        { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2243        { "FATAL_ERROR", 0x3D },
2244        { "NMI_TRM_HW_ERR", 0x46 },
2245        { "NMI_INTERRUPT_TRM", 0x4C },
2246        { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2247        { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2248        { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2249        { "NMI_INTERRUPT_HOST", 0x66 },
2250        { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2251        { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2252        { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2253        { "ADVANCED_SYSASSERT", 0 },
2254};
2255
2256static const char *desc_lookup(u32 num)
2257{
2258        int i;
2259        int max = ARRAY_SIZE(desc_lookup_text);
2260
2261        if (num < max)
2262                return desc_lookup_text[num];
2263
2264        max = ARRAY_SIZE(advanced_lookup) - 1;
2265        for (i = 0; i < max; i++) {
2266                if (advanced_lookup[i].num == num)
2267                        break;;
2268        }
2269        return advanced_lookup[i].name;
2270}
2271
2272#define ERROR_START_OFFSET  (1 * sizeof(u32))
2273#define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2274
2275void iwl_dump_nic_error_log(struct iwl_priv *priv)
2276{
2277        u32 data2, line;
2278        u32 desc, time, count, base, data1;
2279        u32 blink1, blink2, ilink1, ilink2;
2280        u32 pc, hcmd;
2281
2282        if (priv->ucode_type == UCODE_INIT) {
2283                base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2284                if (!base)
2285                        base = priv->_agn.init_errlog_ptr;
2286        } else {
2287                base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2288                if (!base)
2289                        base = priv->_agn.inst_errlog_ptr;
2290        }
2291
2292        if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2293                IWL_ERR(priv,
2294                        "Not valid error log pointer 0x%08X for %s uCode\n",
2295                        base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2296                return;
2297        }
2298
2299        count = iwl_read_targ_mem(priv, base);
2300
2301        if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2302                IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2303                IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2304                        priv->status, count);
2305        }
2306
2307        desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2308        priv->isr_stats.err_code = desc;
2309        pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2310        blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2311        blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2312        ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2313        ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2314        data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2315        data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2316        line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2317        time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2318        hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2319
2320        trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2321                                      blink1, blink2, ilink1, ilink2);
2322
2323        IWL_ERR(priv, "Desc                                  Time       "
2324                "data1      data2      line\n");
2325        IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2326                desc_lookup(desc), desc, time, data1, data2, line);
2327        IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2328        IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2329                pc, blink1, blink2, ilink1, ilink2, hcmd);
2330}
2331
2332#define EVENT_START_OFFSET  (4 * sizeof(u32))
2333
2334/**
2335 * iwl_print_event_log - Dump error event log to syslog
2336 *
2337 */
2338static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2339                               u32 num_events, u32 mode,
2340                               int pos, char **buf, size_t bufsz)
2341{
2342        u32 i;
2343        u32 base;       /* SRAM byte address of event log header */
2344        u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2345        u32 ptr;        /* SRAM byte address of log data */
2346        u32 ev, time, data; /* event log data */
2347        unsigned long reg_flags;
2348
2349        if (num_events == 0)
2350                return pos;
2351
2352        if (priv->ucode_type == UCODE_INIT) {
2353                base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2354                if (!base)
2355                        base = priv->_agn.init_evtlog_ptr;
2356        } else {
2357                base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2358                if (!base)
2359                        base = priv->_agn.inst_evtlog_ptr;
2360        }
2361
2362        if (mode == 0)
2363                event_size = 2 * sizeof(u32);
2364        else
2365                event_size = 3 * sizeof(u32);
2366
2367        ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2368
2369        /* Make sure device is powered up for SRAM reads */
2370        spin_lock_irqsave(&priv->reg_lock, reg_flags);
2371        iwl_grab_nic_access(priv);
2372
2373        /* Set starting address; reads will auto-increment */
2374        _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2375        rmb();
2376
2377        /* "time" is actually "data" for mode 0 (no timestamp).
2378        * place event id # at far right for easier visual parsing. */
2379        for (i = 0; i < num_events; i++) {
2380                ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2381                time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2382                if (mode == 0) {
2383                        /* data, ev */
2384                        if (bufsz) {
2385                                pos += scnprintf(*buf + pos, bufsz - pos,
2386                                                "EVT_LOG:0x%08x:%04u\n",
2387                                                time, ev);
2388                        } else {
2389                                trace_iwlwifi_dev_ucode_event(priv, 0,
2390                                        time, ev);
2391                                IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2392                                        time, ev);
2393                        }
2394                } else {
2395                        data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2396                        if (bufsz) {
2397                                pos += scnprintf(*buf + pos, bufsz - pos,
2398                                                "EVT_LOGT:%010u:0x%08x:%04u\n",
2399                                                 time, data, ev);
2400                        } else {
2401                                IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2402                                        time, data, ev);
2403                                trace_iwlwifi_dev_ucode_event(priv, time,
2404                                        data, ev);
2405                        }
2406                }
2407        }
2408
2409        /* Allow device to power down */
2410        iwl_release_nic_access(priv);
2411        spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2412        return pos;
2413}
2414
2415/**
2416 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2417 */
2418static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2419                                    u32 num_wraps, u32 next_entry,
2420                                    u32 size, u32 mode,
2421                                    int pos, char **buf, size_t bufsz)
2422{
2423        /*
2424         * display the newest DEFAULT_LOG_ENTRIES entries
2425         * i.e the entries just before the next ont that uCode would fill.
2426         */
2427        if (num_wraps) {
2428                if (next_entry < size) {
2429                        pos = iwl_print_event_log(priv,
2430                                                capacity - (size - next_entry),
2431                                                size - next_entry, mode,
2432                                                pos, buf, bufsz);
2433                        pos = iwl_print_event_log(priv, 0,
2434                                                  next_entry, mode,
2435                                                  pos, buf, bufsz);
2436                } else
2437                        pos = iwl_print_event_log(priv, next_entry - size,
2438                                                  size, mode, pos, buf, bufsz);
2439        } else {
2440                if (next_entry < size) {
2441                        pos = iwl_print_event_log(priv, 0, next_entry,
2442                                                  mode, pos, buf, bufsz);
2443                } else {
2444                        pos = iwl_print_event_log(priv, next_entry - size,
2445                                                  size, mode, pos, buf, bufsz);
2446                }
2447        }
2448        return pos;
2449}
2450
2451#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2452
2453int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2454                            char **buf, bool display)
2455{
2456        u32 base;       /* SRAM byte address of event log header */
2457        u32 capacity;   /* event log capacity in # entries */
2458        u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2459        u32 num_wraps;  /* # times uCode wrapped to top of log */
2460        u32 next_entry; /* index of next entry to be written by uCode */
2461        u32 size;       /* # entries that we'll print */
2462        u32 logsize;
2463        int pos = 0;
2464        size_t bufsz = 0;
2465
2466        if (priv->ucode_type == UCODE_INIT) {
2467                base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2468                logsize = priv->_agn.init_evtlog_size;
2469                if (!base)
2470                        base = priv->_agn.init_evtlog_ptr;
2471        } else {
2472                base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2473                logsize = priv->_agn.inst_evtlog_size;
2474                if (!base)
2475                        base = priv->_agn.inst_evtlog_ptr;
2476        }
2477
2478        if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2479                IWL_ERR(priv,
2480                        "Invalid event log pointer 0x%08X for %s uCode\n",
2481                        base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2482                return -EINVAL;
2483        }
2484
2485        /* event log header */
2486        capacity = iwl_read_targ_mem(priv, base);
2487        mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2488        num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2489        next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2490
2491        if (capacity > logsize) {
2492                IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2493                        capacity, logsize);
2494                capacity = logsize;
2495        }
2496
2497        if (next_entry > logsize) {
2498                IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2499                        next_entry, logsize);
2500                next_entry = logsize;
2501        }
2502
2503        size = num_wraps ? capacity : next_entry;
2504
2505        /* bail out if nothing in log */
2506        if (size == 0) {
2507                IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2508                return pos;
2509        }
2510
2511        /* enable/disable bt channel inhibition */
2512        priv->bt_ch_announce = iwlagn_bt_ch_announce;
2513
2514#ifdef CONFIG_IWLWIFI_DEBUG
2515        if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2516                size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2517                        ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2518#else
2519        size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2520                ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2521#endif
2522        IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2523                size);
2524
2525#ifdef CONFIG_IWLWIFI_DEBUG
2526        if (display) {
2527                if (full_log)
2528                        bufsz = capacity * 48;
2529                else
2530                        bufsz = size * 48;
2531                *buf = kmalloc(bufsz, GFP_KERNEL);
2532                if (!*buf)
2533                        return -ENOMEM;
2534        }
2535        if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2536                /*
2537                 * if uCode has wrapped back to top of log,
2538                 * start at the oldest entry,
2539                 * i.e the next one that uCode would fill.
2540                 */
2541                if (num_wraps)
2542                        pos = iwl_print_event_log(priv, next_entry,
2543                                                capacity - next_entry, mode,
2544                                                pos, buf, bufsz);
2545                /* (then/else) start at top of log */
2546                pos = iwl_print_event_log(priv, 0,
2547                                          next_entry, mode, pos, buf, bufsz);
2548        } else
2549                pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2550                                                next_entry, size, mode,
2551                                                pos, buf, bufsz);
2552#else
2553        pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2554                                        next_entry, size, mode,
2555                                        pos, buf, bufsz);
2556#endif
2557        return pos;
2558}
2559
2560static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2561{
2562        struct iwl_ct_kill_config cmd;
2563        struct iwl_ct_kill_throttling_config adv_cmd;
2564        unsigned long flags;
2565        int ret = 0;
2566
2567        spin_lock_irqsave(&priv->lock, flags);
2568        iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2569                    CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2570        spin_unlock_irqrestore(&priv->lock, flags);
2571        priv->thermal_throttle.ct_kill_toggle = false;
2572
2573        if (priv->cfg->base_params->support_ct_kill_exit) {
2574                adv_cmd.critical_temperature_enter =
2575                        cpu_to_le32(priv->hw_params.ct_kill_threshold);
2576                adv_cmd.critical_temperature_exit =
2577                        cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2578
2579                ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2580                                       sizeof(adv_cmd), &adv_cmd);
2581                if (ret)
2582                        IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2583                else
2584                        IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2585                                        "succeeded, "
2586                                        "critical temperature enter is %d,"
2587                                        "exit is %d\n",
2588                                       priv->hw_params.ct_kill_threshold,
2589                                       priv->hw_params.ct_kill_exit_threshold);
2590        } else {
2591                cmd.critical_temperature_R =
2592                        cpu_to_le32(priv->hw_params.ct_kill_threshold);
2593
2594                ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2595                                       sizeof(cmd), &cmd);
2596                if (ret)
2597                        IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2598                else
2599                        IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2600                                        "succeeded, "
2601                                        "critical temperature is %d\n",
2602                                        priv->hw_params.ct_kill_threshold);
2603        }
2604}
2605
2606static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2607{
2608        struct iwl_calib_cfg_cmd calib_cfg_cmd;
2609        struct iwl_host_cmd cmd = {
2610                .id = CALIBRATION_CFG_CMD,
2611                .len = sizeof(struct iwl_calib_cfg_cmd),
2612                .data = &calib_cfg_cmd,
2613        };
2614
2615        memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2616        calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2617        calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2618
2619        return iwl_send_cmd(priv, &cmd);
2620}
2621
2622
2623/**
2624 * iwl_alive_start - called after REPLY_ALIVE notification received
2625 *                   from protocol/runtime uCode (initialization uCode's
2626 *                   Alive gets handled by iwl_init_alive_start()).
2627 */
2628static void iwl_alive_start(struct iwl_priv *priv)
2629{
2630        int ret = 0;
2631        struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2632
2633        IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2634
2635        if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2636                /* We had an error bringing up the hardware, so take it
2637                 * all the way back down so we can try again */
2638                IWL_DEBUG_INFO(priv, "Alive failed.\n");
2639                goto restart;
2640        }
2641
2642        /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2643         * This is a paranoid check, because we would not have gotten the
2644         * "runtime" alive if code weren't properly loaded.  */
2645        if (iwl_verify_ucode(priv)) {
2646                /* Runtime instruction load was bad;
2647                 * take it all the way back down so we can try again */
2648                IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2649                goto restart;
2650        }
2651
2652        ret = priv->cfg->ops->lib->alive_notify(priv);
2653        if (ret) {
2654                IWL_WARN(priv,
2655                        "Could not complete ALIVE transition [ntf]: %d\n", ret);
2656                goto restart;
2657        }
2658
2659
2660        /* After the ALIVE response, we can send host commands to the uCode */
2661        set_bit(STATUS_ALIVE, &priv->status);
2662
2663        /* Enable watchdog to monitor the driver tx queues */
2664        iwl_setup_watchdog(priv);
2665
2666        if (iwl_is_rfkill(priv))
2667                return;
2668
2669        /* download priority table before any calibration request */
2670        if (priv->cfg->bt_params &&
2671            priv->cfg->bt_params->advanced_bt_coexist) {
2672                /* Configure Bluetooth device coexistence support */
2673                priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2674                priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2675                priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2676                priv->cfg->ops->hcmd->send_bt_config(priv);
2677                priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2678                iwlagn_send_prio_tbl(priv);
2679
2680                /* FIXME: w/a to force change uCode BT state machine */
2681                iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2682                        BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2683                iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2684                        BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2685        }
2686        if (priv->hw_params.calib_rt_cfg)
2687                iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2688
2689        ieee80211_wake_queues(priv->hw);
2690
2691        priv->active_rate = IWL_RATES_MASK;
2692
2693        /* Configure Tx antenna selection based on H/W config */
2694        if (priv->cfg->ops->hcmd->set_tx_ant)
2695                priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2696
2697        if (iwl_is_associated_ctx(ctx)) {
2698                struct iwl_rxon_cmd *active_rxon =
2699                                (struct iwl_rxon_cmd *)&ctx->active;
2700                /* apply any changes in staging */
2701                ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2702                active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2703        } else {
2704                struct iwl_rxon_context *tmp;
2705                /* Initialize our rx_config data */
2706                for_each_context(priv, tmp)
2707                        iwl_connection_init_rx_config(priv, tmp);
2708
2709                if (priv->cfg->ops->hcmd->set_rxon_chain)
2710                        priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2711        }
2712
2713        if (priv->cfg->bt_params &&
2714            !priv->cfg->bt_params->advanced_bt_coexist) {
2715                /* Configure Bluetooth device coexistence support */
2716                priv->cfg->ops->hcmd->send_bt_config(priv);
2717        }
2718
2719        iwl_reset_run_time_calib(priv);
2720
2721        set_bit(STATUS_READY, &priv->status);
2722
2723        /* Configure the adapter for unassociated operation */
2724        iwlcore_commit_rxon(priv, ctx);
2725
2726        /* At this point, the NIC is initialized and operational */
2727        iwl_rf_kill_ct_config(priv);
2728
2729        iwl_leds_init(priv);
2730
2731        IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2732        wake_up_interruptible(&priv->wait_command_queue);
2733
2734        iwl_power_update_mode(priv, true);
2735        IWL_DEBUG_INFO(priv, "Updated power mode\n");
2736
2737
2738        return;
2739
2740 restart:
2741        queue_work(priv->workqueue, &priv->restart);
2742}
2743
2744static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2745
2746static void __iwl_down(struct iwl_priv *priv)
2747{
2748        unsigned long flags;
2749        int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2750
2751        IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2752
2753        iwl_scan_cancel_timeout(priv, 200);
2754
2755        exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2756
2757        /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2758         * to prevent rearm timer */
2759        del_timer_sync(&priv->watchdog);
2760
2761        iwl_clear_ucode_stations(priv, NULL);
2762        iwl_dealloc_bcast_stations(priv);
2763        iwl_clear_driver_stations(priv);
2764
2765        /* reset BT coex data */
2766        priv->bt_status = 0;
2767        if (priv->cfg->bt_params)
2768                priv->bt_traffic_load =
2769                         priv->cfg->bt_params->bt_init_traffic_load;
2770        else
2771                priv->bt_traffic_load = 0;
2772        priv->bt_sco_active = false;
2773        priv->bt_full_concurrent = false;
2774        priv->bt_ci_compliance = 0;
2775
2776        /* Unblock any waiting calls */
2777        wake_up_interruptible_all(&priv->wait_command_queue);
2778
2779        /* Wipe out the EXIT_PENDING status bit if we are not actually
2780         * exiting the module */
2781        if (!exit_pending)
2782                clear_bit(STATUS_EXIT_PENDING, &priv->status);
2783
2784        /* stop and reset the on-board processor */
2785        iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2786
2787        /* tell the device to stop sending interrupts */
2788        spin_lock_irqsave(&priv->lock, flags);
2789        iwl_disable_interrupts(priv);
2790        spin_unlock_irqrestore(&priv->lock, flags);
2791        iwl_synchronize_irq(priv);
2792
2793        if (priv->mac80211_registered)
2794                ieee80211_stop_queues(priv->hw);
2795
2796        /* If we have not previously called iwl_init() then
2797         * clear all bits but the RF Kill bit and return */
2798        if (!iwl_is_init(priv)) {
2799                priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2800                                        STATUS_RF_KILL_HW |
2801                               test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2802                                        STATUS_GEO_CONFIGURED |
2803                               test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2804                                        STATUS_EXIT_PENDING;
2805                goto exit;
2806        }
2807
2808        /* ...otherwise clear out all the status bits but the RF Kill
2809         * bit and continue taking the NIC down. */
2810        priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2811                                STATUS_RF_KILL_HW |
2812                        test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2813                                STATUS_GEO_CONFIGURED |
2814                        test_bit(STATUS_FW_ERROR, &priv->status) <<
2815                                STATUS_FW_ERROR |
2816                       test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2817                                STATUS_EXIT_PENDING;
2818
2819        /* device going down, Stop using ICT table */
2820        if (priv->cfg->ops->lib->isr_ops.disable)
2821                priv->cfg->ops->lib->isr_ops.disable(priv);
2822
2823        iwlagn_txq_ctx_stop(priv);
2824        iwlagn_rxq_stop(priv);
2825
2826        /* Power-down device's busmaster DMA clocks */
2827        iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2828        udelay(5);
2829
2830        /* Make sure (redundant) we've released our request to stay awake */
2831        iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2832
2833        /* Stop the device, and put it in low power state */
2834        iwl_apm_stop(priv);
2835
2836 exit:
2837        memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2838
2839        dev_kfree_skb(priv->beacon_skb);
2840        priv->beacon_skb = NULL;
2841
2842        /* clear out any free frames */
2843        iwl_clear_free_frames(priv);
2844}
2845
2846static void iwl_down(struct iwl_priv *priv)
2847{
2848        mutex_lock(&priv->mutex);
2849        __iwl_down(priv);
2850        mutex_unlock(&priv->mutex);
2851
2852        iwl_cancel_deferred_work(priv);
2853}
2854
2855#define HW_READY_TIMEOUT (50)
2856
2857static int iwl_set_hw_ready(struct iwl_priv *priv)
2858{
2859        int ret = 0;
2860
2861        iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2862                CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2863
2864        /* See if we got it */
2865        ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2866                                CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2867                                CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2868                                HW_READY_TIMEOUT);
2869        if (ret != -ETIMEDOUT)
2870                priv->hw_ready = true;
2871        else
2872                priv->hw_ready = false;
2873
2874        IWL_DEBUG_INFO(priv, "hardware %s\n",
2875                      (priv->hw_ready == 1) ? "ready" : "not ready");
2876        return ret;
2877}
2878
2879static int iwl_prepare_card_hw(struct iwl_priv *priv)
2880{
2881        int ret = 0;
2882
2883        IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2884
2885        ret = iwl_set_hw_ready(priv);
2886        if (priv->hw_ready)
2887                return ret;
2888
2889        /* If HW is not ready, prepare the conditions to check again */
2890        iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2891                        CSR_HW_IF_CONFIG_REG_PREPARE);
2892
2893        ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2894                        ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2895                        CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2896
2897        /* HW should be ready by now, check again. */
2898        if (ret != -ETIMEDOUT)
2899                iwl_set_hw_ready(priv);
2900
2901        return ret;
2902}
2903
2904#define MAX_HW_RESTARTS 5
2905
2906static int __iwl_up(struct iwl_priv *priv)
2907{
2908        struct iwl_rxon_context *ctx;
2909        int i;
2910        int ret;
2911
2912        if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2913                IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2914                return -EIO;
2915        }
2916
2917        if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2918                IWL_ERR(priv, "ucode not available for device bringup\n");
2919                return -EIO;
2920        }
2921
2922        for_each_context(priv, ctx) {
2923                ret = iwlagn_alloc_bcast_station(priv, ctx);
2924                if (ret) {
2925                        iwl_dealloc_bcast_stations(priv);
2926                        return ret;
2927                }
2928        }
2929
2930        iwl_prepare_card_hw(priv);
2931
2932        if (!priv->hw_ready) {
2933                IWL_WARN(priv, "Exit HW not ready\n");
2934                return -EIO;
2935        }
2936
2937        /* If platform's RF_KILL switch is NOT set to KILL */
2938        if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2939                clear_bit(STATUS_RF_KILL_HW, &priv->status);
2940        else
2941                set_bit(STATUS_RF_KILL_HW, &priv->status);
2942
2943        if (iwl_is_rfkill(priv)) {
2944                wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2945
2946                iwl_enable_interrupts(priv);
2947                IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2948                return 0;
2949        }
2950
2951        iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2952
2953        /* must be initialised before iwl_hw_nic_init */
2954        if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2955                priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2956        else
2957                priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2958
2959        ret = iwlagn_hw_nic_init(priv);
2960        if (ret) {
2961                IWL_ERR(priv, "Unable to init nic\n");
2962                return ret;
2963        }
2964
2965        /* make sure rfkill handshake bits are cleared */
2966        iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2967        iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2968                    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2969
2970        /* clear (again), then enable host interrupts */
2971        iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2972        iwl_enable_interrupts(priv);
2973
2974        /* really make sure rfkill handshake bits are cleared */
2975        iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2976        iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2977
2978        /* Copy original ucode data image from disk into backup cache.
2979         * This will be used to initialize the on-board processor's
2980         * data SRAM for a clean start when the runtime program first loads. */
2981        memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2982               priv->ucode_data.len);
2983
2984        for (i = 0; i < MAX_HW_RESTARTS; i++) {
2985
2986                /* load bootstrap state machine,
2987                 * load bootstrap program into processor's memory,
2988                 * prepare to load the "initialize" uCode */
2989                ret = priv->cfg->ops->lib->load_ucode(priv);
2990
2991                if (ret) {
2992                        IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2993                                ret);
2994                        continue;
2995                }
2996
2997                /* start card; "initialize" will load runtime ucode */
2998                iwl_nic_start(priv);
2999
3000                IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3001
3002                return 0;
3003        }
3004
3005        set_bit(STATUS_EXIT_PENDING, &priv->status);
3006        __iwl_down(priv);
3007        clear_bit(STATUS_EXIT_PENDING, &priv->status);
3008
3009        /* tried to restart and config the device for as long as our
3010         * patience could withstand */
3011        IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3012        return -EIO;
3013}
3014
3015
3016/*****************************************************************************
3017 *
3018 * Workqueue callbacks
3019 *
3020 *****************************************************************************/
3021
3022static void iwl_bg_init_alive_start(struct work_struct *data)
3023{
3024        struct iwl_priv *priv =
3025            container_of(data, struct iwl_priv, init_alive_start.work);
3026
3027        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3028                return;
3029
3030        mutex_lock(&priv->mutex);
3031        priv->cfg->ops->lib->init_alive_start(priv);
3032        mutex_unlock(&priv->mutex);
3033}
3034
3035static void iwl_bg_alive_start(struct work_struct *data)
3036{
3037        struct iwl_priv *priv =
3038            container_of(data, struct iwl_priv, alive_start.work);
3039
3040        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3041                return;
3042
3043        /* enable dram interrupt */
3044        if (priv->cfg->ops->lib->isr_ops.reset)
3045                priv->cfg->ops->lib->isr_ops.reset(priv);
3046
3047        mutex_lock(&priv->mutex);
3048        iwl_alive_start(priv);
3049        mutex_unlock(&priv->mutex);
3050}
3051
3052static void iwl_bg_run_time_calib_work(struct work_struct *work)
3053{
3054        struct iwl_priv *priv = container_of(work, struct iwl_priv,
3055                        run_time_calib_work);
3056
3057        mutex_lock(&priv->mutex);
3058
3059        if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3060            test_bit(STATUS_SCANNING, &priv->status)) {
3061                mutex_unlock(&priv->mutex);
3062                return;
3063        }
3064
3065        if (priv->start_calib) {
3066                if (priv->cfg->bt_params &&
3067                    priv->cfg->bt_params->bt_statistics) {
3068                        iwl_chain_noise_calibration(priv,
3069                                        (void *)&priv->_agn.statistics_bt);
3070                        iwl_sensitivity_calibration(priv,
3071                                        (void *)&priv->_agn.statistics_bt);
3072                } else {
3073                        iwl_chain_noise_calibration(priv,
3074                                        (void *)&priv->_agn.statistics);
3075                        iwl_sensitivity_calibration(priv,
3076                                        (void *)&priv->_agn.statistics);
3077                }
3078        }
3079
3080        mutex_unlock(&priv->mutex);
3081}
3082
3083static void iwl_bg_restart(struct work_struct *data)
3084{
3085        struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3086
3087        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3088                return;
3089
3090        if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3091                struct iwl_rxon_context *ctx;
3092                bool bt_sco, bt_full_concurrent;
3093                u8 bt_ci_compliance;
3094                u8 bt_load;
3095                u8 bt_status;
3096
3097                mutex_lock(&priv->mutex);
3098                for_each_context(priv, ctx)
3099                        ctx->vif = NULL;
3100                priv->is_open = 0;
3101
3102                /*
3103                 * __iwl_down() will clear the BT status variables,
3104                 * which is correct, but when we restart we really
3105                 * want to keep them so restore them afterwards.
3106                 *
3107                 * The restart process will later pick them up and
3108                 * re-configure the hw when we reconfigure the BT
3109                 * command.
3110                 */
3111                bt_sco = priv->bt_sco_active;
3112                bt_full_concurrent = priv->bt_full_concurrent;
3113                bt_ci_compliance = priv->bt_ci_compliance;
3114                bt_load = priv->bt_traffic_load;
3115                bt_status = priv->bt_status;
3116
3117                __iwl_down(priv);
3118
3119                priv->bt_sco_active = bt_sco;
3120                priv->bt_full_concurrent = bt_full_concurrent;
3121                priv->bt_ci_compliance = bt_ci_compliance;
3122                priv->bt_traffic_load = bt_load;
3123                priv->bt_status = bt_status;
3124
3125                mutex_unlock(&priv->mutex);
3126                iwl_cancel_deferred_work(priv);
3127                ieee80211_restart_hw(priv->hw);
3128        } else {
3129                iwl_down(priv);
3130
3131                if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3132                        return;
3133
3134                mutex_lock(&priv->mutex);
3135                __iwl_up(priv);
3136                mutex_unlock(&priv->mutex);
3137        }
3138}
3139
3140static void iwl_bg_rx_replenish(struct work_struct *data)
3141{
3142        struct iwl_priv *priv =
3143            container_of(data, struct iwl_priv, rx_replenish);
3144
3145        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3146                return;
3147
3148        mutex_lock(&priv->mutex);
3149        iwlagn_rx_replenish(priv);
3150        mutex_unlock(&priv->mutex);
3151}
3152
3153/*****************************************************************************
3154 *
3155 * mac80211 entry point functions
3156 *
3157 *****************************************************************************/
3158
3159#define UCODE_READY_TIMEOUT     (4 * HZ)
3160
3161/*
3162 * Not a mac80211 entry point function, but it fits in with all the
3163 * other mac80211 functions grouped here.
3164 */
3165static int iwl_mac_setup_register(struct iwl_priv *priv,
3166                                  struct iwlagn_ucode_capabilities *capa)
3167{
3168        int ret;
3169        struct ieee80211_hw *hw = priv->hw;
3170        struct iwl_rxon_context *ctx;
3171
3172        hw->rate_control_algorithm = "iwl-agn-rs";
3173
3174        /* Tell mac80211 our characteristics */
3175        hw->flags = IEEE80211_HW_SIGNAL_DBM |
3176                    IEEE80211_HW_AMPDU_AGGREGATION |
3177                    IEEE80211_HW_NEED_DTIM_PERIOD |
3178                    IEEE80211_HW_SPECTRUM_MGMT |
3179                    IEEE80211_HW_REPORTS_TX_ACK_STATUS;
3180
3181        if (!priv->cfg->base_params->broken_powersave)
3182                hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3183                             IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3184
3185        if (priv->cfg->sku & IWL_SKU_N)
3186                hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3187                             IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3188
3189        hw->sta_data_size = sizeof(struct iwl_station_priv);
3190        hw->vif_data_size = sizeof(struct iwl_vif_priv);
3191
3192        for_each_context(priv, ctx) {
3193                hw->wiphy->interface_modes |= ctx->interface_modes;
3194                hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3195        }
3196
3197        hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3198                            WIPHY_FLAG_DISABLE_BEACON_HINTS;
3199
3200        /*
3201         * For now, disable PS by default because it affects
3202         * RX performance significantly.
3203         */
3204        hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3205
3206        hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3207        /* we create the 802.11 header and a zero-length SSID element */
3208        hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3209
3210        /* Default value; 4 EDCA QOS priorities */
3211        hw->queues = 4;
3212
3213        hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3214
3215        if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3216                priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3217                        &priv->bands[IEEE80211_BAND_2GHZ];
3218        if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3219                priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3220                        &priv->bands[IEEE80211_BAND_5GHZ];
3221
3222        ret = ieee80211_register_hw(priv->hw);
3223        if (ret) {
3224                IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3225                return ret;
3226        }
3227        priv->mac80211_registered = 1;
3228
3229        return 0;
3230}
3231
3232
3233int iwlagn_mac_start(struct ieee80211_hw *hw)
3234{
3235        struct iwl_priv *priv = hw->priv;
3236        int ret;
3237
3238        IWL_DEBUG_MAC80211(priv, "enter\n");
3239
3240        /* we should be verifying the device is ready to be opened */
3241        mutex_lock(&priv->mutex);
3242        ret = __iwl_up(priv);
3243        mutex_unlock(&priv->mutex);
3244
3245        if (ret)
3246                return ret;
3247
3248        if (iwl_is_rfkill(priv))
3249                goto out;
3250
3251        IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3252
3253        /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3254         * mac80211 will not be run successfully. */
3255        ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3256                        test_bit(STATUS_READY, &priv->status),
3257                        UCODE_READY_TIMEOUT);
3258        if (!ret) {
3259                if (!test_bit(STATUS_READY, &priv->status)) {
3260                        IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3261                                jiffies_to_msecs(UCODE_READY_TIMEOUT));
3262                        return -ETIMEDOUT;
3263                }
3264        }
3265
3266        iwl_led_start(priv);
3267
3268out:
3269        priv->is_open = 1;
3270        IWL_DEBUG_MAC80211(priv, "leave\n");
3271        return 0;
3272}
3273
3274void iwlagn_mac_stop(struct ieee80211_hw *hw)
3275{
3276        struct iwl_priv *priv = hw->priv;
3277
3278        IWL_DEBUG_MAC80211(priv, "enter\n");
3279
3280        if (!priv->is_open)
3281                return;
3282
3283        priv->is_open = 0;
3284
3285        iwl_down(priv);
3286
3287        flush_workqueue(priv->workqueue);
3288
3289        /* User space software may expect getting rfkill changes
3290         * even if interface is down */
3291        iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3292        iwl_enable_rfkill_int(priv);
3293
3294        IWL_DEBUG_MAC80211(priv, "leave\n");
3295}
3296
3297int iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3298{
3299        struct iwl_priv *priv = hw->priv;
3300
3301        IWL_DEBUG_MACDUMP(priv, "enter\n");
3302
3303        IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3304                     ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3305
3306        if (iwlagn_tx_skb(priv, skb))
3307                dev_kfree_skb_any(skb);
3308
3309        IWL_DEBUG_MACDUMP(priv, "leave\n");
3310        return NETDEV_TX_OK;
3311}
3312
3313void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3314                                struct ieee80211_vif *vif,
3315                                struct ieee80211_key_conf *keyconf,
3316                                struct ieee80211_sta *sta,
3317                                u32 iv32, u16 *phase1key)
3318{
3319        struct iwl_priv *priv = hw->priv;
3320        struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3321
3322        IWL_DEBUG_MAC80211(priv, "enter\n");
3323
3324        iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3325                            iv32, phase1key);
3326
3327        IWL_DEBUG_MAC80211(priv, "leave\n");
3328}
3329
3330int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3331                       struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3332                       struct ieee80211_key_conf *key)
3333{
3334        struct iwl_priv *priv = hw->priv;
3335        struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3336        struct iwl_rxon_context *ctx = vif_priv->ctx;
3337        int ret;
3338        u8 sta_id;
3339        bool is_default_wep_key = false;
3340
3341        IWL_DEBUG_MAC80211(priv, "enter\n");
3342
3343        if (priv->cfg->mod_params->sw_crypto) {
3344                IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3345                return -EOPNOTSUPP;
3346        }
3347
3348        sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3349        if (sta_id == IWL_INVALID_STATION)
3350                return -EINVAL;
3351
3352        mutex_lock(&priv->mutex);
3353        iwl_scan_cancel_timeout(priv, 100);
3354
3355        /*
3356         * If we are getting WEP group key and we didn't receive any key mapping
3357         * so far, we are in legacy wep mode (group key only), otherwise we are
3358         * in 1X mode.
3359         * In legacy wep mode, we use another host command to the uCode.
3360         */
3361        if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3362             key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3363            !sta) {
3364                if (cmd == SET_KEY)
3365                        is_default_wep_key = !ctx->key_mapping_keys;
3366                else
3367                        is_default_wep_key =
3368                                        (key->hw_key_idx == HW_KEY_DEFAULT);
3369        }
3370
3371        switch (cmd) {
3372        case SET_KEY:
3373                if (is_default_wep_key)
3374                        ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3375                else
3376                        ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3377                                                  key, sta_id);
3378
3379                IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3380                break;
3381        case DISABLE_KEY:
3382                if (is_default_wep_key)
3383                        ret = iwl_remove_default_wep_key(priv, ctx, key);
3384                else
3385                        ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3386
3387                IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3388                break;
3389        default:
3390                ret = -EINVAL;
3391        }
3392
3393        mutex_unlock(&priv->mutex);
3394        IWL_DEBUG_MAC80211(priv, "leave\n");
3395
3396        return ret;
3397}
3398
3399int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3400                            struct ieee80211_vif *vif,
3401                            enum ieee80211_ampdu_mlme_action action,
3402                            struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3403{
3404        struct iwl_priv *priv = hw->priv;
3405        int ret = -EINVAL;
3406
3407        IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3408                     sta->addr, tid);
3409
3410        if (!(priv->cfg->sku & IWL_SKU_N))
3411                return -EACCES;
3412
3413        mutex_lock(&priv->mutex);
3414
3415        switch (action) {
3416        case IEEE80211_AMPDU_RX_START:
3417                IWL_DEBUG_HT(priv, "start Rx\n");
3418                ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3419                break;
3420        case IEEE80211_AMPDU_RX_STOP:
3421                IWL_DEBUG_HT(priv, "stop Rx\n");
3422                ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3423                if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3424                        ret = 0;
3425                break;
3426        case IEEE80211_AMPDU_TX_START:
3427                IWL_DEBUG_HT(priv, "start Tx\n");
3428                ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3429                if (ret == 0) {
3430                        priv->_agn.agg_tids_count++;
3431                        IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3432                                     priv->_agn.agg_tids_count);
3433                }
3434                break;
3435        case IEEE80211_AMPDU_TX_STOP:
3436                IWL_DEBUG_HT(priv, "stop Tx\n");
3437                ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3438                if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3439                        priv->_agn.agg_tids_count--;
3440                        IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3441                                     priv->_agn.agg_tids_count);
3442                }
3443                if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3444                        ret = 0;
3445                if (priv->cfg->ht_params &&
3446                    priv->cfg->ht_params->use_rts_for_aggregation) {
3447                        struct iwl_station_priv *sta_priv =
3448                                (void *) sta->drv_priv;
3449                        /*
3450                         * switch off RTS/CTS if it was previously enabled
3451                         */
3452
3453                        sta_priv->lq_sta.lq.general_params.flags &=
3454                                ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3455                        iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3456                                        &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3457                }
3458                break;
3459        case IEEE80211_AMPDU_TX_OPERATIONAL:
3460                if (priv->cfg->ht_params &&
3461                    priv->cfg->ht_params->use_rts_for_aggregation) {
3462                        struct iwl_station_priv *sta_priv =
3463                                (void *) sta->drv_priv;
3464
3465                        /*
3466                         * switch to RTS/CTS if it is the prefer protection
3467                         * method for HT traffic
3468                         */
3469
3470                        sta_priv->lq_sta.lq.general_params.flags |=
3471                                LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3472                        iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3473                                        &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3474                }
3475                ret = 0;
3476                break;
3477        }
3478        mutex_unlock(&priv->mutex);
3479
3480        return ret;
3481}
3482
3483int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3484                       struct ieee80211_vif *vif,
3485                       struct ieee80211_sta *sta)
3486{
3487        struct iwl_priv *priv = hw->priv;
3488        struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3489        struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3490        bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3491        int ret;
3492        u8 sta_id;
3493
3494        IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3495                        sta->addr);
3496        mutex_lock(&priv->mutex);
3497        IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3498                        sta->addr);
3499        sta_priv->common.sta_id = IWL_INVALID_STATION;
3500
3501        atomic_set(&sta_priv->pending_frames, 0);
3502        if (vif->type == NL80211_IFTYPE_AP)
3503                sta_priv->client = true;
3504
3505        ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3506                                     is_ap, sta, &sta_id);
3507        if (ret) {
3508                IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3509                        sta->addr, ret);
3510                /* Should we return success if return code is EEXIST ? */
3511                mutex_unlock(&priv->mutex);
3512                return ret;
3513        }
3514
3515        sta_priv->common.sta_id = sta_id;
3516
3517        /* Initialize rate scaling */
3518        IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3519                       sta->addr);
3520        iwl_rs_rate_init(priv, sta, sta_id);
3521        mutex_unlock(&priv->mutex);
3522
3523        return 0;
3524}
3525
3526void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3527                               struct ieee80211_channel_switch *ch_switch)
3528{
3529        struct iwl_priv *priv = hw->priv;
3530        const struct iwl_channel_info *ch_info;
3531        struct ieee80211_conf *conf = &hw->conf;
3532        struct ieee80211_channel *channel = ch_switch->channel;
3533        struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3534        /*
3535         * MULTI-FIXME
3536         * When we add support for multiple interfaces, we need to
3537         * revisit this. The channel switch command in the device
3538         * only affects the BSS context, but what does that really
3539         * mean? And what if we get a CSA on the second interface?
3540         * This needs a lot of work.
3541         */
3542        struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3543        u16 ch;
3544        unsigned long flags = 0;
3545
3546        IWL_DEBUG_MAC80211(priv, "enter\n");
3547
3548        if (iwl_is_rfkill(priv))
3549                goto out_exit;
3550
3551        if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3552            test_bit(STATUS_SCANNING, &priv->status))
3553                goto out_exit;
3554
3555        if (!iwl_is_associated_ctx(ctx))
3556                goto out_exit;
3557
3558        /* channel switch in progress */
3559        if (priv->switch_rxon.switch_in_progress == true)
3560                goto out_exit;
3561
3562        mutex_lock(&priv->mutex);
3563        if (priv->cfg->ops->lib->set_channel_switch) {
3564
3565                ch = channel->hw_value;
3566                if (le16_to_cpu(ctx->active.channel) != ch) {
3567                        ch_info = iwl_get_channel_info(priv,
3568                                                       channel->band,
3569                                                       ch);
3570                        if (!is_channel_valid(ch_info)) {
3571                                IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3572                                goto out;
3573                        }
3574                        spin_lock_irqsave(&priv->lock, flags);
3575
3576                        priv->current_ht_config.smps = conf->smps_mode;
3577
3578                        /* Configure HT40 channels */
3579                        ctx->ht.enabled = conf_is_ht(conf);
3580                        if (ctx->ht.enabled) {
3581                                if (conf_is_ht40_minus(conf)) {
3582                                        ctx->ht.extension_chan_offset =
3583                                                IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3584                                        ctx->ht.is_40mhz = true;
3585                                } else if (conf_is_ht40_plus(conf)) {
3586                                        ctx->ht.extension_chan_offset =
3587                                                IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3588                                        ctx->ht.is_40mhz = true;
3589                                } else {
3590                                        ctx->ht.extension_chan_offset =
3591                                                IEEE80211_HT_PARAM_CHA_SEC_NONE;
3592                                        ctx->ht.is_40mhz = false;
3593                                }
3594                        } else
3595                                ctx->ht.is_40mhz = false;
3596
3597                        if ((le16_to_cpu(ctx->staging.channel) != ch))
3598                                ctx->staging.flags = 0;
3599
3600                        iwl_set_rxon_channel(priv, channel, ctx);
3601                        iwl_set_rxon_ht(priv, ht_conf);
3602                        iwl_set_flags_for_band(priv, ctx, channel->band,
3603                                               ctx->vif);
3604                        spin_unlock_irqrestore(&priv->lock, flags);
3605
3606                        iwl_set_rate(priv);
3607                        /*
3608                         * at this point, staging_rxon has the
3609                         * configuration for channel switch
3610                         */
3611                        if (priv->cfg->ops->lib->set_channel_switch(priv,
3612                                                                    ch_switch))
3613                                priv->switch_rxon.switch_in_progress = false;
3614                }
3615        }
3616out:
3617        mutex_unlock(&priv->mutex);
3618out_exit:
3619        if (!priv->switch_rxon.switch_in_progress)
3620                ieee80211_chswitch_done(ctx->vif, false);
3621        IWL_DEBUG_MAC80211(priv, "leave\n");
3622}
3623
3624void iwlagn_configure_filter(struct ieee80211_hw *hw,
3625                             unsigned int changed_flags,
3626                             unsigned int *total_flags,
3627                             u64 multicast)
3628{
3629        struct iwl_priv *priv = hw->priv;
3630        __le32 filter_or = 0, filter_nand = 0;
3631        struct iwl_rxon_context *ctx;
3632
3633#define CHK(test, flag) do { \
3634        if (*total_flags & (test))              \
3635                filter_or |= (flag);            \
3636        else                                    \
3637                filter_nand |= (flag);          \
3638        } while (0)
3639
3640        IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3641                        changed_flags, *total_flags);
3642
3643        CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3644        /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3645        CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3646        CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3647
3648#undef CHK
3649
3650        mutex_lock(&priv->mutex);
3651
3652        for_each_context(priv, ctx) {
3653                ctx->staging.filter_flags &= ~filter_nand;
3654                ctx->staging.filter_flags |= filter_or;
3655
3656                /*
3657                 * Not committing directly because hardware can perform a scan,
3658                 * but we'll eventually commit the filter flags change anyway.
3659                 */
3660        }
3661
3662        mutex_unlock(&priv->mutex);
3663
3664        /*
3665         * Receiving all multicast frames is always enabled by the
3666         * default flags setup in iwl_connection_init_rx_config()
3667         * since we currently do not support programming multicast
3668         * filters into the device.
3669         */
3670        *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3671                        FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3672}
3673
3674void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3675{
3676        struct iwl_priv *priv = hw->priv;
3677
3678        mutex_lock(&priv->mutex);
3679        IWL_DEBUG_MAC80211(priv, "enter\n");
3680
3681        /* do not support "flush" */
3682        if (!priv->cfg->ops->lib->txfifo_flush)
3683                goto done;
3684
3685        if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3686                IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3687                goto done;
3688        }
3689        if (iwl_is_rfkill(priv)) {
3690                IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3691                goto done;
3692        }
3693
3694        /*
3695         * mac80211 will not push any more frames for transmit
3696         * until the flush is completed
3697         */
3698        if (drop) {
3699                IWL_DEBUG_MAC80211(priv, "send flush command\n");
3700                if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3701                        IWL_ERR(priv, "flush request fail\n");
3702                        goto done;
3703                }
3704        }
3705        IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3706        iwlagn_wait_tx_queue_empty(priv);
3707done:
3708        mutex_unlock(&priv->mutex);
3709        IWL_DEBUG_MAC80211(priv, "leave\n");
3710}
3711
3712/*****************************************************************************
3713 *
3714 * driver setup and teardown
3715 *
3716 *****************************************************************************/
3717
3718static void iwl_setup_deferred_work(struct iwl_priv *priv)
3719{
3720        priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3721
3722        init_waitqueue_head(&priv->wait_command_queue);
3723
3724        INIT_WORK(&priv->restart, iwl_bg_restart);
3725        INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3726        INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3727        INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3728        INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3729        INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3730        INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3731        INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3732        INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3733
3734        iwl_setup_scan_deferred_work(priv);
3735
3736        if (priv->cfg->ops->lib->setup_deferred_work)
3737                priv->cfg->ops->lib->setup_deferred_work(priv);
3738
3739        init_timer(&priv->statistics_periodic);
3740        priv->statistics_periodic.data = (unsigned long)priv;
3741        priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3742
3743        init_timer(&priv->ucode_trace);
3744        priv->ucode_trace.data = (unsigned long)priv;
3745        priv->ucode_trace.function = iwl_bg_ucode_trace;
3746
3747        init_timer(&priv->watchdog);
3748        priv->watchdog.data = (unsigned long)priv;
3749        priv->watchdog.function = iwl_bg_watchdog;
3750
3751        if (!priv->cfg->base_params->use_isr_legacy)
3752                tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3753                        iwl_irq_tasklet, (unsigned long)priv);
3754        else
3755                tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3756                        iwl_irq_tasklet_legacy, (unsigned long)priv);
3757}
3758
3759static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3760{
3761        if (priv->cfg->ops->lib->cancel_deferred_work)
3762                priv->cfg->ops->lib->cancel_deferred_work(priv);
3763
3764        cancel_delayed_work_sync(&priv->init_alive_start);
3765        cancel_delayed_work(&priv->alive_start);
3766        cancel_work_sync(&priv->run_time_calib_work);
3767        cancel_work_sync(&priv->beacon_update);
3768
3769        iwl_cancel_scan_deferred_work(priv);
3770
3771        cancel_work_sync(&priv->bt_full_concurrency);
3772        cancel_work_sync(&priv->bt_runtime_config);
3773
3774        del_timer_sync(&priv->statistics_periodic);
3775        del_timer_sync(&priv->ucode_trace);
3776}
3777
3778static void iwl_init_hw_rates(struct iwl_priv *priv,
3779                              struct ieee80211_rate *rates)
3780{
3781        int i;
3782
3783        for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3784                rates[i].bitrate = iwl_rates[i].ieee * 5;
3785                rates[i].hw_value = i; /* Rate scaling will work on indexes */
3786                rates[i].hw_value_short = i;
3787                rates[i].flags = 0;
3788                if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3789                        /*
3790                         * If CCK != 1M then set short preamble rate flag.
3791                         */
3792                        rates[i].flags |=
3793                                (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3794                                        0 : IEEE80211_RATE_SHORT_PREAMBLE;
3795                }
3796        }
3797}
3798
3799static int iwl_init_drv(struct iwl_priv *priv)
3800{
3801        int ret;
3802
3803        spin_lock_init(&priv->sta_lock);
3804        spin_lock_init(&priv->hcmd_lock);
3805
3806        INIT_LIST_HEAD(&priv->free_frames);
3807
3808        mutex_init(&priv->mutex);
3809        mutex_init(&priv->sync_cmd_mutex);
3810
3811        priv->ieee_channels = NULL;
3812        priv->ieee_rates = NULL;
3813        priv->band = IEEE80211_BAND_2GHZ;
3814
3815        priv->iw_mode = NL80211_IFTYPE_STATION;
3816        priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3817        priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3818        priv->_agn.agg_tids_count = 0;
3819
3820        /* initialize force reset */
3821        priv->force_reset[IWL_RF_RESET].reset_duration =
3822                IWL_DELAY_NEXT_FORCE_RF_RESET;
3823        priv->force_reset[IWL_FW_RESET].reset_duration =
3824                IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3825
3826        /* Choose which receivers/antennas to use */
3827        if (priv->cfg->ops->hcmd->set_rxon_chain)
3828                priv->cfg->ops->hcmd->set_rxon_chain(priv,
3829                                        &priv->contexts[IWL_RXON_CTX_BSS]);
3830
3831        iwl_init_scan_params(priv);
3832
3833        /* init bt coex */
3834        if (priv->cfg->bt_params &&
3835            priv->cfg->bt_params->advanced_bt_coexist) {
3836                priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3837                priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3838                priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3839                priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3840                priv->bt_duration = BT_DURATION_LIMIT_DEF;
3841                priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3842        }
3843
3844        /* Set the tx_power_user_lmt to the lowest power level
3845         * this value will get overwritten by channel max power avg
3846         * from eeprom */
3847        priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3848        priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3849
3850        ret = iwl_init_channel_map(priv);
3851        if (ret) {
3852                IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3853                goto err;
3854        }
3855
3856        ret = iwlcore_init_geos(priv);
3857        if (ret) {
3858                IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3859                goto err_free_channel_map;
3860        }
3861        iwl_init_hw_rates(priv, priv->ieee_rates);
3862
3863        return 0;
3864
3865err_free_channel_map:
3866        iwl_free_channel_map(priv);
3867err:
3868        return ret;
3869}
3870
3871static void iwl_uninit_drv(struct iwl_priv *priv)
3872{
3873        iwl_calib_free_results(priv);
3874        iwlcore_free_geos(priv);
3875        iwl_free_channel_map(priv);
3876        kfree(priv->scan_cmd);
3877}
3878
3879#ifdef CONFIG_IWL5000
3880struct ieee80211_ops iwlagn_hw_ops = {
3881        .tx = iwlagn_mac_tx,
3882        .start = iwlagn_mac_start,
3883        .stop = iwlagn_mac_stop,
3884        .add_interface = iwl_mac_add_interface,
3885        .remove_interface = iwl_mac_remove_interface,
3886        .change_interface = iwl_mac_change_interface,
3887        .config = iwlagn_mac_config,
3888        .configure_filter = iwlagn_configure_filter,
3889        .set_key = iwlagn_mac_set_key,
3890        .update_tkip_key = iwlagn_mac_update_tkip_key,
3891        .conf_tx = iwl_mac_conf_tx,
3892        .bss_info_changed = iwlagn_bss_info_changed,
3893        .ampdu_action = iwlagn_mac_ampdu_action,
3894        .hw_scan = iwl_mac_hw_scan,
3895        .sta_notify = iwlagn_mac_sta_notify,
3896        .sta_add = iwlagn_mac_sta_add,
3897        .sta_remove = iwl_mac_sta_remove,
3898        .channel_switch = iwlagn_mac_channel_switch,
3899        .flush = iwlagn_mac_flush,
3900        .tx_last_beacon = iwl_mac_tx_last_beacon,
3901};
3902#endif
3903
3904static void iwl_hw_detect(struct iwl_priv *priv)
3905{
3906        priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
3907        priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
3908        pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
3909        IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3910}
3911
3912static int iwl_set_hw_params(struct iwl_priv *priv)
3913{
3914        priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3915        priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3916        if (priv->cfg->mod_params->amsdu_size_8K)
3917                priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3918        else
3919                priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3920
3921        priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3922
3923        if (priv->cfg->mod_params->disable_11n)
3924                priv->cfg->sku &= ~IWL_SKU_N;
3925
3926        /* Device-specific setup */
3927        return priv->cfg->ops->lib->set_hw_params(priv);
3928}
3929
3930static const u8 iwlagn_bss_ac_to_fifo[] = {
3931        IWL_TX_FIFO_VO,
3932        IWL_TX_FIFO_VI,
3933        IWL_TX_FIFO_BE,
3934        IWL_TX_FIFO_BK,
3935};
3936
3937static const u8 iwlagn_bss_ac_to_queue[] = {
3938        0, 1, 2, 3,
3939};
3940
3941static const u8 iwlagn_pan_ac_to_fifo[] = {
3942        IWL_TX_FIFO_VO_IPAN,
3943        IWL_TX_FIFO_VI_IPAN,
3944        IWL_TX_FIFO_BE_IPAN,
3945        IWL_TX_FIFO_BK_IPAN,
3946};
3947
3948static const u8 iwlagn_pan_ac_to_queue[] = {
3949        7, 6, 5, 4,
3950};
3951
3952static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3953{
3954        int err = 0, i;
3955        struct iwl_priv *priv;
3956        struct ieee80211_hw *hw;
3957        struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3958        unsigned long flags;
3959        u16 pci_cmd, num_mac;
3960
3961        /************************
3962         * 1. Allocating HW data
3963         ************************/
3964
3965        /* Disabling hardware scan means that mac80211 will perform scans
3966         * "the hard way", rather than using device's scan. */
3967        if (cfg->mod_params->disable_hw_scan) {
3968                dev_printk(KERN_DEBUG, &(pdev->dev),
3969                        "sw scan support is deprecated\n");
3970#ifdef CONFIG_IWL5000
3971                iwlagn_hw_ops.hw_scan = NULL;
3972#endif
3973#ifdef CONFIG_IWL4965
3974                iwl4965_hw_ops.hw_scan = NULL;
3975#endif
3976        }
3977
3978        hw = iwl_alloc_all(cfg);
3979        if (!hw) {
3980                err = -ENOMEM;
3981                goto out;
3982        }
3983        priv = hw->priv;
3984        /* At this point both hw and priv are allocated. */
3985
3986        /*
3987         * The default context is always valid,
3988         * more may be discovered when firmware
3989         * is loaded.
3990         */
3991        priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3992
3993        for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3994                priv->contexts[i].ctxid = i;
3995
3996        priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3997        priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3998        priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3999        priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4000        priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4001        priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4002        priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4003        priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4004        priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4005        priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4006        priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4007                BIT(NL80211_IFTYPE_ADHOC);
4008        priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4009                BIT(NL80211_IFTYPE_STATION);
4010        priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
4011        priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4012        priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4013        priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4014
4015        priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4016        priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4017        priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4018        priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4019        priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4020        priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4021        priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4022        priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4023        priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4024        priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4025        priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4026        priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4027                BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4028        priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4029        priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4030        priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4031
4032        BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4033
4034        SET_IEEE80211_DEV(hw, &pdev->dev);
4035
4036        IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4037        priv->cfg = cfg;
4038        priv->pci_dev = pdev;
4039        priv->inta_mask = CSR_INI_SET_MASK;
4040
4041        /* is antenna coupling more than 35dB ? */
4042        priv->bt_ant_couple_ok =
4043                (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4044                true : false;
4045
4046        /* enable/disable bt channel inhibition */
4047        priv->bt_ch_announce = iwlagn_bt_ch_announce;
4048        IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
4049                       (priv->bt_ch_announce) ? "On" : "Off");
4050
4051        if (iwl_alloc_traffic_mem(priv))
4052                IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4053
4054        /**************************
4055         * 2. Initializing PCI bus
4056         **************************/
4057        pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4058                                PCIE_LINK_STATE_CLKPM);
4059
4060        if (pci_enable_device(pdev)) {
4061                err = -ENODEV;
4062                goto out_ieee80211_free_hw;
4063        }
4064
4065        pci_set_master(pdev);
4066
4067        err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4068        if (!err)
4069                err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4070        if (err) {
4071                err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4072                if (!err)
4073                        err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4074                /* both attempts failed: */
4075                if (err) {
4076                        IWL_WARN(priv, "No suitable DMA available.\n");
4077                        goto out_pci_disable_device;
4078                }
4079        }
4080
4081        err = pci_request_regions(pdev, DRV_NAME);
4082        if (err)
4083                goto out_pci_disable_device;
4084
4085        pci_set_drvdata(pdev, priv);
4086
4087
4088        /***********************
4089         * 3. Read REV register
4090         ***********************/
4091        priv->hw_base = pci_iomap(pdev, 0, 0);
4092        if (!priv->hw_base) {
4093                err = -ENODEV;
4094                goto out_pci_release_regions;
4095        }
4096
4097        IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4098                (unsigned long long) pci_resource_len(pdev, 0));
4099        IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4100
4101        /* these spin locks will be used in apm_ops.init and EEPROM access
4102         * we should init now
4103         */
4104        spin_lock_init(&priv->reg_lock);
4105        spin_lock_init(&priv->lock);
4106
4107        /*
4108         * stop and reset the on-board processor just in case it is in a
4109         * strange state ... like being left stranded by a primary kernel
4110         * and this is now the kdump kernel trying to start up
4111         */
4112        iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4113
4114        iwl_hw_detect(priv);
4115        IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4116                priv->cfg->name, priv->hw_rev);
4117
4118        /* We disable the RETRY_TIMEOUT register (0x41) to keep
4119         * PCI Tx retries from interfering with C3 CPU state */
4120        pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4121
4122        iwl_prepare_card_hw(priv);
4123        if (!priv->hw_ready) {
4124                IWL_WARN(priv, "Failed, HW not ready\n");
4125                goto out_iounmap;
4126        }
4127
4128        /*****************
4129         * 4. Read EEPROM
4130         *****************/
4131        /* Read the EEPROM */
4132        err = iwl_eeprom_init(priv);
4133        if (err) {
4134                IWL_ERR(priv, "Unable to init EEPROM\n");
4135                goto out_iounmap;
4136        }
4137        err = iwl_eeprom_check_version(priv);
4138        if (err)
4139                goto out_free_eeprom;
4140
4141        err = iwl_eeprom_check_sku(priv);
4142        if (err)
4143                goto out_free_eeprom;
4144
4145        /* extract MAC Address */
4146        iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4147        IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4148        priv->hw->wiphy->addresses = priv->addresses;
4149        priv->hw->wiphy->n_addresses = 1;
4150        num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4151        if (num_mac > 1) {
4152                memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4153                       ETH_ALEN);
4154                priv->addresses[1].addr[5]++;
4155                priv->hw->wiphy->n_addresses++;
4156        }
4157
4158        /************************
4159         * 5. Setup HW constants
4160         ************************/
4161        if (iwl_set_hw_params(priv)) {
4162                IWL_ERR(priv, "failed to set hw parameters\n");
4163                goto out_free_eeprom;
4164        }
4165
4166        /*******************
4167         * 6. Setup priv
4168         *******************/
4169
4170        err = iwl_init_drv(priv);
4171        if (err)
4172                goto out_free_eeprom;
4173        /* At this point both hw and priv are initialized. */
4174
4175        /********************
4176         * 7. Setup services
4177         ********************/
4178        spin_lock_irqsave(&priv->lock, flags);
4179        iwl_disable_interrupts(priv);
4180        spin_unlock_irqrestore(&priv->lock, flags);
4181
4182        pci_enable_msi(priv->pci_dev);
4183
4184        if (priv->cfg->ops->lib->isr_ops.alloc)
4185                priv->cfg->ops->lib->isr_ops.alloc(priv);
4186
4187        err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
4188                          IRQF_SHARED, DRV_NAME, priv);
4189        if (err) {
4190                IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4191                goto out_disable_msi;
4192        }
4193
4194        iwl_setup_deferred_work(priv);
4195        iwl_setup_rx_handlers(priv);
4196
4197        /*********************************************
4198         * 8. Enable interrupts and read RFKILL state
4199         *********************************************/
4200
4201        /* enable rfkill interrupt: hw bug w/a */
4202        pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4203        if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4204                pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4205                pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4206        }
4207
4208        iwl_enable_rfkill_int(priv);
4209
4210        /* If platform's RF_KILL switch is NOT set to KILL */
4211        if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4212                clear_bit(STATUS_RF_KILL_HW, &priv->status);
4213        else
4214                set_bit(STATUS_RF_KILL_HW, &priv->status);
4215
4216        wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4217                test_bit(STATUS_RF_KILL_HW, &priv->status));
4218
4219        iwl_power_initialize(priv);
4220        iwl_tt_initialize(priv);
4221
4222        init_completion(&priv->_agn.firmware_loading_complete);
4223
4224        err = iwl_request_firmware(priv, true);
4225        if (err)
4226                goto out_destroy_workqueue;
4227
4228        return 0;
4229
4230 out_destroy_workqueue:
4231        destroy_workqueue(priv->workqueue);
4232        priv->workqueue = NULL;
4233        free_irq(priv->pci_dev->irq, priv);
4234        if (priv->cfg->ops->lib->isr_ops.free)
4235                priv->cfg->ops->lib->isr_ops.free(priv);
4236 out_disable_msi:
4237        pci_disable_msi(priv->pci_dev);
4238        iwl_uninit_drv(priv);
4239 out_free_eeprom:
4240        iwl_eeprom_free(priv);
4241 out_iounmap:
4242        pci_iounmap(pdev, priv->hw_base);
4243 out_pci_release_regions:
4244        pci_set_drvdata(pdev, NULL);
4245        pci_release_regions(pdev);
4246 out_pci_disable_device:
4247        pci_disable_device(pdev);
4248 out_ieee80211_free_hw:
4249        iwl_free_traffic_mem(priv);
4250        ieee80211_free_hw(priv->hw);
4251 out:
4252        return err;
4253}
4254
4255static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4256{
4257        struct iwl_priv *priv = pci_get_drvdata(pdev);
4258        unsigned long flags;
4259
4260        if (!priv)
4261                return;
4262
4263        wait_for_completion(&priv->_agn.firmware_loading_complete);
4264
4265        IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4266
4267        iwl_dbgfs_unregister(priv);
4268        sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4269
4270        /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4271         * to be called and iwl_down since we are removing the device
4272         * we need to set STATUS_EXIT_PENDING bit.
4273         */
4274        set_bit(STATUS_EXIT_PENDING, &priv->status);
4275        if (priv->mac80211_registered) {
4276                ieee80211_unregister_hw(priv->hw);
4277                priv->mac80211_registered = 0;
4278        } else {
4279                iwl_down(priv);
4280        }
4281
4282        /*
4283         * Make sure device is reset to low power before unloading driver.
4284         * This may be redundant with iwl_down(), but there are paths to
4285         * run iwl_down() without calling apm_ops.stop(), and there are
4286         * paths to avoid running iwl_down() at all before leaving driver.
4287         * This (inexpensive) call *makes sure* device is reset.
4288         */
4289        iwl_apm_stop(priv);
4290
4291        iwl_tt_exit(priv);
4292
4293        /* make sure we flush any pending irq or
4294         * tasklet for the driver
4295         */
4296        spin_lock_irqsave(&priv->lock, flags);
4297        iwl_disable_interrupts(priv);
4298        spin_unlock_irqrestore(&priv->lock, flags);
4299
4300        iwl_synchronize_irq(priv);
4301
4302        iwl_dealloc_ucode_pci(priv);
4303
4304        if (priv->rxq.bd)
4305                iwlagn_rx_queue_free(priv, &priv->rxq);
4306        iwlagn_hw_txq_ctx_free(priv);
4307
4308        iwl_eeprom_free(priv);
4309
4310
4311        /*netif_stop_queue(dev); */
4312        flush_workqueue(priv->workqueue);
4313
4314        /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4315         * priv->workqueue... so we can't take down the workqueue
4316         * until now... */
4317        destroy_workqueue(priv->workqueue);
4318        priv->workqueue = NULL;
4319        iwl_free_traffic_mem(priv);
4320
4321        free_irq(priv->pci_dev->irq, priv);
4322        pci_disable_msi(priv->pci_dev);
4323        pci_iounmap(pdev, priv->hw_base);
4324        pci_release_regions(pdev);
4325        pci_disable_device(pdev);
4326        pci_set_drvdata(pdev, NULL);
4327
4328        iwl_uninit_drv(priv);
4329
4330        if (priv->cfg->ops->lib->isr_ops.free)
4331                priv->cfg->ops->lib->isr_ops.free(priv);
4332
4333        dev_kfree_skb(priv->beacon_skb);
4334
4335        ieee80211_free_hw(priv->hw);
4336}
4337
4338
4339/*****************************************************************************
4340 *
4341 * driver and module entry point
4342 *
4343 *****************************************************************************/
4344
4345/* Hardware specific file defines the PCI IDs table for that hardware module */
4346static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4347#ifdef CONFIG_IWL4965
4348        {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4349        {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4350#endif /* CONFIG_IWL4965 */
4351#ifdef CONFIG_IWL5000
4352/* 5100 Series WiFi */
4353        {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4354        {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4355        {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4356        {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4357        {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4358        {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4359        {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4360        {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4361        {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4362        {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4363        {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4364        {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4365        {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4366        {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4367        {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4368        {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4369        {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4370        {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4371        {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4372        {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4373        {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4374        {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4375        {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4376        {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4377
4378/* 5300 Series WiFi */
4379        {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4380        {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4381        {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4382        {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4383        {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4384        {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4385        {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4386        {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4387        {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4388        {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4389        {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4390        {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4391
4392/* 5350 Series WiFi/WiMax */
4393        {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4394        {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4395        {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4396
4397/* 5150 Series Wifi/WiMax */
4398        {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4399        {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4400        {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4401        {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4402        {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4403        {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4404
4405        {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4406        {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4407        {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4408        {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4409
4410/* 6x00 Series */
4411        {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4412        {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4413        {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4414        {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4415        {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4416        {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4417        {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4418        {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4419        {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4420        {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4421
4422/* 6x05 Series */
4423        {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4424        {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4425        {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4426        {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4427        {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4428        {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4429        {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4430
4431/* 6x30 Series */
4432        {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4433        {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4434        {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4435        {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4436        {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4437        {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4438        {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4439        {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4440        {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4441        {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4442        {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4443        {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4444        {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4445        {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4446        {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4447        {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4448
4449/* 6x50 WiFi/WiMax Series */
4450        {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4451        {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4452        {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4453        {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4454        {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4455        {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4456
4457/* 6150 WiFi/WiMax Series */
4458        {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4459        {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4460        {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4461        {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4462        {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4463        {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4464
4465/* 1000 Series WiFi */
4466        {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4467        {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4468        {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4469        {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4470        {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4471        {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4472        {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4473        {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4474        {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4475        {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4476        {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4477        {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4478
4479/* 100 Series WiFi */
4480        {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4481        {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4482        {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4483        {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4484        {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4485        {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4486
4487/* 130 Series WiFi */
4488        {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4489        {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4490        {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4491        {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4492        {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4493        {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4494
4495#endif /* CONFIG_IWL5000 */
4496
4497        {0}
4498};
4499MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4500
4501static struct pci_driver iwl_driver = {
4502        .name = DRV_NAME,
4503        .id_table = iwl_hw_card_ids,
4504        .probe = iwl_pci_probe,
4505        .remove = __devexit_p(iwl_pci_remove),
4506        .driver.pm = IWL_PM_OPS,
4507};
4508
4509static int __init iwl_init(void)
4510{
4511
4512        int ret;
4513        pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4514        pr_info(DRV_COPYRIGHT "\n");
4515
4516        ret = iwlagn_rate_control_register();
4517        if (ret) {
4518                pr_err("Unable to register rate control algorithm: %d\n", ret);
4519                return ret;
4520        }
4521
4522        ret = pci_register_driver(&iwl_driver);
4523        if (ret) {
4524                pr_err("Unable to initialize PCI module\n");
4525                goto error_register;
4526        }
4527
4528        return ret;
4529
4530error_register:
4531        iwlagn_rate_control_unregister();
4532        return ret;
4533}
4534
4535static void __exit iwl_exit(void)
4536{
4537        pci_unregister_driver(&iwl_driver);
4538        iwlagn_rate_control_unregister();
4539}
4540
4541module_exit(iwl_exit);
4542module_init(iwl_init);
4543
4544#ifdef CONFIG_IWLWIFI_DEBUG
4545module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4546MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4547module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4548MODULE_PARM_DESC(debug, "debug output mask");
4549#endif
4550
4551module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4552MODULE_PARM_DESC(swcrypto50,
4553                 "using crypto in software (default 0 [hardware]) (deprecated)");
4554module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4555MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4556module_param_named(queues_num50,
4557                   iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4558MODULE_PARM_DESC(queues_num50,
4559                 "number of hw queues in 50xx series (deprecated)");
4560module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4561MODULE_PARM_DESC(queues_num, "number of hw queues.");
4562module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4563MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4564module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4565MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4566module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4567                   int, S_IRUGO);
4568MODULE_PARM_DESC(amsdu_size_8K50,
4569                 "enable 8K amsdu size in 50XX series (deprecated)");
4570module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4571                   int, S_IRUGO);
4572MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4573module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4574MODULE_PARM_DESC(fw_restart50,
4575                 "restart firmware in case of error (deprecated)");
4576module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4577MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4578module_param_named(
4579        disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4580MODULE_PARM_DESC(disable_hw_scan,
4581                 "disable hardware scanning (default 0) (deprecated)");
4582
4583module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4584                   S_IRUGO);
4585MODULE_PARM_DESC(ucode_alternative,
4586                 "specify ucode alternative to use from ucode file");
4587
4588module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4589MODULE_PARM_DESC(antenna_coupling,
4590                 "specify antenna coupling in dB (defualt: 0 dB)");
4591
4592module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4593MODULE_PARM_DESC(bt_ch_inhibition,
4594                 "Disable BT channel inhibition (default: enable)");
4595