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39#ifndef __IWM_LMAC_H__
40#define __IWM_LMAC_H__
41
42struct iwm_lmac_hdr {
43 u8 id;
44 u8 flags;
45 __le16 seq_num;
46} __packed;
47
48
49#define CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_AFTER_MSK 0x1
50
51struct iwm_lmac_cal_cfg_elt {
52 __le32 enable;
53 __le32 start;
54 __le32 send_res;
55 __le32 apply_res;
56 __le32 reserved;
57} __packed;
58
59struct iwm_lmac_cal_cfg_status {
60 struct iwm_lmac_cal_cfg_elt init;
61 struct iwm_lmac_cal_cfg_elt periodic;
62 __le32 flags;
63} __packed;
64
65struct iwm_lmac_cal_cfg_cmd {
66 struct iwm_lmac_cal_cfg_status ucode_cfg;
67 struct iwm_lmac_cal_cfg_status driver_cfg;
68 __le32 reserved;
69} __packed;
70
71struct iwm_lmac_cal_cfg_resp {
72 __le32 status;
73} __packed;
74
75#define IWM_CARD_STATE_SW_HW_ENABLED 0x00
76#define IWM_CARD_STATE_HW_DISABLED 0x01
77#define IWM_CARD_STATE_SW_DISABLED 0x02
78#define IWM_CARD_STATE_CTKILL_DISABLED 0x04
79#define IWM_CARD_STATE_IS_RXON 0x10
80
81struct iwm_lmac_card_state {
82 __le32 flags;
83} __packed;
84
85
86
87
88
89
90
91enum {
92
93 COEX_UNASSOC_IDLE = 0,
94 COEX_UNASSOC_MANUAL_SCAN,
95 COEX_UNASSOC_AUTO_SCAN,
96
97
98 COEX_CALIBRATION,
99 COEX_PERIODIC_CALIBRATION,
100
101
102 COEX_CONNECTION_ESTAB,
103
104
105 COEX_ASSOCIATED_IDLE,
106 COEX_ASSOC_MANUAL_SCAN,
107 COEX_ASSOC_AUTO_SCAN,
108 COEX_ASSOC_ACTIVE_LEVEL,
109
110
111 COEX_RF_ON,
112 COEX_RF_OFF,
113 COEX_STAND_ALONE_DEBUG,
114
115
116 COEX_IPAN_ASSOC_LEVEL,
117
118
119 COEX_RSRVD1,
120 COEX_RSRVD2,
121
122 COEX_EVENTS_NUM
123};
124
125#define COEX_EVT_FLAG_MEDIUM_FREE_NTFY_MSK 0x1
126#define COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_MSK 0x2
127#define COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_MSK 0x4
128
129struct coex_event {
130 u8 req_prio;
131 u8 win_med_prio;
132 u8 reserved;
133 u8 flags;
134} __packed;
135
136#define COEX_FLAGS_STA_TABLE_VALID_MSK 0x1
137#define COEX_FLAGS_UNASSOC_WAKEUP_UMASK_MSK 0x4
138#define COEX_FLAGS_ASSOC_WAKEUP_UMASK_MSK 0x8
139#define COEX_FLAGS_COEX_ENABLE_MSK 0x80
140
141struct iwm_coex_prio_table_cmd {
142 u8 flags;
143 u8 reserved[3];
144 struct coex_event sta_prio[COEX_EVENTS_NUM];
145} __packed;
146
147
148
149
150
151
152
153
154
155
156#define COEX_UNASSOC_IDLE_FLAGS 0
157#define COEX_UNASSOC_MANUAL_SCAN_FLAGS (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_MSK | \
158 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_MSK)
159#define COEX_UNASSOC_AUTO_SCAN_FLAGS (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_MSK | \
160 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_MSK)
161#define COEX_CALIBRATION_FLAGS (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_MSK | \
162 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_MSK)
163#define COEX_PERIODIC_CALIBRATION_FLAGS 0
164
165
166#define COEX_CONNECTION_ESTAB_FLAGS (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_MSK | \
167 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_MSK | \
168 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_MSK)
169#define COEX_ASSOCIATED_IDLE_FLAGS 0
170#define COEX_ASSOC_MANUAL_SCAN_FLAGS (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_MSK | \
171 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_MSK)
172#define COEX_ASSOC_AUTO_SCAN_FLAGS (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_MSK | \
173 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_MSK)
174#define COEX_ASSOC_ACTIVE_LEVEL_FLAGS 0
175#define COEX_RF_ON_FLAGS 0
176#define COEX_RF_OFF_FLAGS 0
177#define COEX_STAND_ALONE_DEBUG_FLAGS (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_MSK | \
178 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_MSK)
179#define COEX_IPAN_ASSOC_LEVEL_FLAGS (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_MSK | \
180 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_MSK | \
181 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_MSK)
182#define COEX_RSRVD1_FLAGS 0
183#define COEX_RSRVD2_FLAGS 0
184
185
186#define COEX_XOR_RF_ON_FLAGS (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_MSK | \
187 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_MSK | \
188 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_MSK)
189
190
191struct iwm_ct_kill_cfg_cmd {
192 u32 exit_threshold;
193 u32 reserved;
194 u32 entry_threshold;
195} __packed;
196
197
198
199#define REPLY_PAD 0x0
200#define REPLY_ALIVE 0x1
201#define REPLY_ERROR 0x2
202#define REPLY_ECHO 0x3
203#define REPLY_HALT 0x6
204
205
206#define REPLY_RX_ON 0x10
207#define REPLY_RX_ON_ASSOC 0x11
208#define REPLY_RX_OFF 0x12
209#define REPLY_QOS_PARAM 0x13
210#define REPLY_RX_ON_TIMING 0x14
211#define REPLY_INTERNAL_QOS_PARAM 0x15
212#define REPLY_RX_INT_TIMEOUT_CNFG 0x16
213#define REPLY_NULL 0x17
214
215
216#define REPLY_ADD_STA 0x18
217#define REPLY_REMOVE_STA 0x19
218#define REPLY_RESET_ALL_STA 0x1a
219
220
221#define REPLY_ALM_RX 0x1b
222#define REPLY_TX 0x1c
223#define REPLY_TXFIFO_FLUSH 0x1e
224
225
226#define REPLY_MGMT_MCAST_KEY 0x1f
227#define REPLY_WEPKEY 0x20
228#define REPLY_INIT_IV 0x21
229#define REPLY_WRITE_MIB 0x22
230#define REPLY_READ_MIB 0x23
231#define REPLY_RADIO_FE 0x24
232#define REPLY_TXFIFO_CFG 0x25
233#define REPLY_WRITE_READ 0x26
234#define REPLY_INSTALL_SEC_KEY 0x27
235
236
237#define REPLY_RATE_SCALE 0x47
238#define REPLY_LEDS_CMD 0x48
239#define REPLY_TX_LINK_QUALITY_CMD 0x4e
240#define REPLY_ANA_MIB_OVERRIDE_CMD 0x4f
241#define REPLY_WRITE2REG_CMD 0x50
242
243
244#define COEX_PRIORITY_TABLE_CMD 0x5a
245#define COEX_MEDIUM_NOTIFICATION 0x5b
246#define COEX_EVENT_CMD 0x5c
247
248
249#define REPLY_MAX_SLEEP_TIME_CMD 0x61
250#define CALIBRATION_CFG_CMD 0x65
251#define CALIBRATION_RES_NOTIFICATION 0x66
252#define CALIBRATION_COMPLETE_NOTIFICATION 0x67
253
254
255#define REPLY_QUIET_CMD 0x71
256#define REPLY_CHANNEL_SWITCH 0x72
257#define CHANNEL_SWITCH_NOTIFICATION 0x73
258
259#define REPLY_SPECTRUM_MEASUREMENT_CMD 0x74
260#define SPECTRUM_MEASURE_NOTIFICATION 0x75
261#define REPLY_MEASUREMENT_ABORT_CMD 0x76
262
263
264#define POWER_TABLE_CMD 0x77
265#define SAVE_RESTORE_ADDRESS_CMD 0x78
266#define REPLY_WATERMARK_CMD 0x79
267#define PM_DEBUG_STATISTIC_NOTIFIC 0x7B
268#define PD_FLUSH_N_NOTIFICATION 0x7C
269
270
271#define REPLY_SCAN_REQUEST_CMD 0x80
272#define REPLY_SCAN_ABORT_CMD 0x81
273#define SCAN_START_NOTIFICATION 0x82
274#define SCAN_RESULTS_NOTIFICATION 0x83
275#define SCAN_COMPLETE_NOTIFICATION 0x84
276
277
278#define REPLY_CONT_TX_CMD 0x85
279#define END_OF_CONT_TX_NOTIFICATION 0x86
280
281
282#define TIMER_CMD 0x87
283#define EEPROM_WRITE_CMD 0x88
284
285
286#define FEEDBACK_REQUEST_NOTIFICATION 0x8b
287#define REPLY_CW_CMD 0x8c
288
289
290#define BEACON_NOTIFICATION 0x90
291#define REPLY_TX_BEACON 0x91
292#define REPLY_REQUEST_ATIM 0x93
293#define WHO_IS_AWAKE_NOTIFICATION 0x94
294#define TX_PWR_DBM_LIMIT_CMD 0x95
295#define QUIET_NOTIFICATION 0x96
296#define TX_PWR_TABLE_CMD 0x97
297#define TX_ANT_CONFIGURATION_CMD 0x98
298#define MEASURE_ABORT_NOTIFICATION 0x99
299#define REPLY_CALIBRATION_TUNE 0x9a
300
301
302#define REPLY_BT_CONFIG 0x9b
303#define REPLY_STATISTICS_CMD 0x9c
304#define STATISTICS_NOTIFICATION 0x9d
305
306
307#define REPLY_CARD_STATE_CMD 0xa0
308#define CARD_STATE_NOTIFICATION 0xa1
309
310
311#define MISSED_BEACONS_NOTIFICATION 0xa2
312#define MISSED_BEACONS_NOTIFICATION_TH_CMD 0xa3
313
314#define REPLY_CT_KILL_CONFIG_CMD 0xa4
315
316
317#define REPLY_HD_PARAMS_CMD 0xa6
318#define HD_PARAMS_NOTIFICATION 0xa7
319#define SENSITIVITY_CMD 0xa8
320#define U_APSD_PARAMS_CMD 0xa9
321#define NOISY_PLATFORM_CMD 0xaa
322#define ILLEGAL_CMD 0xac
323#define REPLY_PHY_CALIBRATION_CMD 0xb0
324#define REPLAY_RX_GAIN_CALIB_CMD 0xb1
325
326
327#define REPLY_WIPAN_PARAMS_CMD 0xb2
328#define REPLY_WIPAN_RX_ON_CMD 0xb3
329#define REPLY_WIPAN_RX_ON_TIMING 0xb4
330#define REPLY_WIPAN_TX_PWR_TABLE_CMD 0xb5
331#define REPLY_WIPAN_RXON_ASSOC_CMD 0xb6
332#define REPLY_WIPAN_QOS_PARAM 0xb7
333#define WIPAN_REPLY_WEPKEY 0xb8
334
335
336#define BEAMFORMER_CFG_CMD 0xba
337#define BEAMFORMEE_NOTIFICATION 0xbb
338
339
340#define REPLY_RX_PHY_CMD 0xc0
341#define REPLY_RX_MPDU_CMD 0xc1
342#define REPLY_MULTICAST_HASH 0xc2
343#define REPLY_KDR_RX 0xc3
344#define REPLY_RX_DSP_EXT_INFO 0xc4
345#define REPLY_COMPRESSED_BA 0xc5
346
347
348#define PNC_CONFIG_CMD 0xc8
349#define PNC_UPDATE_TABLE_CMD 0xc9
350#define XVT_GENERAL_CTRL_CMD 0xca
351#define REPLY_LEGACY_RADIO_FE 0xdd
352
353
354#define WOWLAN_PATTERNS 0xe0
355#define WOWLAN_WAKEUP_FILTER 0xe1
356#define WOWLAN_TSC_RSC_PARAM 0xe2
357#define WOWLAN_TKIP_PARAM 0xe3
358#define WOWLAN_KEK_KCK_MATERIAL 0xe4
359#define WOWLAN_GET_STATUSES 0xe5
360#define WOWLAN_TX_POWER_PER_DB 0xe6
361#define REPLY_WOWLAN_GET_STATUSES WOWLAN_GET_STATUSES
362
363#define REPLY_DEBUG_CMD 0xf0
364#define REPLY_DSP_DEBUG_CMD 0xf1
365#define REPLY_DEBUG_MONITOR_CMD 0xf2
366#define REPLY_DEBUG_XVT_CMD 0xf3
367#define REPLY_DEBUG_DC_CALIB 0xf4
368#define REPLY_DYNAMIC_BP 0xf5
369
370
371#define REPLY_GP1_CMD 0xfa
372#define REPLY_GP2_CMD 0xfb
373#define REPLY_GP3_CMD 0xfc
374#define REPLY_GP4_CMD 0xfd
375#define REPLY_REPLAY_WRAPPER 0xfe
376#define REPLY_FRAME_DURATION_CALC_CMD 0xff
377
378#define LMAC_COMMAND_ID_MAX 0xff
379#define LMAC_COMMAND_ID_NUM (LMAC_COMMAND_ID_MAX + 1)
380
381
382
383
384enum {
385 PHY_CALIBRATE_DC_CMD = 0,
386 PHY_CALIBRATE_LO_CMD = 1,
387 PHY_CALIBRATE_RX_BB_CMD = 2,
388 PHY_CALIBRATE_TX_IQ_CMD = 3,
389 PHY_CALIBRATE_RX_IQ_CMD = 4,
390 PHY_CALIBRATION_NOISE_CMD = 5,
391 PHY_CALIBRATE_AGC_TABLE_CMD = 6,
392 PHY_CALIBRATE_CRYSTAL_FRQ_CMD = 7,
393 PHY_CALIBRATE_OPCODES_NUM,
394 SHILOH_PHY_CALIBRATE_DC_CMD = 8,
395 SHILOH_PHY_CALIBRATE_LO_CMD = 9,
396 SHILOH_PHY_CALIBRATE_RX_BB_CMD = 10,
397 SHILOH_PHY_CALIBRATE_TX_IQ_CMD = 11,
398 SHILOH_PHY_CALIBRATE_RX_IQ_CMD = 12,
399 SHILOH_PHY_CALIBRATION_NOISE_CMD = 13,
400 SHILOH_PHY_CALIBRATE_AGC_TABLE_CMD = 14,
401 SHILOH_PHY_CALIBRATE_CRYSTAL_FRQ_CMD = 15,
402 SHILOH_PHY_CALIBRATE_BASE_BAND_CMD = 16,
403 SHILOH_PHY_CALIBRATE_TXIQ_PERIODIC_CMD = 17,
404 CALIBRATION_CMD_NUM,
405};
406
407enum {
408 CALIB_CFG_RX_BB_IDX = 0,
409 CALIB_CFG_DC_IDX = 1,
410 CALIB_CFG_LO_IDX = 2,
411 CALIB_CFG_TX_IQ_IDX = 3,
412 CALIB_CFG_RX_IQ_IDX = 4,
413 CALIB_CFG_NOISE_IDX = 5,
414 CALIB_CFG_CRYSTAL_IDX = 6,
415 CALIB_CFG_TEMPERATURE_IDX = 7,
416 CALIB_CFG_PAPD_IDX = 8,
417 CALIB_CFG_LAST_IDX = CALIB_CFG_PAPD_IDX,
418 CALIB_CFG_MODULE_NUM,
419};
420
421#define IWM_CALIB_MAP_INIT_MSK 0xFFFF
422#define IWM_CALIB_MAP_PER_LMAC(m) ((m & 0xFF0000) >> 16)
423#define IWM_CALIB_MAP_PER_UMAC(m) ((m & 0xFF000000) >> 24)
424#define IWM_CALIB_OPCODE_TO_INDEX(op) (op - PHY_CALIBRATE_OPCODES_NUM)
425
426struct iwm_lmac_calib_hdr {
427 u8 opcode;
428 u8 first_grp;
429 u8 grp_num;
430 u8 all_data_valid;
431} __packed;
432
433#define IWM_LMAC_CALIB_FREQ_GROUPS_NR 7
434#define IWM_CALIB_FREQ_GROUPS_NR 5
435#define IWM_CALIB_DC_MODES_NR 12
436
437struct iwm_calib_rxiq_entry {
438 u16 ptam_postdist_ars;
439 u16 ptam_postdist_arc;
440} __packed;
441
442struct iwm_calib_rxiq_group {
443 struct iwm_calib_rxiq_entry mode[IWM_CALIB_DC_MODES_NR];
444} __packed;
445
446struct iwm_lmac_calib_rxiq {
447 struct iwm_calib_rxiq_group group[IWM_LMAC_CALIB_FREQ_GROUPS_NR];
448} __packed;
449
450struct iwm_calib_rxiq {
451 struct iwm_lmac_calib_hdr hdr;
452 struct iwm_calib_rxiq_group group[IWM_CALIB_FREQ_GROUPS_NR];
453} __packed;
454
455#define LMAC_STA_ID_SEED 0x0f
456#define LMAC_STA_ID_POS 0
457
458#define LMAC_STA_COLOR_SEED 0x7
459#define LMAC_STA_COLOR_POS 4
460
461struct iwm_lmac_power_report {
462 u8 pa_status;
463 u8 pa_integ_res_A[3];
464 u8 pa_integ_res_B[3];
465 u8 pa_integ_res_C[3];
466} __packed;
467
468struct iwm_lmac_tx_resp {
469 u8 frame_cnt;
470 u8 bt_kill_cnt;
471 __le16 retry_cnt;
472 __le32 initial_tx_rate;
473 __le16 wireless_media_time;
474 struct iwm_lmac_power_report power_report;
475 __le32 tfd_info;
476 __le16 seq_ctl;
477 __le16 byte_cnt;
478 u8 tlc_rate_info;
479 u8 ra_tid;
480 __le16 frame_ctl;
481 __le32 status;
482} __packed;
483
484#endif
485