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15#include <linux/module.h>
16#include <linux/uaccess.h>
17#include <linux/init.h>
18#include <linux/netdevice.h>
19#include <linux/etherdevice.h>
20#include <linux/skbuff.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/of_address.h>
24#include <linux/of_device.h>
25#include <linux/of_platform.h>
26#include <linux/of_mdio.h>
27#include <linux/of_net.h>
28#include <linux/phy.h>
29
30#define DRIVER_NAME "xilinx_emaclite"
31
32
33#define XEL_TXBUFF_OFFSET 0x0
34#define XEL_MDIOADDR_OFFSET 0x07E4
35#define XEL_MDIOWR_OFFSET 0x07E8
36#define XEL_MDIORD_OFFSET 0x07EC
37#define XEL_MDIOCTRL_OFFSET 0x07F0
38#define XEL_GIER_OFFSET 0x07F8
39#define XEL_TSR_OFFSET 0x07FC
40#define XEL_TPLR_OFFSET 0x07F4
41
42#define XEL_RXBUFF_OFFSET 0x1000
43#define XEL_RPLR_OFFSET 0x100C
44#define XEL_RSR_OFFSET 0x17FC
45
46#define XEL_BUFFER_OFFSET 0x0800
47
48
49#define XEL_MDIOADDR_REGADR_MASK 0x0000001F
50#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0
51#define XEL_MDIOADDR_PHYADR_SHIFT 5
52#define XEL_MDIOADDR_OP_MASK 0x00000400
53
54
55#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF
56
57
58#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF
59
60
61#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001
62#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008
63
64
65#define XEL_GIER_GIE_MASK 0x80000000
66
67
68#define XEL_TSR_XMIT_BUSY_MASK 0x00000001
69#define XEL_TSR_PROGRAM_MASK 0x00000002
70#define XEL_TSR_XMIT_IE_MASK 0x00000008
71#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000
72
73
74
75
76#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
77
78
79#define XEL_RSR_RECV_DONE_MASK 0x00000001
80#define XEL_RSR_RECV_IE_MASK 0x00000008
81
82
83#define XEL_TPLR_LENGTH_MASK 0x0000FFFF
84
85
86#define XEL_RPLR_LENGTH_MASK 0x0000FFFF
87
88#define XEL_HEADER_OFFSET 12
89#define XEL_HEADER_SHIFT 16
90
91
92#define XEL_ARP_PACKET_SIZE 28
93#define XEL_HEADER_IP_LENGTH_OFFSET 16
94
95
96
97#define TX_TIMEOUT (60*HZ)
98#define ALIGNMENT 4
99
100
101#define BUFFER_ALIGN(adr) ((ALIGNMENT - ((u32) adr)) % ALIGNMENT)
102
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120
121struct net_local {
122
123 struct net_device *ndev;
124
125 bool tx_ping_pong;
126 bool rx_ping_pong;
127 u32 next_tx_buf_to_use;
128 u32 next_rx_buf_to_use;
129 void __iomem *base_addr;
130
131 spinlock_t reset_lock;
132 struct sk_buff *deferred_skb;
133
134 struct phy_device *phy_dev;
135 struct device_node *phy_node;
136
137 struct mii_bus *mii_bus;
138 int mdio_irqs[PHY_MAX_ADDR];
139
140 int last_link;
141 bool has_mdio;
142};
143
144
145
146
147
148
149
150
151
152
153
154
155
156static void xemaclite_enable_interrupts(struct net_local *drvdata)
157{
158 u32 reg_data;
159
160
161 reg_data = in_be32(drvdata->base_addr + XEL_TSR_OFFSET);
162 out_be32(drvdata->base_addr + XEL_TSR_OFFSET,
163 reg_data | XEL_TSR_XMIT_IE_MASK);
164
165
166
167 if (drvdata->tx_ping_pong != 0) {
168 reg_data = in_be32(drvdata->base_addr +
169 XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
170 out_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
171 XEL_TSR_OFFSET,
172 reg_data | XEL_TSR_XMIT_IE_MASK);
173 }
174
175
176 out_be32(drvdata->base_addr + XEL_RSR_OFFSET,
177 XEL_RSR_RECV_IE_MASK);
178
179
180
181 if (drvdata->rx_ping_pong != 0) {
182 out_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
183 XEL_RSR_OFFSET,
184 XEL_RSR_RECV_IE_MASK);
185 }
186
187
188 out_be32(drvdata->base_addr + XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
189}
190
191
192
193
194
195
196
197
198static void xemaclite_disable_interrupts(struct net_local *drvdata)
199{
200 u32 reg_data;
201
202
203 out_be32(drvdata->base_addr + XEL_GIER_OFFSET, XEL_GIER_GIE_MASK);
204
205
206 reg_data = in_be32(drvdata->base_addr + XEL_TSR_OFFSET);
207 out_be32(drvdata->base_addr + XEL_TSR_OFFSET,
208 reg_data & (~XEL_TSR_XMIT_IE_MASK));
209
210
211
212 if (drvdata->tx_ping_pong != 0) {
213 reg_data = in_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
214 XEL_TSR_OFFSET);
215 out_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
216 XEL_TSR_OFFSET,
217 reg_data & (~XEL_TSR_XMIT_IE_MASK));
218 }
219
220
221 reg_data = in_be32(drvdata->base_addr + XEL_RSR_OFFSET);
222 out_be32(drvdata->base_addr + XEL_RSR_OFFSET,
223 reg_data & (~XEL_RSR_RECV_IE_MASK));
224
225
226
227 if (drvdata->rx_ping_pong != 0) {
228
229 reg_data = in_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
230 XEL_RSR_OFFSET);
231 out_be32(drvdata->base_addr + XEL_BUFFER_OFFSET +
232 XEL_RSR_OFFSET,
233 reg_data & (~XEL_RSR_RECV_IE_MASK));
234 }
235}
236
237
238
239
240
241
242
243
244
245
246static void xemaclite_aligned_write(void *src_ptr, u32 *dest_ptr,
247 unsigned length)
248{
249 u32 align_buffer;
250 u32 *to_u32_ptr;
251 u16 *from_u16_ptr, *to_u16_ptr;
252
253 to_u32_ptr = dest_ptr;
254 from_u16_ptr = (u16 *) src_ptr;
255 align_buffer = 0;
256
257 for (; length > 3; length -= 4) {
258 to_u16_ptr = (u16 *) ((void *) &align_buffer);
259 *to_u16_ptr++ = *from_u16_ptr++;
260 *to_u16_ptr++ = *from_u16_ptr++;
261
262
263 *to_u32_ptr++ = align_buffer;
264 }
265 if (length) {
266 u8 *from_u8_ptr, *to_u8_ptr;
267
268
269 align_buffer = 0;
270 to_u8_ptr = (u8 *) &align_buffer;
271 from_u8_ptr = (u8 *) from_u16_ptr;
272
273
274 for (; length > 0; length--)
275 *to_u8_ptr++ = *from_u8_ptr++;
276
277 *to_u32_ptr = align_buffer;
278 }
279}
280
281
282
283
284
285
286
287
288
289
290static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr,
291 unsigned length)
292{
293 u16 *to_u16_ptr, *from_u16_ptr;
294 u32 *from_u32_ptr;
295 u32 align_buffer;
296
297 from_u32_ptr = src_ptr;
298 to_u16_ptr = (u16 *) dest_ptr;
299
300 for (; length > 3; length -= 4) {
301
302 align_buffer = *from_u32_ptr++;
303 from_u16_ptr = (u16 *)&align_buffer;
304
305
306 *to_u16_ptr++ = *from_u16_ptr++;
307 *to_u16_ptr++ = *from_u16_ptr++;
308 }
309
310 if (length) {
311 u8 *to_u8_ptr, *from_u8_ptr;
312
313
314 to_u8_ptr = (u8 *) to_u16_ptr;
315 align_buffer = *from_u32_ptr++;
316 from_u8_ptr = (u8 *) &align_buffer;
317
318
319 for (; length > 0; length--)
320 *to_u8_ptr = *from_u8_ptr;
321 }
322}
323
324
325
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336
337
338
339static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
340 unsigned int byte_count)
341{
342 u32 reg_data;
343 void __iomem *addr;
344
345
346 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
347
348
349 if (byte_count > ETH_FRAME_LEN)
350 byte_count = ETH_FRAME_LEN;
351
352
353 reg_data = in_be32(addr + XEL_TSR_OFFSET);
354 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
355 XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
356
357
358 if (drvdata->tx_ping_pong != 0)
359 drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET;
360 } else if (drvdata->tx_ping_pong != 0) {
361
362
363
364 addr = (void __iomem __force *)((u32 __force)addr ^
365 XEL_BUFFER_OFFSET);
366 reg_data = in_be32(addr + XEL_TSR_OFFSET);
367
368 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
369 XEL_TSR_XMIT_ACTIVE_MASK)) != 0)
370 return -1;
371 } else
372 return -1;
373
374
375 xemaclite_aligned_write(data, (u32 __force *) addr, byte_count);
376
377 out_be32(addr + XEL_TPLR_OFFSET, (byte_count & XEL_TPLR_LENGTH_MASK));
378
379
380
381
382
383 reg_data = in_be32(addr + XEL_TSR_OFFSET);
384 reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK);
385 out_be32(addr + XEL_TSR_OFFSET, reg_data);
386
387 return 0;
388}
389
390
391
392
393
394
395
396
397
398
399
400static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data)
401{
402 void __iomem *addr;
403 u16 length, proto_type;
404 u32 reg_data;
405
406
407 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use);
408
409
410 reg_data = in_be32(addr + XEL_RSR_OFFSET);
411
412 if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
413 if (drvdata->rx_ping_pong != 0)
414 drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET;
415 } else {
416
417
418
419
420 if (drvdata->rx_ping_pong != 0)
421 addr = (void __iomem __force *)((u32 __force)addr ^
422 XEL_BUFFER_OFFSET);
423 else
424 return 0;
425
426
427 reg_data = in_be32(addr + XEL_RSR_OFFSET);
428 if ((reg_data & XEL_RSR_RECV_DONE_MASK) !=
429 XEL_RSR_RECV_DONE_MASK)
430 return 0;
431 }
432
433
434 proto_type = ((ntohl(in_be32(addr + XEL_HEADER_OFFSET +
435 XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) &
436 XEL_RPLR_LENGTH_MASK);
437
438
439
440 if (proto_type > (ETH_FRAME_LEN + ETH_FCS_LEN)) {
441
442 if (proto_type == ETH_P_IP) {
443 length = ((ntohl(in_be32(addr +
444 XEL_HEADER_IP_LENGTH_OFFSET +
445 XEL_RXBUFF_OFFSET)) >>
446 XEL_HEADER_SHIFT) &
447 XEL_RPLR_LENGTH_MASK);
448 length += ETH_HLEN + ETH_FCS_LEN;
449
450 } else if (proto_type == ETH_P_ARP)
451 length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN;
452 else
453
454
455 length = ETH_FRAME_LEN + ETH_FCS_LEN;
456 } else
457
458 length = proto_type + ETH_HLEN + ETH_FCS_LEN;
459
460
461 xemaclite_aligned_read((u32 __force *) (addr + XEL_RXBUFF_OFFSET),
462 data, length);
463
464
465 reg_data = in_be32(addr + XEL_RSR_OFFSET);
466 reg_data &= ~XEL_RSR_RECV_DONE_MASK;
467 out_be32(addr + XEL_RSR_OFFSET, reg_data);
468
469 return length;
470}
471
472
473
474
475
476
477
478
479
480
481
482
483static void xemaclite_update_address(struct net_local *drvdata,
484 u8 *address_ptr)
485{
486 void __iomem *addr;
487 u32 reg_data;
488
489
490 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
491
492 xemaclite_aligned_write(address_ptr, (u32 __force *) addr, ETH_ALEN);
493
494 out_be32(addr + XEL_TPLR_OFFSET, ETH_ALEN);
495
496
497 reg_data = in_be32(addr + XEL_TSR_OFFSET);
498 out_be32(addr + XEL_TSR_OFFSET, reg_data | XEL_TSR_PROG_MAC_ADDR);
499
500
501 while ((in_be32(addr + XEL_TSR_OFFSET) &
502 XEL_TSR_PROG_MAC_ADDR) != 0)
503 ;
504}
505
506
507
508
509
510
511
512
513
514
515
516
517static int xemaclite_set_mac_address(struct net_device *dev, void *address)
518{
519 struct net_local *lp = netdev_priv(dev);
520 struct sockaddr *addr = address;
521
522 if (netif_running(dev))
523 return -EBUSY;
524
525 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
526 xemaclite_update_address(lp, dev->dev_addr);
527 return 0;
528}
529
530
531
532
533
534
535
536static void xemaclite_tx_timeout(struct net_device *dev)
537{
538 struct net_local *lp = netdev_priv(dev);
539 unsigned long flags;
540
541 dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n",
542 TX_TIMEOUT * 1000UL / HZ);
543
544 dev->stats.tx_errors++;
545
546
547 spin_lock_irqsave(&lp->reset_lock, flags);
548
549
550 netif_stop_queue(dev);
551
552 xemaclite_disable_interrupts(lp);
553 xemaclite_enable_interrupts(lp);
554
555 if (lp->deferred_skb) {
556 dev_kfree_skb(lp->deferred_skb);
557 lp->deferred_skb = NULL;
558 dev->stats.tx_errors++;
559 }
560
561
562 dev->trans_start = jiffies;
563
564
565 netif_wake_queue(dev);
566 spin_unlock_irqrestore(&lp->reset_lock, flags);
567}
568
569
570
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572
573
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575
576
577
578
579
580static void xemaclite_tx_handler(struct net_device *dev)
581{
582 struct net_local *lp = netdev_priv(dev);
583
584 dev->stats.tx_packets++;
585 if (lp->deferred_skb) {
586 if (xemaclite_send_data(lp,
587 (u8 *) lp->deferred_skb->data,
588 lp->deferred_skb->len) != 0)
589 return;
590 else {
591 dev->stats.tx_bytes += lp->deferred_skb->len;
592 dev_kfree_skb_irq(lp->deferred_skb);
593 lp->deferred_skb = NULL;
594 dev->trans_start = jiffies;
595 netif_wake_queue(dev);
596 }
597 }
598}
599
600
601
602
603
604
605
606
607static void xemaclite_rx_handler(struct net_device *dev)
608{
609 struct net_local *lp = netdev_priv(dev);
610 struct sk_buff *skb;
611 unsigned int align;
612 u32 len;
613
614 len = ETH_FRAME_LEN + ETH_FCS_LEN;
615 skb = dev_alloc_skb(len + ALIGNMENT);
616 if (!skb) {
617
618 dev->stats.rx_dropped++;
619 dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n");
620 return;
621 }
622
623
624
625
626
627
628 align = BUFFER_ALIGN(skb->data);
629 if (align)
630 skb_reserve(skb, align);
631
632 skb_reserve(skb, 2);
633
634 len = xemaclite_recv_data(lp, (u8 *) skb->data);
635
636 if (!len) {
637 dev->stats.rx_errors++;
638 dev_kfree_skb_irq(skb);
639 return;
640 }
641
642 skb_put(skb, len);
643
644 skb->protocol = eth_type_trans(skb, dev);
645 skb_checksum_none_assert(skb);
646
647 dev->stats.rx_packets++;
648 dev->stats.rx_bytes += len;
649
650 netif_rx(skb);
651}
652
653
654
655
656
657
658
659
660
661static irqreturn_t xemaclite_interrupt(int irq, void *dev_id)
662{
663 bool tx_complete = 0;
664 struct net_device *dev = dev_id;
665 struct net_local *lp = netdev_priv(dev);
666 void __iomem *base_addr = lp->base_addr;
667 u32 tx_status;
668
669
670 if ((in_be32(base_addr + XEL_RSR_OFFSET) & XEL_RSR_RECV_DONE_MASK) ||
671 (in_be32(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)
672 & XEL_RSR_RECV_DONE_MASK))
673
674 xemaclite_rx_handler(dev);
675
676
677 tx_status = in_be32(base_addr + XEL_TSR_OFFSET);
678 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
679 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
680
681 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
682 out_be32(base_addr + XEL_TSR_OFFSET, tx_status);
683
684 tx_complete = 1;
685 }
686
687
688 tx_status = in_be32(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
689 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
690 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
691
692 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
693 out_be32(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET,
694 tx_status);
695
696 tx_complete = 1;
697 }
698
699
700 if (tx_complete != 0)
701 xemaclite_tx_handler(dev);
702
703 return IRQ_HANDLED;
704}
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720static int xemaclite_mdio_wait(struct net_local *lp)
721{
722 long end = jiffies + 2;
723
724
725
726
727 while (in_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET) &
728 XEL_MDIOCTRL_MDIOSTS_MASK) {
729 if (end - jiffies <= 0) {
730 WARN_ON(1);
731 return -ETIMEDOUT;
732 }
733 msleep(1);
734 }
735 return 0;
736}
737
738
739
740
741
742
743
744
745
746
747
748
749
750static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg)
751{
752 struct net_local *lp = bus->priv;
753 u32 ctrl_reg;
754 u32 rc;
755
756 if (xemaclite_mdio_wait(lp))
757 return -ETIMEDOUT;
758
759
760
761
762
763 ctrl_reg = in_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET);
764 out_be32(lp->base_addr + XEL_MDIOADDR_OFFSET,
765 XEL_MDIOADDR_OP_MASK |
766 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg));
767 out_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET,
768 ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
769
770 if (xemaclite_mdio_wait(lp))
771 return -ETIMEDOUT;
772
773 rc = in_be32(lp->base_addr + XEL_MDIORD_OFFSET);
774
775 dev_dbg(&lp->ndev->dev,
776 "xemaclite_mdio_read(phy_id=%i, reg=%x) == %x\n",
777 phy_id, reg, rc);
778
779 return rc;
780}
781
782
783
784
785
786
787
788
789
790
791
792static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg,
793 u16 val)
794{
795 struct net_local *lp = bus->priv;
796 u32 ctrl_reg;
797
798 dev_dbg(&lp->ndev->dev,
799 "xemaclite_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
800 phy_id, reg, val);
801
802 if (xemaclite_mdio_wait(lp))
803 return -ETIMEDOUT;
804
805
806
807
808
809
810 ctrl_reg = in_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET);
811 out_be32(lp->base_addr + XEL_MDIOADDR_OFFSET,
812 ~XEL_MDIOADDR_OP_MASK &
813 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg));
814 out_be32(lp->base_addr + XEL_MDIOWR_OFFSET, val);
815 out_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET,
816 ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
817
818 return 0;
819}
820
821
822
823
824
825
826
827
828static int xemaclite_mdio_reset(struct mii_bus *bus)
829{
830 return 0;
831}
832
833
834
835
836
837
838
839
840
841
842
843static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev)
844{
845 struct mii_bus *bus;
846 int rc;
847 struct resource res;
848 struct device_node *np = of_get_parent(lp->phy_node);
849
850
851
852
853 if (!np)
854 return -ENODEV;
855
856
857
858
859 out_be32(lp->base_addr + XEL_MDIOCTRL_OFFSET,
860 XEL_MDIOCTRL_MDIOEN_MASK);
861
862 bus = mdiobus_alloc();
863 if (!bus)
864 return -ENOMEM;
865
866 of_address_to_resource(np, 0, &res);
867 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
868 (unsigned long long)res.start);
869 bus->priv = lp;
870 bus->name = "Xilinx Emaclite MDIO";
871 bus->read = xemaclite_mdio_read;
872 bus->write = xemaclite_mdio_write;
873 bus->reset = xemaclite_mdio_reset;
874 bus->parent = dev;
875 bus->irq = lp->mdio_irqs;
876
877 lp->mii_bus = bus;
878
879 rc = of_mdiobus_register(bus, np);
880 if (rc)
881 goto err_register;
882
883 return 0;
884
885err_register:
886 mdiobus_free(bus);
887 return rc;
888}
889
890
891
892
893
894
895
896
897void xemaclite_adjust_link(struct net_device *ndev)
898{
899 struct net_local *lp = netdev_priv(ndev);
900 struct phy_device *phy = lp->phy_dev;
901 int link_state;
902
903
904 link_state = phy->speed | (phy->duplex << 1) | phy->link;
905
906 if (lp->last_link != link_state) {
907 lp->last_link = link_state;
908 phy_print_status(phy);
909 }
910}
911
912
913
914
915
916
917
918
919
920static int xemaclite_open(struct net_device *dev)
921{
922 struct net_local *lp = netdev_priv(dev);
923 int retval;
924
925
926 xemaclite_disable_interrupts(lp);
927
928 if (lp->phy_node) {
929 u32 bmcr;
930
931 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
932 xemaclite_adjust_link, 0,
933 PHY_INTERFACE_MODE_MII);
934 if (!lp->phy_dev) {
935 dev_err(&lp->ndev->dev, "of_phy_connect() failed\n");
936 return -ENODEV;
937 }
938
939
940 lp->phy_dev->supported &= (PHY_BASIC_FEATURES);
941 lp->phy_dev->advertising = lp->phy_dev->supported;
942
943
944 phy_write(lp->phy_dev, MII_CTRL1000, 0);
945
946
947 phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL);
948
949
950 bmcr = phy_read(lp->phy_dev, MII_BMCR);
951 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
952 phy_write(lp->phy_dev, MII_BMCR, bmcr);
953
954 phy_start(lp->phy_dev);
955 }
956
957
958 xemaclite_update_address(lp, dev->dev_addr);
959
960
961 retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev);
962 if (retval) {
963 dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n",
964 dev->irq);
965 if (lp->phy_dev)
966 phy_disconnect(lp->phy_dev);
967 lp->phy_dev = NULL;
968
969 return retval;
970 }
971
972
973 xemaclite_enable_interrupts(lp);
974
975
976 netif_start_queue(dev);
977
978 return 0;
979}
980
981
982
983
984
985
986
987
988
989static int xemaclite_close(struct net_device *dev)
990{
991 struct net_local *lp = netdev_priv(dev);
992
993 netif_stop_queue(dev);
994 xemaclite_disable_interrupts(lp);
995 free_irq(dev->irq, dev);
996
997 if (lp->phy_dev)
998 phy_disconnect(lp->phy_dev);
999 lp->phy_dev = NULL;
1000
1001 return 0;
1002}
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018static int xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev)
1019{
1020 struct net_local *lp = netdev_priv(dev);
1021 struct sk_buff *new_skb;
1022 unsigned int len;
1023 unsigned long flags;
1024
1025 len = orig_skb->len;
1026
1027 new_skb = orig_skb;
1028
1029 spin_lock_irqsave(&lp->reset_lock, flags);
1030 if (xemaclite_send_data(lp, (u8 *) new_skb->data, len) != 0) {
1031
1032
1033
1034 netif_stop_queue(dev);
1035 lp->deferred_skb = new_skb;
1036 spin_unlock_irqrestore(&lp->reset_lock, flags);
1037 return 0;
1038 }
1039 spin_unlock_irqrestore(&lp->reset_lock, flags);
1040
1041 dev->stats.tx_bytes += len;
1042 dev_kfree_skb(new_skb);
1043
1044 return 0;
1045}
1046
1047
1048
1049
1050
1051
1052
1053
1054static void xemaclite_remove_ndev(struct net_device *ndev)
1055{
1056 if (ndev) {
1057 struct net_local *lp = netdev_priv(ndev);
1058
1059 if (lp->base_addr)
1060 iounmap((void __iomem __force *) (lp->base_addr));
1061 free_netdev(ndev);
1062 }
1063}
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075static bool get_bool(struct platform_device *ofdev, const char *s)
1076{
1077 u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL);
1078
1079 if (p) {
1080 return (bool)*p;
1081 } else {
1082 dev_warn(&ofdev->dev, "Parameter %s not found,"
1083 "defaulting to false\n", s);
1084 return 0;
1085 }
1086}
1087
1088static struct net_device_ops xemaclite_netdev_ops;
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104static int __devinit xemaclite_of_probe(struct platform_device *ofdev,
1105 const struct of_device_id *match)
1106{
1107 struct resource r_irq;
1108 struct resource r_mem;
1109 struct net_device *ndev = NULL;
1110 struct net_local *lp = NULL;
1111 struct device *dev = &ofdev->dev;
1112 const void *mac_address;
1113
1114 int rc = 0;
1115
1116 dev_info(dev, "Device Tree Probing\n");
1117
1118
1119 rc = of_address_to_resource(ofdev->dev.of_node, 0, &r_mem);
1120 if (rc) {
1121 dev_err(dev, "invalid address\n");
1122 return rc;
1123 }
1124
1125
1126 rc = of_irq_to_resource(ofdev->dev.of_node, 0, &r_irq);
1127 if (rc == NO_IRQ) {
1128 dev_err(dev, "no IRQ found\n");
1129 return rc;
1130 }
1131
1132
1133 ndev = alloc_etherdev(sizeof(struct net_local));
1134 if (!ndev) {
1135 dev_err(dev, "Could not allocate network device\n");
1136 return -ENOMEM;
1137 }
1138
1139 dev_set_drvdata(dev, ndev);
1140 SET_NETDEV_DEV(ndev, &ofdev->dev);
1141
1142 ndev->irq = r_irq.start;
1143 ndev->mem_start = r_mem.start;
1144 ndev->mem_end = r_mem.end;
1145
1146 lp = netdev_priv(ndev);
1147 lp->ndev = ndev;
1148
1149 if (!request_mem_region(ndev->mem_start,
1150 ndev->mem_end - ndev->mem_start + 1,
1151 DRIVER_NAME)) {
1152 dev_err(dev, "Couldn't lock memory region at %p\n",
1153 (void *)ndev->mem_start);
1154 rc = -EBUSY;
1155 goto error2;
1156 }
1157
1158
1159 lp->base_addr = ioremap(r_mem.start, resource_size(&r_mem));
1160 if (NULL == lp->base_addr) {
1161 dev_err(dev, "EmacLite: Could not allocate iomem\n");
1162 rc = -EIO;
1163 goto error1;
1164 }
1165
1166 spin_lock_init(&lp->reset_lock);
1167 lp->next_tx_buf_to_use = 0x0;
1168 lp->next_rx_buf_to_use = 0x0;
1169 lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong");
1170 lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong");
1171 mac_address = of_get_mac_address(ofdev->dev.of_node);
1172
1173 if (mac_address)
1174
1175 memcpy(ndev->dev_addr, mac_address, 6);
1176 else
1177 dev_warn(dev, "No MAC address found\n");
1178
1179
1180 out_be32(lp->base_addr + XEL_TSR_OFFSET, 0);
1181 out_be32(lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET, 0);
1182
1183
1184 xemaclite_update_address(lp, ndev->dev_addr);
1185
1186 lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0);
1187 rc = xemaclite_mdio_setup(lp, &ofdev->dev);
1188 if (rc)
1189 dev_warn(&ofdev->dev, "error registering MDIO bus\n");
1190
1191 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr);
1192
1193 ndev->netdev_ops = &xemaclite_netdev_ops;
1194 ndev->flags &= ~IFF_MULTICAST;
1195 ndev->watchdog_timeo = TX_TIMEOUT;
1196
1197
1198 rc = register_netdev(ndev);
1199 if (rc) {
1200 dev_err(dev,
1201 "Cannot register network device, aborting\n");
1202 goto error1;
1203 }
1204
1205 dev_info(dev,
1206 "Xilinx EmacLite at 0x%08X mapped to 0x%08X, irq=%d\n",
1207 (unsigned int __force)ndev->mem_start,
1208 (unsigned int __force)lp->base_addr, ndev->irq);
1209 return 0;
1210
1211error1:
1212 release_mem_region(ndev->mem_start, resource_size(&r_mem));
1213
1214error2:
1215 xemaclite_remove_ndev(ndev);
1216 return rc;
1217}
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229static int __devexit xemaclite_of_remove(struct platform_device *of_dev)
1230{
1231 struct device *dev = &of_dev->dev;
1232 struct net_device *ndev = dev_get_drvdata(dev);
1233
1234 struct net_local *lp = netdev_priv(ndev);
1235
1236
1237 if (lp->has_mdio) {
1238 mdiobus_unregister(lp->mii_bus);
1239 kfree(lp->mii_bus->irq);
1240 mdiobus_free(lp->mii_bus);
1241 lp->mii_bus = NULL;
1242 }
1243
1244 unregister_netdev(ndev);
1245
1246 if (lp->phy_node)
1247 of_node_put(lp->phy_node);
1248 lp->phy_node = NULL;
1249
1250 release_mem_region(ndev->mem_start, ndev->mem_end-ndev->mem_start + 1);
1251
1252 xemaclite_remove_ndev(ndev);
1253 dev_set_drvdata(dev, NULL);
1254
1255 return 0;
1256}
1257
1258#ifdef CONFIG_NET_POLL_CONTROLLER
1259static void
1260xemaclite_poll_controller(struct net_device *ndev)
1261{
1262 disable_irq(ndev->irq);
1263 xemaclite_interrupt(ndev->irq, ndev);
1264 enable_irq(ndev->irq);
1265}
1266#endif
1267
1268static struct net_device_ops xemaclite_netdev_ops = {
1269 .ndo_open = xemaclite_open,
1270 .ndo_stop = xemaclite_close,
1271 .ndo_start_xmit = xemaclite_send,
1272 .ndo_set_mac_address = xemaclite_set_mac_address,
1273 .ndo_tx_timeout = xemaclite_tx_timeout,
1274#ifdef CONFIG_NET_POLL_CONTROLLER
1275 .ndo_poll_controller = xemaclite_poll_controller,
1276#endif
1277};
1278
1279
1280static struct of_device_id xemaclite_of_match[] __devinitdata = {
1281 { .compatible = "xlnx,opb-ethernetlite-1.01.a", },
1282 { .compatible = "xlnx,opb-ethernetlite-1.01.b", },
1283 { .compatible = "xlnx,xps-ethernetlite-1.00.a", },
1284 { .compatible = "xlnx,xps-ethernetlite-2.00.a", },
1285 { .compatible = "xlnx,xps-ethernetlite-2.01.a", },
1286 { .compatible = "xlnx,xps-ethernetlite-3.00.a", },
1287 { },
1288};
1289MODULE_DEVICE_TABLE(of, xemaclite_of_match);
1290
1291static struct of_platform_driver xemaclite_of_driver = {
1292 .driver = {
1293 .name = DRIVER_NAME,
1294 .owner = THIS_MODULE,
1295 .of_match_table = xemaclite_of_match,
1296 },
1297 .probe = xemaclite_of_probe,
1298 .remove = __devexit_p(xemaclite_of_remove),
1299};
1300
1301
1302
1303
1304
1305
1306static int __init xemaclite_init(void)
1307{
1308
1309 return of_register_platform_driver(&xemaclite_of_driver);
1310}
1311
1312
1313
1314
1315static void __exit xemaclite_cleanup(void)
1316{
1317 of_unregister_platform_driver(&xemaclite_of_driver);
1318}
1319
1320module_init(xemaclite_init);
1321module_exit(xemaclite_cleanup);
1322
1323MODULE_AUTHOR("Xilinx, Inc.");
1324MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver");
1325MODULE_LICENSE("GPL");
1326