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18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/acpi.h>
24#include <linux/kallsyms.h>
25#include <linux/dmi.h>
26#include <linux/pci-aspm.h>
27#include <linux/ioport.h>
28#include <asm/dma.h>
29#include "pci.h"
30
31
32
33
34
35
36
37
38static void __devinit quirk_resource_alignment(struct pci_dev *dev)
39{
40 int i;
41 struct resource *r;
42 resource_size_t align, size;
43 u16 command;
44
45 if (!pci_is_reassigndev(dev))
46 return;
47
48 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
49 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
50 dev_warn(&dev->dev,
51 "Can't reassign resources to host bridge.\n");
52 return;
53 }
54
55 dev_info(&dev->dev,
56 "Disabling memory decoding and releasing memory resources.\n");
57 pci_read_config_word(dev, PCI_COMMAND, &command);
58 command &= ~PCI_COMMAND_MEMORY;
59 pci_write_config_word(dev, PCI_COMMAND, command);
60
61 align = pci_specified_resource_alignment(dev);
62 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
63 r = &dev->resource[i];
64 if (!(r->flags & IORESOURCE_MEM))
65 continue;
66 size = resource_size(r);
67 if (size < align) {
68 size = align;
69 dev_info(&dev->dev,
70 "Rounding up size of resource #%d to %#llx.\n",
71 i, (unsigned long long)size);
72 }
73 r->end = size - 1;
74 r->start = 0;
75 }
76
77
78
79
80 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
81 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
82 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
83 r = &dev->resource[i];
84 if (!(r->flags & IORESOURCE_MEM))
85 continue;
86 r->end = resource_size(r) - 1;
87 r->start = 0;
88 }
89 pci_disable_bridge_window(dev);
90 }
91}
92DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
93
94
95
96
97
98
99
100static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
101{
102 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
103 dev->mmio_always_on = 1;
104}
105DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on);
106
107
108
109
110
111static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
112{
113 dev->broken_parity_status = 1;
114}
115DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
116DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
117
118
119
120static void quirk_passive_release(struct pci_dev *dev)
121{
122 struct pci_dev *d = NULL;
123 unsigned char dlc;
124
125
126
127 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
128 pci_read_config_byte(d, 0x82, &dlc);
129 if (!(dlc & 1<<1)) {
130 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
131 dlc |= 1<<1;
132 pci_write_config_byte(d, 0x82, dlc);
133 }
134 }
135}
136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
137DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
138
139
140
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142
143
144
145
146static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
147{
148 if (!isa_dma_bridge_buggy) {
149 isa_dma_bridge_buggy=1;
150 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
151 }
152}
153
154
155
156
157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
164
165
166
167
168
169static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
170{
171 u32 pmbase;
172 u16 pm1a;
173
174 pci_read_config_dword(dev, 0x40, &pmbase);
175 pmbase = pmbase & 0xff80;
176 pm1a = inw(pmbase);
177
178 if (pm1a & 0x10) {
179 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
180 outw(0x10, pmbase);
181 }
182}
183DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
184
185
186
187
188static void __devinit quirk_nopcipci(struct pci_dev *dev)
189{
190 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
191 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
192 pci_pci_problems |= PCIPCI_FAIL;
193 }
194}
195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
197
198static void __devinit quirk_nopciamd(struct pci_dev *dev)
199{
200 u8 rev;
201 pci_read_config_byte(dev, 0x08, &rev);
202 if (rev == 0x13) {
203
204 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
205 pci_pci_problems |= PCIAGP_FAIL;
206 }
207}
208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
209
210
211
212
213static void __devinit quirk_triton(struct pci_dev *dev)
214{
215 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
216 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
217 pci_pci_problems |= PCIPCI_TRITON;
218 }
219}
220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
224
225
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233
234
235
236static void quirk_vialatency(struct pci_dev *dev)
237{
238 struct pci_dev *p;
239 u8 busarb;
240
241
242
243 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
244 if (p!=NULL) {
245
246
247 if (p->revision < 0x40 || p->revision > 0x42)
248 goto exit;
249 } else {
250 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
251 if (p==NULL)
252 goto exit;
253
254 if (p->revision < 0x10 || p->revision > 0x12)
255 goto exit;
256 }
257
258
259
260
261
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267
268
269
270
271 pci_read_config_byte(dev, 0x76, &busarb);
272
273
274 busarb &= ~(1<<5);
275 busarb |= (1<<4);
276 pci_write_config_byte(dev, 0x76, busarb);
277 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
278exit:
279 pci_dev_put(p);
280}
281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
283DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
284
285DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
286DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
287DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
288
289
290
291
292static void __devinit quirk_viaetbf(struct pci_dev *dev)
293{
294 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
295 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
296 pci_pci_problems |= PCIPCI_VIAETBF;
297 }
298}
299DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
300
301static void __devinit quirk_vsfx(struct pci_dev *dev)
302{
303 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
304 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
305 pci_pci_problems |= PCIPCI_VSFX;
306 }
307}
308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
309
310
311
312
313
314
315
316static void __init quirk_alimagik(struct pci_dev *dev)
317{
318 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
319 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
320 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
321 }
322}
323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
325
326
327
328
329
330static void __devinit quirk_natoma(struct pci_dev *dev)
331{
332 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
333 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
334 pci_pci_problems |= PCIPCI_NATOMA;
335 }
336}
337DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
338DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
339DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
340DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
341DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
342DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
343
344
345
346
347
348static void __devinit quirk_citrine(struct pci_dev *dev)
349{
350 dev->cfg_size = 0xA0;
351}
352DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
353
354
355
356
357
358static void __devinit quirk_s3_64M(struct pci_dev *dev)
359{
360 struct resource *r = &dev->resource[0];
361
362 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
363 r->start = 0;
364 r->end = 0x3ffffff;
365 }
366}
367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
369
370
371
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373
374
375
376static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
377{
378 if (pci_resource_len(dev, 0) != 8) {
379 struct resource *res = &dev->resource[0];
380 res->end = res->start + 8 - 1;
381 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
382 "(incorrect header); workaround applied.\n");
383 }
384}
385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
386
387static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
388 unsigned size, int nr, const char *name)
389{
390 region &= ~(size-1);
391 if (region) {
392 struct pci_bus_region bus_region;
393 struct resource *res = dev->resource + nr;
394
395 res->name = pci_name(dev);
396 res->start = region;
397 res->end = region + size - 1;
398 res->flags = IORESOURCE_IO;
399
400
401 bus_region.start = res->start;
402 bus_region.end = res->end;
403 pcibios_bus_to_resource(dev, res, &bus_region);
404
405 if (pci_claim_resource(dev, nr) == 0)
406 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
407 res, name);
408 }
409}
410
411
412
413
414
415static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
416{
417 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
418
419 request_region(0x3b0, 0x0C, "RadeonIGP");
420 request_region(0x3d3, 0x01, "RadeonIGP");
421}
422DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
423
424
425
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428
429
430
431
432
433
434
435static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
436{
437 u16 region;
438
439 pci_read_config_word(dev, 0xE0, ®ion);
440 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
441 pci_read_config_word(dev, 0xE2, ®ion);
442 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
443}
444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
445
446static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
447{
448 u32 devres;
449 u32 mask, size, base;
450
451 pci_read_config_dword(dev, port, &devres);
452 if ((devres & enable) != enable)
453 return;
454 mask = (devres >> 16) & 15;
455 base = devres & 0xffff;
456 size = 16;
457 for (;;) {
458 unsigned bit = size >> 1;
459 if ((bit & mask) == bit)
460 break;
461 size = bit;
462 }
463
464
465
466
467
468 base &= -size;
469 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
470}
471
472static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
473{
474 u32 devres;
475 u32 mask, size, base;
476
477 pci_read_config_dword(dev, port, &devres);
478 if ((devres & enable) != enable)
479 return;
480 base = devres & 0xffff0000;
481 mask = (devres & 0x3f) << 16;
482 size = 128 << 16;
483 for (;;) {
484 unsigned bit = size >> 1;
485 if ((bit & mask) == bit)
486 break;
487 size = bit;
488 }
489
490
491
492
493 base &= -size;
494 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
495}
496
497
498
499
500
501
502
503static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
504{
505 u32 region, res_a;
506
507 pci_read_config_dword(dev, 0x40, ®ion);
508 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
509 pci_read_config_dword(dev, 0x90, ®ion);
510 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
511
512
513 pci_read_config_dword(dev, 0x5c, &res_a);
514
515 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
516 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
517
518
519
520
521 if (res_a & (1 << 29)) {
522 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
523 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
524 }
525
526 if (res_a & (1 << 30)) {
527 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
528 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
529 }
530 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
531 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
532}
533DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
534DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
535
536
537
538
539
540
541static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
542{
543 u32 region;
544
545 pci_read_config_dword(dev, 0x40, ®ion);
546 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
547
548 pci_read_config_dword(dev, 0x58, ®ion);
549 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
550}
551DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
552DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
553DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
554DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
555DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
556DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
557DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
558DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
559DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
560DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
561
562static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
563{
564 u32 region;
565
566 pci_read_config_dword(dev, 0x40, ®ion);
567 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
568
569 pci_read_config_dword(dev, 0x48, ®ion);
570 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
571}
572
573static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
574{
575 u32 val;
576 u32 size, base;
577
578 pci_read_config_dword(dev, reg, &val);
579
580
581 if (!(val & 1))
582 return;
583 base = val & 0xfffc;
584 if (dynsize) {
585
586
587
588
589
590
591 size = 16;
592 } else {
593 size = 128;
594 }
595 base &= ~(size-1);
596
597
598 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
599}
600
601static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
602{
603
604 ich6_lpc_acpi_gpio(dev);
605
606
607 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
608 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
609}
610DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
611DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
612
613static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
614{
615 u32 val;
616 u32 mask, base;
617
618 pci_read_config_dword(dev, reg, &val);
619
620
621 if (!(val & 1))
622 return;
623
624
625
626
627
628 base = val & 0xfffc;
629 mask = (val >> 16) & 0xfc;
630 mask |= 3;
631
632
633 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
634}
635
636
637static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
638{
639
640 ich6_lpc_acpi_gpio(dev);
641
642
643 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
644 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
645 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
646 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
647}
648DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
649DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
650DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
651DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
652DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
653DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
654DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
655DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
656DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
657DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
659DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
660DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
661
662
663
664
665
666static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
667{
668 u32 region;
669
670 if (dev->revision & 0x10) {
671 pci_read_config_dword(dev, 0x48, ®ion);
672 region &= PCI_BASE_ADDRESS_IO_MASK;
673 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
674 }
675}
676DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
677
678
679
680
681
682
683
684static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
685{
686 u16 hm;
687 u32 smb;
688
689 quirk_vt82c586_acpi(dev);
690
691 pci_read_config_word(dev, 0x70, &hm);
692 hm &= PCI_BASE_ADDRESS_IO_MASK;
693 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
694
695 pci_read_config_dword(dev, 0x90, &smb);
696 smb &= PCI_BASE_ADDRESS_IO_MASK;
697 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
698}
699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
700
701
702
703
704
705
706static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
707{
708 u16 pm, smb;
709
710 pci_read_config_word(dev, 0x88, &pm);
711 pm &= PCI_BASE_ADDRESS_IO_MASK;
712 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
713
714 pci_read_config_word(dev, 0xd0, &smb);
715 smb &= PCI_BASE_ADDRESS_IO_MASK;
716 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
717}
718DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
719
720
721
722
723
724static void __devinit quirk_xio2000a(struct pci_dev *dev)
725{
726 struct pci_dev *pdev;
727 u16 command;
728
729 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
730 "secondary bus fast back-to-back transfers disabled\n");
731 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
732 pci_read_config_word(pdev, PCI_COMMAND, &command);
733 if (command & PCI_COMMAND_FAST_BACK)
734 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
735 }
736}
737DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
738 quirk_xio2000a);
739
740#ifdef CONFIG_X86_IO_APIC
741
742#include <asm/io_apic.h>
743
744
745
746
747
748
749
750
751static void quirk_via_ioapic(struct pci_dev *dev)
752{
753 u8 tmp;
754
755 if (nr_ioapics < 1)
756 tmp = 0;
757 else
758 tmp = 0x1f;
759
760 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
761 tmp == 0 ? "Disa" : "Ena");
762
763
764 pci_write_config_byte (dev, 0x58, tmp);
765}
766DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
767DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
768
769
770
771
772
773
774
775static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
776{
777 u8 misc_control2;
778#define BYPASS_APIC_DEASSERT 8
779
780 pci_read_config_byte(dev, 0x5B, &misc_control2);
781 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
782 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
783 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
784 }
785}
786DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
787DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
788
789
790
791
792
793
794
795
796
797
798static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
799{
800 if (dev->revision >= 0x02) {
801 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
802 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
803 }
804}
805DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
806
807static void __init quirk_ioapic_rmw(struct pci_dev *dev)
808{
809 if (dev->devfn == 0 && dev->bus->number == 0)
810 sis_apic_bug = 1;
811}
812DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
813#endif
814
815
816
817
818
819static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
820{
821 if (dev->subordinate && dev->revision <= 0x12) {
822 dev_info(&dev->dev, "AMD8131 rev %x detected; "
823 "disabling PCI-X MMRBC\n", dev->revision);
824 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
825 }
826}
827DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
828
829
830
831
832
833
834
835
836
837static void __devinit quirk_via_acpi(struct pci_dev *d)
838{
839
840
841
842 u8 irq;
843 pci_read_config_byte(d, 0x42, &irq);
844 irq &= 0xf;
845 if (irq && (irq != 2))
846 d->irq = irq;
847}
848DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
849DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
850
851
852
853
854
855
856static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
857
858static void quirk_via_bridge(struct pci_dev *dev)
859{
860
861 switch (dev->device) {
862 case PCI_DEVICE_ID_VIA_82C686:
863
864
865
866 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
867 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
868 break;
869 case PCI_DEVICE_ID_VIA_8237:
870 case PCI_DEVICE_ID_VIA_8237A:
871 via_vlink_dev_lo = 15;
872 break;
873 case PCI_DEVICE_ID_VIA_8235:
874 via_vlink_dev_lo = 16;
875 break;
876 case PCI_DEVICE_ID_VIA_8231:
877 case PCI_DEVICE_ID_VIA_8233_0:
878 case PCI_DEVICE_ID_VIA_8233A:
879 case PCI_DEVICE_ID_VIA_8233C_0:
880 via_vlink_dev_lo = 17;
881 break;
882 }
883}
884DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
885DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
886DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
888DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
889DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
890DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
891DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906static void quirk_via_vlink(struct pci_dev *dev)
907{
908 u8 irq, new_irq;
909
910
911 if (via_vlink_dev_lo == -1)
912 return;
913
914 new_irq = dev->irq;
915
916
917 if (!new_irq || new_irq > 15)
918 return;
919
920
921 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
922 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
923 return;
924
925
926
927
928 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
929 if (new_irq != irq) {
930 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
931 irq, new_irq);
932 udelay(15);
933 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
934 }
935}
936DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
937
938
939
940
941
942
943
944static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
945{
946 pci_write_config_byte(dev, 0xfc, 0);
947 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
948}
949DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
950
951
952
953
954
955
956
957static void quirk_cardbus_legacy(struct pci_dev *dev)
958{
959 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
960 return;
961 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
962}
963DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
964DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
965
966
967
968
969
970
971
972
973static void quirk_amd_ordering(struct pci_dev *dev)
974{
975 u32 pcic;
976 pci_read_config_dword(dev, 0x4C, &pcic);
977 if ((pcic&6)!=6) {
978 pcic |= 6;
979 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
980 pci_write_config_dword(dev, 0x4C, pcic);
981 pci_read_config_dword(dev, 0x84, &pcic);
982 pcic |= (1<<23);
983 pci_write_config_dword(dev, 0x84, pcic);
984 }
985}
986DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
987DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
988
989
990
991
992
993
994
995
996static void __devinit quirk_dunord ( struct pci_dev * dev )
997{
998 struct resource *r = &dev->resource [1];
999 r->start = 0;
1000 r->end = 0xffffff;
1001}
1002DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1003
1004
1005
1006
1007
1008
1009
1010static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
1011{
1012 dev->transparent = 1;
1013}
1014DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1015DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1016
1017
1018
1019
1020
1021
1022
1023static void quirk_mediagx_master(struct pci_dev *dev)
1024{
1025 u8 reg;
1026 pci_read_config_byte(dev, 0x41, ®);
1027 if (reg & 2) {
1028 reg &= ~2;
1029 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1030 pci_write_config_byte(dev, 0x41, reg);
1031 }
1032}
1033DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1034DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1035
1036
1037
1038
1039
1040
1041static void quirk_disable_pxb(struct pci_dev *pdev)
1042{
1043 u16 config;
1044
1045 if (pdev->revision != 0x04)
1046 return;
1047 pci_read_config_word(pdev, 0x40, &config);
1048 if (config & (1<<6)) {
1049 config &= ~(1<<6);
1050 pci_write_config_word(pdev, 0x40, config);
1051 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1052 }
1053}
1054DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1055DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1056
1057static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
1058{
1059
1060 u8 tmp;
1061
1062 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1063 if (tmp == 0x01) {
1064 pci_read_config_byte(pdev, 0x40, &tmp);
1065 pci_write_config_byte(pdev, 0x40, tmp|1);
1066 pci_write_config_byte(pdev, 0x9, 1);
1067 pci_write_config_byte(pdev, 0xa, 6);
1068 pci_write_config_byte(pdev, 0x40, tmp);
1069
1070 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1071 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1072 }
1073}
1074DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1075DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1076DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1077DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1078DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1079DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1080
1081
1082
1083
1084static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1085{
1086 u8 prog;
1087 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1088 if (prog & 5) {
1089 prog &= ~5;
1090 pdev->class &= ~5;
1091 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1092
1093 }
1094}
1095DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1096
1097
1098
1099
1100static void __init quirk_ide_samemode(struct pci_dev *pdev)
1101{
1102 u8 prog;
1103
1104 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1105
1106 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1107 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1108 prog &= ~5;
1109 pdev->class &= ~5;
1110 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1111 }
1112}
1113DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1114
1115
1116
1117
1118
1119static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1120{
1121
1122 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1123 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1124}
1125DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1126DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
1127
1128DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1129
1130
1131DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
1132
1133
1134
1135
1136static void __init quirk_eisa_bridge(struct pci_dev *dev)
1137{
1138 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1139}
1140DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168static int asus_hides_smbus;
1169
1170static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1171{
1172 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1173 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1174 switch(dev->subsystem_device) {
1175 case 0x8025:
1176 case 0x8070:
1177 case 0x8088:
1178 case 0x1626:
1179 asus_hides_smbus = 1;
1180 }
1181 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1182 switch(dev->subsystem_device) {
1183 case 0x80b1:
1184 case 0x80b2:
1185 case 0x8093:
1186 asus_hides_smbus = 1;
1187 }
1188 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1189 switch(dev->subsystem_device) {
1190 case 0x8030:
1191 asus_hides_smbus = 1;
1192 }
1193 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1194 switch (dev->subsystem_device) {
1195 case 0x8070:
1196 asus_hides_smbus = 1;
1197 }
1198 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1199 switch (dev->subsystem_device) {
1200 case 0x80c9:
1201 asus_hides_smbus = 1;
1202 }
1203 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1204 switch (dev->subsystem_device) {
1205 case 0x1751:
1206 case 0x1821:
1207 case 0x1897:
1208 asus_hides_smbus = 1;
1209 }
1210 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1211 switch (dev->subsystem_device) {
1212 case 0x184b:
1213 case 0x186a:
1214 asus_hides_smbus = 1;
1215 }
1216 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1217 switch (dev->subsystem_device) {
1218 case 0x80f2:
1219 asus_hides_smbus = 1;
1220 }
1221 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1222 switch (dev->subsystem_device) {
1223 case 0x1882:
1224 case 0x1977:
1225 asus_hides_smbus = 1;
1226 }
1227 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1228 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1229 switch(dev->subsystem_device) {
1230 case 0x088C:
1231 case 0x0890:
1232 asus_hides_smbus = 1;
1233 }
1234 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1235 switch (dev->subsystem_device) {
1236 case 0x12bc:
1237 case 0x12bd:
1238 case 0x006a:
1239 asus_hides_smbus = 1;
1240 }
1241 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1242 switch (dev->subsystem_device) {
1243 case 0x12bf:
1244 asus_hides_smbus = 1;
1245 }
1246 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1247 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1248 switch(dev->subsystem_device) {
1249 case 0xC00C:
1250 asus_hides_smbus = 1;
1251 }
1252 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1253 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1254 switch(dev->subsystem_device) {
1255 case 0x0058:
1256 asus_hides_smbus = 1;
1257 }
1258 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1259 switch(dev->subsystem_device) {
1260 case 0xB16C:
1261
1262
1263
1264 asus_hides_smbus = 1;
1265 }
1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1267 switch(dev->subsystem_device) {
1268 case 0x00b8:
1269 case 0x00b9:
1270 case 0x00ba:
1271
1272
1273
1274
1275
1276 asus_hides_smbus = 1;
1277 }
1278 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1279 switch (dev->subsystem_device) {
1280 case 0x001A:
1281
1282
1283
1284 asus_hides_smbus = 1;
1285 }
1286 }
1287}
1288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1290DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1291DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1293DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1294DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1295DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1296DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1297DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1298
1299DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1300DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1301DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1302
1303static void asus_hides_smbus_lpc(struct pci_dev *dev)
1304{
1305 u16 val;
1306
1307 if (likely(!asus_hides_smbus))
1308 return;
1309
1310 pci_read_config_word(dev, 0xF2, &val);
1311 if (val & 0x8) {
1312 pci_write_config_word(dev, 0xF2, val & (~0x8));
1313 pci_read_config_word(dev, 0xF2, &val);
1314 if (val & 0x8)
1315 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1316 else
1317 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1318 }
1319}
1320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1327DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1328DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1329DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1330DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1331DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1332DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1333DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1334
1335
1336static void __iomem *asus_rcba_base;
1337static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1338{
1339 u32 rcba;
1340
1341 if (likely(!asus_hides_smbus))
1342 return;
1343 WARN_ON(asus_rcba_base);
1344
1345 pci_read_config_dword(dev, 0xF0, &rcba);
1346
1347 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1348 if (asus_rcba_base == NULL)
1349 return;
1350}
1351
1352static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1353{
1354 u32 val;
1355
1356 if (likely(!asus_hides_smbus || !asus_rcba_base))
1357 return;
1358
1359 val = readl(asus_rcba_base + 0x3418);
1360 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1361}
1362
1363static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1364{
1365 if (likely(!asus_hides_smbus || !asus_rcba_base))
1366 return;
1367 iounmap(asus_rcba_base);
1368 asus_rcba_base = NULL;
1369 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1370}
1371
1372static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1373{
1374 asus_hides_smbus_lpc_ich6_suspend(dev);
1375 asus_hides_smbus_lpc_ich6_resume_early(dev);
1376 asus_hides_smbus_lpc_ich6_resume(dev);
1377}
1378DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1379DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1380DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1381DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1382
1383
1384
1385
1386static void quirk_sis_96x_smbus(struct pci_dev *dev)
1387{
1388 u8 val = 0;
1389 pci_read_config_byte(dev, 0x77, &val);
1390 if (val & 0x10) {
1391 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1392 pci_write_config_byte(dev, 0x77, val & ~0x10);
1393 }
1394}
1395DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1396DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1397DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1398DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1399DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1400DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1401DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1402DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412#define SIS_DETECT_REGISTER 0x40
1413
1414static void quirk_sis_503(struct pci_dev *dev)
1415{
1416 u8 reg;
1417 u16 devid;
1418
1419 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1420 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1421 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1422 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1423 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1424 return;
1425 }
1426
1427
1428
1429
1430
1431
1432 dev->device = devid;
1433 quirk_sis_96x_smbus(dev);
1434}
1435DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1436DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1437
1438
1439
1440
1441
1442
1443
1444
1445static void asus_hides_ac97_lpc(struct pci_dev *dev)
1446{
1447 u8 val;
1448 int asus_hides_ac97 = 0;
1449
1450 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1451 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1452 asus_hides_ac97 = 1;
1453 }
1454
1455 if (!asus_hides_ac97)
1456 return;
1457
1458 pci_read_config_byte(dev, 0x50, &val);
1459 if (val & 0xc0) {
1460 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1461 pci_read_config_byte(dev, 0x50, &val);
1462 if (val & 0xc0)
1463 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1464 else
1465 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1466 }
1467}
1468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1469DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1470
1471#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1472
1473
1474
1475
1476
1477
1478static void quirk_jmicron_ata(struct pci_dev *pdev)
1479{
1480 u32 conf1, conf5, class;
1481 u8 hdr;
1482
1483
1484 if (PCI_FUNC(pdev->devfn))
1485 return;
1486
1487 pci_read_config_dword(pdev, 0x40, &conf1);
1488 pci_read_config_dword(pdev, 0x80, &conf5);
1489
1490 conf1 &= ~0x00CFF302;
1491 conf5 &= ~(1 << 24);
1492
1493 switch (pdev->device) {
1494 case PCI_DEVICE_ID_JMICRON_JMB360:
1495 case PCI_DEVICE_ID_JMICRON_JMB362:
1496 case PCI_DEVICE_ID_JMICRON_JMB364:
1497
1498 conf1 |= 0x0002A100;
1499 break;
1500
1501 case PCI_DEVICE_ID_JMICRON_JMB365:
1502 case PCI_DEVICE_ID_JMICRON_JMB366:
1503
1504 conf5 |= (1 << 24);
1505
1506 case PCI_DEVICE_ID_JMICRON_JMB361:
1507 case PCI_DEVICE_ID_JMICRON_JMB363:
1508 case PCI_DEVICE_ID_JMICRON_JMB369:
1509
1510
1511 conf1 |= 0x00C2A1B3;
1512 break;
1513
1514 case PCI_DEVICE_ID_JMICRON_JMB368:
1515
1516 conf1 |= 0x00C00000;
1517 break;
1518 }
1519
1520 pci_write_config_dword(pdev, 0x40, conf1);
1521 pci_write_config_dword(pdev, 0x80, conf5);
1522
1523
1524 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1525 pdev->hdr_type = hdr & 0x7f;
1526 pdev->multifunction = !!(hdr & 0x80);
1527
1528 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1529 pdev->class = class >> 8;
1530}
1531DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1532DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1533DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1534DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1535DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1536DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1537DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1538DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1539DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1540DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1541DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1542DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1543DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1544DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1545DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1546DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1547DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1548DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1549
1550#endif
1551
1552#ifdef CONFIG_X86_IO_APIC
1553static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1554{
1555 int i;
1556
1557 if ((pdev->class >> 8) != 0xff00)
1558 return;
1559
1560
1561
1562
1563 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1564 insert_resource(&iomem_resource, &pdev->resource[0]);
1565
1566
1567
1568 for (i=1; i < 6; i++) {
1569 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1570 }
1571
1572}
1573DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1574#endif
1575
1576static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1577{
1578 pci_msi_off(pdev);
1579 pdev->no_msi = 1;
1580}
1581DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1583DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1584
1585
1586
1587
1588
1589
1590static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1591{
1592 pci_msi_off(dev);
1593 dev->no_msi = 1;
1594 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1595}
1596DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1597DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1598DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1599DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1600DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1601
1602
1603
1604
1605
1606static void quirk_intel_pcie_pm(struct pci_dev * dev)
1607{
1608 pci_pm_d3_delay = 120;
1609 dev->no_d1d2 = 1;
1610}
1611
1612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1615DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1616DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1618DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1621DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1622DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1623DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1624DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1625DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1627DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1628DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1630DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1632DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1633
1634#ifdef CONFIG_X86_IO_APIC
1635
1636
1637
1638
1639
1640
1641static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1642{
1643 if (noioapicquirk || noioapicreroute)
1644 return;
1645
1646 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1647 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1648 dev->vendor, dev->device);
1649}
1650DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1651DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1652DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1654DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1655DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1658DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1659DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1660DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1661DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1662DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1663DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1664DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1665DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676#define INTEL_6300_IOAPIC_ABAR 0x40
1677#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1678
1679static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1680{
1681 u16 pci_config_word;
1682
1683 if (noioapicquirk)
1684 return;
1685
1686 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1687 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1688 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1689
1690 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1691 dev->vendor, dev->device);
1692}
1693DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1694DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1695
1696
1697
1698
1699#define BC_HT1000_FEATURE_REG 0x64
1700#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1701#define BC_HT1000_MAP_IDX 0xC00
1702#define BC_HT1000_MAP_DATA 0xC01
1703
1704static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1705{
1706 u32 pci_config_dword;
1707 u8 irq;
1708
1709 if (noioapicquirk)
1710 return;
1711
1712 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1713 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1714 BC_HT1000_PIC_REGS_ENABLE);
1715
1716 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1717 outb(irq, BC_HT1000_MAP_IDX);
1718 outb(0x00, BC_HT1000_MAP_DATA);
1719 }
1720
1721 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1722
1723 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1724 dev->vendor, dev->device);
1725}
1726DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1727DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737#define AMD_813X_MISC 0x40
1738#define AMD_813X_NOIOAMODE (1<<0)
1739#define AMD_813X_REV_B1 0x12
1740#define AMD_813X_REV_B2 0x13
1741
1742static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1743{
1744 u32 pci_config_dword;
1745
1746 if (noioapicquirk)
1747 return;
1748 if ((dev->revision == AMD_813X_REV_B1) ||
1749 (dev->revision == AMD_813X_REV_B2))
1750 return;
1751
1752 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1753 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1754 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1755
1756 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1757 dev->vendor, dev->device);
1758}
1759DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1760DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1761DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1762DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1763
1764#define AMD_8111_PCI_IRQ_ROUTING 0x56
1765
1766static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1767{
1768 u16 pci_config_word;
1769
1770 if (noioapicquirk)
1771 return;
1772
1773 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1774 if (!pci_config_word) {
1775 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1776 "already disabled\n", dev->vendor, dev->device);
1777 return;
1778 }
1779 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1780 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1781 dev->vendor, dev->device);
1782}
1783DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1784DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1785#endif
1786
1787
1788
1789
1790
1791
1792static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1793{
1794 struct resource *r = &dev->resource[0];
1795
1796 if (r->start & 0x8) {
1797 r->start = 0;
1798 r->end = 0xf;
1799 }
1800}
1801DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1802 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1803 quirk_tc86c001_ide);
1804
1805static void __devinit quirk_netmos(struct pci_dev *dev)
1806{
1807 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1808 unsigned int num_serial = dev->subsystem_device & 0xf;
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820 switch (dev->device) {
1821 case PCI_DEVICE_ID_NETMOS_9835:
1822
1823 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1824 dev->subsystem_device == 0x0299)
1825 return;
1826 case PCI_DEVICE_ID_NETMOS_9735:
1827 case PCI_DEVICE_ID_NETMOS_9745:
1828 case PCI_DEVICE_ID_NETMOS_9845:
1829 case PCI_DEVICE_ID_NETMOS_9855:
1830 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1831 num_parallel) {
1832 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1833 "%u serial); changing class SERIAL to OTHER "
1834 "(use parport_serial)\n",
1835 dev->device, num_parallel, num_serial);
1836 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1837 (dev->class & 0xff);
1838 }
1839 }
1840}
1841DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1842
1843static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1844{
1845 u16 command, pmcsr;
1846 u8 __iomem *csr;
1847 u8 cmd_hi;
1848 int pm;
1849
1850 switch (dev->device) {
1851
1852 case 0x1029:
1853 case 0x1030 ... 0x1034:
1854 case 0x1038 ... 0x103E:
1855 case 0x1050 ... 0x1057:
1856 case 0x1059:
1857 case 0x1064 ... 0x106B:
1858 case 0x1091 ... 0x1095:
1859 case 0x1209:
1860 case 0x1229:
1861 case 0x2449:
1862 case 0x2459:
1863 case 0x245D:
1864 case 0x27DC:
1865 break;
1866 default:
1867 return;
1868 }
1869
1870
1871
1872
1873
1874
1875
1876
1877 pci_read_config_word(dev, PCI_COMMAND, &command);
1878
1879 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1880 return;
1881
1882
1883
1884
1885
1886 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1887 if (pm) {
1888 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1889 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1890 return;
1891 }
1892
1893
1894 csr = ioremap(pci_resource_start(dev, 0), 8);
1895 if (!csr) {
1896 dev_warn(&dev->dev, "Can't map e100 registers\n");
1897 return;
1898 }
1899
1900 cmd_hi = readb(csr + 3);
1901 if (cmd_hi == 0) {
1902 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1903 "disabling\n");
1904 writeb(1, csr + 3);
1905 }
1906
1907 iounmap(csr);
1908}
1909DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1910
1911
1912
1913
1914
1915static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1916{
1917 dev_info(&dev->dev, "Disabling L0s\n");
1918 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1919}
1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1923DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1924DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1925DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1926DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1927DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1928DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1931DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1932DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1933DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1934
1935static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1936{
1937
1938
1939
1940
1941 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1942 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1943 dev->class = PCI_CLASS_STORAGE_SCSI;
1944 }
1945}
1946DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1947
1948
1949static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1950{
1951 u16 en1k;
1952 u8 io_base_lo, io_limit_lo;
1953 unsigned long base, limit;
1954 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1955
1956 pci_read_config_word(dev, 0x40, &en1k);
1957
1958 if (en1k & 0x200) {
1959 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1960
1961 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1962 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1963 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1964 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1965
1966 if (base <= limit) {
1967 res->start = base;
1968 res->end = limit + 0x3ff;
1969 }
1970 }
1971}
1972DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1973
1974
1975
1976
1977
1978static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1979{
1980 u16 en1k, iobl_adr, iobl_adr_1k;
1981 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1982
1983 pci_read_config_word(dev, 0x40, &en1k);
1984
1985 if (en1k & 0x200) {
1986 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1987
1988 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1989
1990 if (iobl_adr != iobl_adr_1k) {
1991 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1992 iobl_adr,iobl_adr_1k);
1993 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1994 }
1995 }
1996}
1997DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1998
1999
2000
2001
2002
2003static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2004{
2005 uint8_t b;
2006 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2007 if (!(b & 0x20)) {
2008 pci_write_config_byte(dev, 0xf41, b | 0x20);
2009 dev_info(&dev->dev,
2010 "Linking AER extended capability\n");
2011 }
2012 }
2013}
2014DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2015 quirk_nvidia_ck804_pcie_aer_ext_cap);
2016DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2017 quirk_nvidia_ck804_pcie_aer_ext_cap);
2018
2019static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2020{
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2033 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2034 uint8_t b;
2035
2036
2037
2038 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2039 if (!p)
2040 return;
2041 pci_dev_put(p);
2042
2043 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2044 if (b & 0x40) {
2045
2046 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2047
2048 dev_info(&dev->dev,
2049 "Disabling VIA CX700 PCI parking\n");
2050 }
2051 }
2052
2053 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2054 if (b != 0) {
2055
2056 pci_write_config_byte(dev, 0x72, 0x0);
2057
2058
2059 pci_write_config_byte(dev, 0x75, 0x1);
2060
2061
2062 pci_write_config_byte(dev, 0x77, 0x0);
2063
2064 dev_info(&dev->dev,
2065 "Disabling VIA CX700 PCI caching\n");
2066 }
2067 }
2068}
2069DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2083{
2084
2085
2086
2087
2088 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2089 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2090 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2091 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2092 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2093 (dev->revision & 0xf0) == 0x0)) {
2094 if (dev->vpd)
2095 dev->vpd->len = 0x80;
2096 }
2097}
2098
2099DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2100 PCI_DEVICE_ID_NX2_5706,
2101 quirk_brcm_570x_limit_vpd);
2102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2103 PCI_DEVICE_ID_NX2_5706S,
2104 quirk_brcm_570x_limit_vpd);
2105DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2106 PCI_DEVICE_ID_NX2_5708,
2107 quirk_brcm_570x_limit_vpd);
2108DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2109 PCI_DEVICE_ID_NX2_5708S,
2110 quirk_brcm_570x_limit_vpd);
2111DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2112 PCI_DEVICE_ID_NX2_5709,
2113 quirk_brcm_570x_limit_vpd);
2114DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2115 PCI_DEVICE_ID_NX2_5709S,
2116 quirk_brcm_570x_limit_vpd);
2117
2118
2119
2120
2121
2122
2123
2124static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2125{
2126 u8 reg;
2127
2128 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2129 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2130 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2131 }
2132}
2133
2134DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2135 quirk_unhide_mch_dev6);
2136DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2137 quirk_unhide_mch_dev6);
2138
2139#ifdef CONFIG_TILE
2140
2141
2142
2143
2144
2145
2146
2147
2148static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2149{
2150 if (tile_plx_gen1) {
2151 pci_write_config_dword(dev, 0x98, 0x1);
2152 mdelay(50);
2153 }
2154}
2155DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2156#endif
2157
2158#ifdef CONFIG_PCI_MSI
2159
2160
2161
2162
2163
2164
2165static void __init quirk_disable_all_msi(struct pci_dev *dev)
2166{
2167 pci_no_msi();
2168 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2169}
2170DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2171DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2172DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2173DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2174DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2175DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2176DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2177
2178
2179static void __devinit quirk_disable_msi(struct pci_dev *dev)
2180{
2181 if (dev->subordinate) {
2182 dev_warn(&dev->dev, "MSI quirk detected; "
2183 "subordinate MSI disabled\n");
2184 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2185 }
2186}
2187DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2188DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2189DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2190
2191
2192
2193
2194
2195
2196
2197static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2198{
2199 struct pci_dev *apc_bridge;
2200
2201 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2202 if (apc_bridge) {
2203 if (apc_bridge->device == 0x9602)
2204 quirk_disable_msi(apc_bridge);
2205 pci_dev_put(apc_bridge);
2206 }
2207}
2208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2209DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2210
2211
2212
2213static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2214{
2215 int pos, ttl = 48;
2216
2217 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2218 while (pos && ttl--) {
2219 u8 flags;
2220
2221 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2222 &flags) == 0)
2223 {
2224 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2225 flags & HT_MSI_FLAGS_ENABLE ?
2226 "enabled" : "disabled");
2227 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2228 }
2229
2230 pos = pci_find_next_ht_capability(dev, pos,
2231 HT_CAPTYPE_MSI_MAPPING);
2232 }
2233 return 0;
2234}
2235
2236
2237static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2238{
2239 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2240 dev_warn(&dev->dev, "MSI quirk detected; "
2241 "subordinate MSI disabled\n");
2242 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2243 }
2244}
2245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2246 quirk_msi_ht_cap);
2247
2248
2249
2250
2251static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2252{
2253 struct pci_dev *pdev;
2254
2255 if (!dev->subordinate)
2256 return;
2257
2258
2259
2260
2261 pdev = pci_get_slot(dev->bus, 0);
2262 if (!pdev)
2263 return;
2264 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2265 dev_warn(&dev->dev, "MSI quirk detected; "
2266 "subordinate MSI disabled\n");
2267 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2268 }
2269 pci_dev_put(pdev);
2270}
2271DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2272 quirk_nvidia_ck804_msi_ht_cap);
2273
2274
2275static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2276{
2277 int pos, ttl = 48;
2278
2279 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2280 while (pos && ttl--) {
2281 u8 flags;
2282
2283 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2284 &flags) == 0) {
2285 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2286
2287 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2288 flags | HT_MSI_FLAGS_ENABLE);
2289 }
2290 pos = pci_find_next_ht_capability(dev, pos,
2291 HT_CAPTYPE_MSI_MAPPING);
2292 }
2293}
2294DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2295 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2296 ht_enable_msi_mapping);
2297
2298DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2299 ht_enable_msi_mapping);
2300
2301
2302
2303
2304
2305static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2306{
2307 if (dmi_name_in_vendors("P5N32-SLI PREMIUM") ||
2308 dmi_name_in_vendors("P5N32-E SLI")) {
2309 dev_info(&dev->dev,
2310 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2311 dev->no_msi = 1;
2312 }
2313}
2314DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2315 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2316 nvenet_msi_disable);
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2329{
2330 u32 cfg;
2331
2332 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2333 return;
2334
2335 pci_read_config_dword(dev, 0x74, &cfg);
2336
2337 if (cfg & ((1 << 2) | (1 << 15))) {
2338 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2339 cfg &= ~((1 << 2) | (1 << 15));
2340 pci_write_config_dword(dev, 0x74, cfg);
2341 }
2342}
2343
2344DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2345 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2346 nvbridge_check_legacy_irq_routing);
2347
2348DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2349 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2350 nvbridge_check_legacy_irq_routing);
2351
2352static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2353{
2354 int pos, ttl = 48;
2355 int found = 0;
2356
2357
2358 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2359 while (pos && ttl--) {
2360 u8 flags;
2361
2362 if (found < 1)
2363 found = 1;
2364 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2365 &flags) == 0) {
2366 if (flags & HT_MSI_FLAGS_ENABLE) {
2367 if (found < 2) {
2368 found = 2;
2369 break;
2370 }
2371 }
2372 }
2373 pos = pci_find_next_ht_capability(dev, pos,
2374 HT_CAPTYPE_MSI_MAPPING);
2375 }
2376
2377 return found;
2378}
2379
2380static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2381{
2382 struct pci_dev *dev;
2383 int pos;
2384 int i, dev_no;
2385 int found = 0;
2386
2387 dev_no = host_bridge->devfn >> 3;
2388 for (i = dev_no + 1; i < 0x20; i++) {
2389 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2390 if (!dev)
2391 continue;
2392
2393
2394 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2395 if (pos != 0) {
2396 pci_dev_put(dev);
2397 break;
2398 }
2399
2400 if (ht_check_msi_mapping(dev)) {
2401 found = 1;
2402 pci_dev_put(dev);
2403 break;
2404 }
2405 pci_dev_put(dev);
2406 }
2407
2408 return found;
2409}
2410
2411#define PCI_HT_CAP_SLAVE_CTRL0 4
2412#define PCI_HT_CAP_SLAVE_CTRL1 8
2413
2414static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2415{
2416 int pos, ctrl_off;
2417 int end = 0;
2418 u16 flags, ctrl;
2419
2420 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2421
2422 if (!pos)
2423 goto out;
2424
2425 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2426
2427 ctrl_off = ((flags >> 10) & 1) ?
2428 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2429 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2430
2431 if (ctrl & (1 << 6))
2432 end = 1;
2433
2434out:
2435 return end;
2436}
2437
2438static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2439{
2440 struct pci_dev *host_bridge;
2441 int pos;
2442 int i, dev_no;
2443 int found = 0;
2444
2445 dev_no = dev->devfn >> 3;
2446 for (i = dev_no; i >= 0; i--) {
2447 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2448 if (!host_bridge)
2449 continue;
2450
2451 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2452 if (pos != 0) {
2453 found = 1;
2454 break;
2455 }
2456 pci_dev_put(host_bridge);
2457 }
2458
2459 if (!found)
2460 return;
2461
2462
2463 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2464 host_bridge_with_leaf(host_bridge))
2465 goto out;
2466
2467
2468 if (msi_ht_cap_enabled(host_bridge))
2469 goto out;
2470
2471 ht_enable_msi_mapping(dev);
2472
2473out:
2474 pci_dev_put(host_bridge);
2475}
2476
2477static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2478{
2479 int pos, ttl = 48;
2480
2481 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2482 while (pos && ttl--) {
2483 u8 flags;
2484
2485 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2486 &flags) == 0) {
2487 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2488
2489 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2490 flags & ~HT_MSI_FLAGS_ENABLE);
2491 }
2492 pos = pci_find_next_ht_capability(dev, pos,
2493 HT_CAPTYPE_MSI_MAPPING);
2494 }
2495}
2496
2497static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2498{
2499 struct pci_dev *host_bridge;
2500 int pos;
2501 int found;
2502
2503 if (!pci_msi_enabled())
2504 return;
2505
2506
2507 found = ht_check_msi_mapping(dev);
2508
2509
2510 if (found == 0)
2511 return;
2512
2513
2514
2515
2516
2517 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2518 if (host_bridge == NULL) {
2519 dev_warn(&dev->dev,
2520 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2521 return;
2522 }
2523
2524 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2525 if (pos != 0) {
2526
2527 if (found == 1) {
2528
2529 if (all)
2530 ht_enable_msi_mapping(dev);
2531 else
2532 nv_ht_enable_msi_mapping(dev);
2533 }
2534 return;
2535 }
2536
2537
2538 if (found == 1)
2539 return;
2540
2541
2542 ht_disable_msi_mapping(dev);
2543}
2544
2545static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2546{
2547 return __nv_msi_ht_cap_quirk(dev, 1);
2548}
2549
2550static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2551{
2552 return __nv_msi_ht_cap_quirk(dev, 0);
2553}
2554
2555DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2556DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2557
2558DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2559DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2560
2561static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2562{
2563 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2564}
2565static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2566{
2567 struct pci_dev *p;
2568
2569
2570
2571
2572
2573 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2574 NULL);
2575 if (!p)
2576 return;
2577
2578 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2579 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2580 pci_dev_put(p);
2581}
2582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2583 PCI_DEVICE_ID_TIGON3_5780,
2584 quirk_msi_intx_disable_bug);
2585DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2586 PCI_DEVICE_ID_TIGON3_5780S,
2587 quirk_msi_intx_disable_bug);
2588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2589 PCI_DEVICE_ID_TIGON3_5714,
2590 quirk_msi_intx_disable_bug);
2591DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2592 PCI_DEVICE_ID_TIGON3_5714S,
2593 quirk_msi_intx_disable_bug);
2594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2595 PCI_DEVICE_ID_TIGON3_5715,
2596 quirk_msi_intx_disable_bug);
2597DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2598 PCI_DEVICE_ID_TIGON3_5715S,
2599 quirk_msi_intx_disable_bug);
2600
2601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2602 quirk_msi_intx_disable_ati_bug);
2603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2604 quirk_msi_intx_disable_ati_bug);
2605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2606 quirk_msi_intx_disable_ati_bug);
2607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2608 quirk_msi_intx_disable_ati_bug);
2609DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2610 quirk_msi_intx_disable_ati_bug);
2611
2612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2613 quirk_msi_intx_disable_bug);
2614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2615 quirk_msi_intx_disable_bug);
2616DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2617 quirk_msi_intx_disable_bug);
2618
2619#endif
2620
2621#ifdef CONFIG_PCI_IOV
2622
2623
2624
2625
2626
2627
2628static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
2629{
2630 int pos, flags;
2631 u32 bar, start, size;
2632
2633 if (PAGE_SIZE > 0x10000)
2634 return;
2635
2636 flags = pci_resource_flags(dev, 0);
2637 if ((flags & PCI_BASE_ADDRESS_SPACE) !=
2638 PCI_BASE_ADDRESS_SPACE_MEMORY ||
2639 (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
2640 PCI_BASE_ADDRESS_MEM_TYPE_32)
2641 return;
2642
2643 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
2644 if (!pos)
2645 return;
2646
2647 pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
2648 if (bar & PCI_BASE_ADDRESS_MEM_MASK)
2649 return;
2650
2651 start = pci_resource_start(dev, 1);
2652 size = pci_resource_len(dev, 1);
2653 if (!start || size != 0x400000 || start & (size - 1))
2654 return;
2655
2656 pci_resource_flags(dev, 1) = 0;
2657 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
2658 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
2659 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
2660
2661 dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
2662}
2663DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
2664DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
2665DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
2666DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov);
2667DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov);
2668DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov);
2669DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1518, quirk_i82576_sriov);
2670
2671#endif
2672
2673
2674
2675
2676
2677
2678
2679static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2680{
2681 dev->is_hotplug_bridge = 1;
2682}
2683
2684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713#ifdef CONFIG_MMC_RICOH_MMC
2714static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2715{
2716
2717 u8 write_enable;
2718 u8 write_target;
2719 u8 disable;
2720
2721
2722 if (PCI_FUNC(dev->devfn))
2723 return;
2724
2725 pci_read_config_byte(dev, 0xB7, &disable);
2726 if (disable & 0x02)
2727 return;
2728
2729 pci_read_config_byte(dev, 0x8E, &write_enable);
2730 pci_write_config_byte(dev, 0x8E, 0xAA);
2731 pci_read_config_byte(dev, 0x8D, &write_target);
2732 pci_write_config_byte(dev, 0x8D, 0xB7);
2733 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2734 pci_write_config_byte(dev, 0x8E, write_enable);
2735 pci_write_config_byte(dev, 0x8D, write_target);
2736
2737 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2738 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2739}
2740DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2741DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2742
2743static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2744{
2745
2746 u8 write_enable;
2747 u8 disable;
2748
2749
2750 if (PCI_FUNC(dev->devfn))
2751 return;
2752
2753 pci_read_config_byte(dev, 0xCB, &disable);
2754
2755 if (disable & 0x02)
2756 return;
2757
2758 pci_read_config_byte(dev, 0xCA, &write_enable);
2759 pci_write_config_byte(dev, 0xCA, 0x57);
2760 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2761 pci_write_config_byte(dev, 0xCA, write_enable);
2762
2763 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2764 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2765}
2766DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2767DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2768#endif
2769
2770#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
2771#define VTUNCERRMSK_REG 0x1ac
2772#define VTD_MSK_SPEC_ERRORS (1 << 31)
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783static void vtd_mask_spec_errors(struct pci_dev *dev)
2784{
2785 u32 word;
2786
2787 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2788 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2789}
2790DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2791DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2792#endif
2793
2794static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2795 struct pci_fixup *end)
2796{
2797 while (f < end) {
2798 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
2799 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
2800 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2801 f->hook(dev);
2802 }
2803 f++;
2804 }
2805}
2806
2807extern struct pci_fixup __start_pci_fixups_early[];
2808extern struct pci_fixup __end_pci_fixups_early[];
2809extern struct pci_fixup __start_pci_fixups_header[];
2810extern struct pci_fixup __end_pci_fixups_header[];
2811extern struct pci_fixup __start_pci_fixups_final[];
2812extern struct pci_fixup __end_pci_fixups_final[];
2813extern struct pci_fixup __start_pci_fixups_enable[];
2814extern struct pci_fixup __end_pci_fixups_enable[];
2815extern struct pci_fixup __start_pci_fixups_resume[];
2816extern struct pci_fixup __end_pci_fixups_resume[];
2817extern struct pci_fixup __start_pci_fixups_resume_early[];
2818extern struct pci_fixup __end_pci_fixups_resume_early[];
2819extern struct pci_fixup __start_pci_fixups_suspend[];
2820extern struct pci_fixup __end_pci_fixups_suspend[];
2821
2822
2823void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2824{
2825 struct pci_fixup *start, *end;
2826
2827 switch(pass) {
2828 case pci_fixup_early:
2829 start = __start_pci_fixups_early;
2830 end = __end_pci_fixups_early;
2831 break;
2832
2833 case pci_fixup_header:
2834 start = __start_pci_fixups_header;
2835 end = __end_pci_fixups_header;
2836 break;
2837
2838 case pci_fixup_final:
2839 start = __start_pci_fixups_final;
2840 end = __end_pci_fixups_final;
2841 break;
2842
2843 case pci_fixup_enable:
2844 start = __start_pci_fixups_enable;
2845 end = __end_pci_fixups_enable;
2846 break;
2847
2848 case pci_fixup_resume:
2849 start = __start_pci_fixups_resume;
2850 end = __end_pci_fixups_resume;
2851 break;
2852
2853 case pci_fixup_resume_early:
2854 start = __start_pci_fixups_resume_early;
2855 end = __end_pci_fixups_resume_early;
2856 break;
2857
2858 case pci_fixup_suspend:
2859 start = __start_pci_fixups_suspend;
2860 end = __end_pci_fixups_suspend;
2861 break;
2862
2863 default:
2864
2865 return;
2866 }
2867 pci_do_fixups(dev, start, end);
2868}
2869EXPORT_SYMBOL(pci_fixup_device);
2870
2871static int __init pci_apply_final_quirks(void)
2872{
2873 struct pci_dev *dev = NULL;
2874 u8 cls = 0;
2875 u8 tmp;
2876
2877 if (pci_cache_line_size)
2878 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
2879 pci_cache_line_size << 2);
2880
2881 for_each_pci_dev(dev) {
2882 pci_fixup_device(pci_fixup_final, dev);
2883
2884
2885
2886
2887
2888 if (!pci_cache_line_size) {
2889 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
2890 if (!cls)
2891 cls = tmp;
2892 if (!tmp || cls == tmp)
2893 continue;
2894
2895 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
2896 "using %u bytes\n", cls << 2, tmp << 2,
2897 pci_dfl_cache_line_size << 2);
2898 pci_cache_line_size = pci_dfl_cache_line_size;
2899 }
2900 }
2901 if (!pci_cache_line_size) {
2902 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
2903 cls << 2, pci_dfl_cache_line_size << 2);
2904 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
2905 }
2906
2907 return 0;
2908}
2909
2910fs_initcall_sync(pci_apply_final_quirks);
2911
2912
2913
2914
2915
2916
2917static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
2918{
2919 int pos;
2920
2921
2922 if (dev->class == PCI_CLASS_SERIAL_USB) {
2923 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
2924 if (!pos)
2925 return -ENOTTY;
2926
2927 if (probe)
2928 return 0;
2929
2930 pci_write_config_byte(dev, pos + 0x4, 1);
2931 msleep(100);
2932
2933 return 0;
2934 } else {
2935 return -ENOTTY;
2936 }
2937}
2938
2939static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
2940{
2941 int pos;
2942
2943 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2944 if (!pos)
2945 return -ENOTTY;
2946
2947 if (probe)
2948 return 0;
2949
2950 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
2951 PCI_EXP_DEVCTL_BCR_FLR);
2952 msleep(100);
2953
2954 return 0;
2955}
2956
2957#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
2958
2959static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
2960 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
2961 reset_intel_82599_sfp_virtfn },
2962 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2963 reset_intel_generic_dev },
2964 { 0 }
2965};
2966
2967int pci_dev_specific_reset(struct pci_dev *dev, int probe)
2968{
2969 const struct pci_dev_reset_methods *i;
2970
2971 for (i = pci_dev_reset_methods; i->reset; i++) {
2972 if ((i->vendor == dev->vendor ||
2973 i->vendor == (u16)PCI_ANY_ID) &&
2974 (i->device == dev->device ||
2975 i->device == (u16)PCI_ANY_ID))
2976 return i->reset(dev, probe);
2977 }
2978
2979 return -ENOTTY;
2980}
2981