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25#ifndef _MV_DEFS_H_
26#define _MV_DEFS_H_
27
28#define PCI_DEVICE_ID_ARECA_1300 0x1300
29#define PCI_DEVICE_ID_ARECA_1320 0x1320
30
31enum chip_flavors {
32 chip_6320,
33 chip_6440,
34 chip_6485,
35 chip_9480,
36 chip_9180,
37 chip_1300,
38 chip_1320
39};
40
41
42enum driver_configuration {
43 MVS_SLOTS = 512,
44 MVS_TX_RING_SZ = 1024,
45 MVS_RX_RING_SZ = 1024,
46
47
48 MVS_SOC_SLOTS = 64,
49 MVS_SOC_TX_RING_SZ = MVS_SOC_SLOTS * 2,
50 MVS_SOC_RX_RING_SZ = MVS_SOC_SLOTS * 2,
51
52 MVS_SLOT_BUF_SZ = 8192,
53 MVS_SSP_CMD_SZ = 64,
54 MVS_ATA_CMD_SZ = 96,
55 MVS_OAF_SZ = 64,
56 MVS_QUEUE_SIZE = 32,
57 MVS_CAN_QUEUE = MVS_SLOTS - 2,
58 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
59};
60
61
62enum hardware_details {
63 MVS_MAX_PHYS = 8,
64 MVS_MAX_PORTS = 8,
65 MVS_SOC_PHYS = 4,
66 MVS_SOC_PORTS = 4,
67 MVS_MAX_DEVICES = 1024,
68};
69
70
71enum peripheral_registers {
72 SPI_CTL = 0x10,
73 SPI_CMD = 0x14,
74 SPI_DATA = 0x18,
75};
76
77enum peripheral_register_bits {
78 TWSI_RDY = (1U << 7),
79 TWSI_RD = (1U << 4),
80
81 SPI_ADDR_MASK = 0x3ffff,
82};
83
84enum hw_register_bits {
85
86 INT_EN = (1U << 1),
87 HBA_RST = (1U << 0),
88
89
90 INT_XOR = (1U << 4),
91 INT_SAS_SATA = (1U << 0),
92
93
94 SATA_TARGET = (1U << 16),
95 MODE_AUTO_DET_PORT7 = (1U << 15),
96 MODE_AUTO_DET_PORT6 = (1U << 14),
97 MODE_AUTO_DET_PORT5 = (1U << 13),
98 MODE_AUTO_DET_PORT4 = (1U << 12),
99 MODE_AUTO_DET_PORT3 = (1U << 11),
100 MODE_AUTO_DET_PORT2 = (1U << 10),
101 MODE_AUTO_DET_PORT1 = (1U << 9),
102 MODE_AUTO_DET_PORT0 = (1U << 8),
103 MODE_AUTO_DET_EN = MODE_AUTO_DET_PORT0 | MODE_AUTO_DET_PORT1 |
104 MODE_AUTO_DET_PORT2 | MODE_AUTO_DET_PORT3 |
105 MODE_AUTO_DET_PORT4 | MODE_AUTO_DET_PORT5 |
106 MODE_AUTO_DET_PORT6 | MODE_AUTO_DET_PORT7,
107 MODE_SAS_PORT7_MASK = (1U << 7),
108 MODE_SAS_PORT6_MASK = (1U << 6),
109 MODE_SAS_PORT5_MASK = (1U << 5),
110 MODE_SAS_PORT4_MASK = (1U << 4),
111 MODE_SAS_PORT3_MASK = (1U << 3),
112 MODE_SAS_PORT2_MASK = (1U << 2),
113 MODE_SAS_PORT1_MASK = (1U << 1),
114 MODE_SAS_PORT0_MASK = (1U << 0),
115 MODE_SAS_SATA = MODE_SAS_PORT0_MASK | MODE_SAS_PORT1_MASK |
116 MODE_SAS_PORT2_MASK | MODE_SAS_PORT3_MASK |
117 MODE_SAS_PORT4_MASK | MODE_SAS_PORT5_MASK |
118 MODE_SAS_PORT6_MASK | MODE_SAS_PORT7_MASK,
119
120
121
122
123
124
125
126 TX_EN = (1U << 16),
127 TX_RING_SZ_MASK = 0xfff,
128
129
130 RX_EN = (1U << 16),
131 RX_RING_SZ_MASK = 0xfff,
132
133
134 COAL_EN = (1U << 16),
135
136
137 CINT_I2C = (1U << 31),
138 CINT_SW0 = (1U << 30),
139 CINT_SW1 = (1U << 29),
140 CINT_PRD_BC = (1U << 28),
141 CINT_DMA_PCIE = (1U << 27),
142 CINT_MEM = (1U << 26),
143 CINT_I2C_SLAVE = (1U << 25),
144 CINT_SRS = (1U << 3),
145 CINT_CI_STOP = (1U << 1),
146 CINT_DONE = (1U << 0),
147
148
149 CINT_PORT_STOPPED = (1U << 16),
150 CINT_PORT = (1U << 8),
151 CINT_PORT_MASK_OFFSET = 8,
152 CINT_PORT_MASK = (0xFF << CINT_PORT_MASK_OFFSET),
153 CINT_PHY_MASK_OFFSET = 4,
154 CINT_PHY_MASK = (0x0F << CINT_PHY_MASK_OFFSET),
155
156
157 TXQ_CMD_SHIFT = 29,
158 TXQ_CMD_SSP = 1,
159 TXQ_CMD_SMP = 2,
160 TXQ_CMD_STP = 3,
161 TXQ_CMD_SSP_FREE_LIST = 4,
162 TXQ_CMD_SLOT_RESET = 7,
163 TXQ_MODE_I = (1U << 28),
164 TXQ_MODE_TARGET = 0,
165 TXQ_MODE_INITIATOR = 1,
166 TXQ_PRIO_HI = (1U << 27),
167 TXQ_PRI_NORMAL = 0,
168 TXQ_PRI_HIGH = 1,
169 TXQ_SRS_SHIFT = 20,
170 TXQ_SRS_MASK = 0x7f,
171 TXQ_PHY_SHIFT = 12,
172 TXQ_PHY_MASK = 0xff,
173 TXQ_SLOT_MASK = 0xfff,
174
175
176 RXQ_GOOD = (1U << 23),
177 RXQ_SLOT_RESET = (1U << 21),
178 RXQ_CMD_RX = (1U << 20),
179 RXQ_ATTN = (1U << 19),
180 RXQ_RSP = (1U << 18),
181 RXQ_ERR = (1U << 17),
182 RXQ_DONE = (1U << 16),
183 RXQ_SLOT_MASK = 0xfff,
184
185
186 MCH_PRD_LEN_SHIFT = 16,
187 MCH_SSP_FR_TYPE_SHIFT = 13,
188
189
190 MCH_SSP_FR_CMD = 0x0,
191
192
193 MCH_SSP_FR_TASK = 0x1,
194
195
196 MCH_SSP_FR_XFER_RDY = 0x4,
197 MCH_SSP_FR_RESP = 0x5,
198 MCH_SSP_FR_READ = 0x6,
199 MCH_SSP_FR_READ_RESP = 0x7,
200
201 MCH_SSP_MODE_PASSTHRU = 1,
202 MCH_SSP_MODE_NORMAL = 0,
203 MCH_PASSTHRU = (1U << 12),
204 MCH_FBURST = (1U << 11),
205 MCH_CHK_LEN = (1U << 10),
206 MCH_RETRY = (1U << 9),
207 MCH_PROTECTION = (1U << 8),
208 MCH_RESET = (1U << 7),
209 MCH_FPDMA = (1U << 6),
210 MCH_ATAPI = (1U << 5),
211 MCH_BIST = (1U << 4),
212 MCH_PMP_MASK = 0xf,
213
214 CCTL_RST = (1U << 5),
215
216
217 CCTL_ENDIAN_DATA = (1U << 3),
218 CCTL_ENDIAN_RSP = (1U << 2),
219 CCTL_ENDIAN_OPEN = (1U << 1),
220 CCTL_ENDIAN_CMD = (1U << 0),
221
222
223 PHY_SSP_RST = (1U << 3),
224 PHY_BCAST_CHG = (1U << 2),
225 PHY_RST_HARD = (1U << 1),
226 PHY_RST = (1U << 0),
227 PHY_READY_MASK = (1U << 20),
228
229
230 PHYEV_DEC_ERR = (1U << 24),
231 PHYEV_DCDR_ERR = (1U << 23),
232 PHYEV_CRC_ERR = (1U << 22),
233 PHYEV_UNASSOC_FIS = (1U << 19),
234 PHYEV_AN = (1U << 18),
235 PHYEV_BIST_ACT = (1U << 17),
236 PHYEV_SIG_FIS = (1U << 16),
237 PHYEV_POOF = (1U << 12),
238 PHYEV_IU_BIG = (1U << 11),
239 PHYEV_IU_SMALL = (1U << 10),
240 PHYEV_UNK_TAG = (1U << 9),
241 PHYEV_BROAD_CH = (1U << 8),
242 PHYEV_COMWAKE = (1U << 7),
243 PHYEV_PORT_SEL = (1U << 6),
244 PHYEV_HARD_RST = (1U << 5),
245 PHYEV_ID_TMOUT = (1U << 4),
246 PHYEV_ID_FAIL = (1U << 3),
247 PHYEV_ID_DONE = (1U << 2),
248 PHYEV_HARD_RST_DONE = (1U << 1),
249 PHYEV_RDY_CH = (1U << 0),
250
251
252 PCS_EN_SATA_REG_SHIFT = (16),
253 PCS_EN_PORT_XMT_SHIFT = (12),
254 PCS_EN_PORT_XMT_SHIFT2 = (8),
255 PCS_SATA_RETRY = (1U << 8),
256 PCS_RSP_RX_EN = (1U << 7),
257 PCS_SATA_RETRY_2 = (1U << 6),
258 PCS_SELF_CLEAR = (1U << 5),
259 PCS_FIS_RX_EN = (1U << 4),
260 PCS_CMD_STOP_ERR = (1U << 3),
261 PCS_CMD_RST = (1U << 1),
262 PCS_CMD_EN = (1U << 0),
263
264
265 PORT_DEV_SSP_TRGT = (1U << 19),
266 PORT_DEV_SMP_TRGT = (1U << 18),
267 PORT_DEV_STP_TRGT = (1U << 17),
268 PORT_DEV_SSP_INIT = (1U << 11),
269 PORT_DEV_SMP_INIT = (1U << 10),
270 PORT_DEV_STP_INIT = (1U << 9),
271 PORT_PHY_ID_MASK = (0xFFU << 24),
272 PORT_SSP_TRGT_MASK = (0x1U << 19),
273 PORT_SSP_INIT_MASK = (0x1U << 11),
274 PORT_DEV_TRGT_MASK = (0x7U << 17),
275 PORT_DEV_INIT_MASK = (0x7U << 9),
276 PORT_DEV_TYPE_MASK = (0x7U << 0),
277
278
279 PHY_RDY = (1U << 2),
280 PHY_DW_SYNC = (1U << 1),
281 PHY_OOB_DTCTD = (1U << 0),
282
283
284
285 PHY_MODE6_LATECLK = (1U << 29),
286 PHY_MODE6_DTL_SPEED = (1U << 27),
287 PHY_MODE6_FC_ORDER = (1U << 26),
288 PHY_MODE6_MUCNT_EN = (1U << 24),
289 PHY_MODE6_SEL_MUCNT_LEN = (1U << 22),
290 PHY_MODE6_SELMUPI = (1U << 20),
291 PHY_MODE6_SELMUPF = (1U << 18),
292 PHY_MODE6_SELMUFF = (1U << 16),
293 PHY_MODE6_SELMUFI = (1U << 14),
294 PHY_MODE6_FREEZE_LOOP = (1U << 12),
295 PHY_MODE6_INT_RXFOFFS = (1U << 3),
296 PHY_MODE6_FRC_RXFOFFS = (1U << 2),
297 PHY_MODE6_STAU_0D8 = (1U << 1),
298 PHY_MODE6_RXSAT_DIS = (1U << 0),
299};
300
301
302enum sas_sata_config_port_regs {
303 PHYR_IDENTIFY = 0x00,
304 PHYR_ADDR_LO = 0x04,
305 PHYR_ADDR_HI = 0x08,
306 PHYR_ATT_DEV_INFO = 0x0C,
307 PHYR_ATT_ADDR_LO = 0x10,
308 PHYR_ATT_ADDR_HI = 0x14,
309 PHYR_SATA_CTL = 0x18,
310 PHYR_PHY_STAT = 0x1C,
311 PHYR_SATA_SIG0 = 0x20,
312 PHYR_SATA_SIG1 = 0x24,
313 PHYR_SATA_SIG2 = 0x28,
314 PHYR_SATA_SIG3 = 0x2c,
315 PHYR_R_ERR_COUNT = 0x30,
316 PHYR_CRC_ERR_COUNT = 0x34,
317 PHYR_WIDE_PORT = 0x38,
318 PHYR_CURRENT0 = 0x80,
319 PHYR_CURRENT1 = 0x84,
320 PHYR_CURRENT2 = 0x88,
321 CONFIG_ID_FRAME0 = 0x100,
322 CONFIG_ID_FRAME1 = 0x104,
323 CONFIG_ID_FRAME2 = 0x108,
324 CONFIG_ID_FRAME3 = 0x10c,
325 CONFIG_ID_FRAME4 = 0x110,
326 CONFIG_ID_FRAME5 = 0x114,
327 CONFIG_ID_FRAME6 = 0x118,
328 CONFIG_ATT_ID_FRAME0 = 0x11c,
329 CONFIG_ATT_ID_FRAME1 = 0x120,
330 CONFIG_ATT_ID_FRAME2 = 0x124,
331 CONFIG_ATT_ID_FRAME3 = 0x128,
332 CONFIG_ATT_ID_FRAME4 = 0x12c,
333 CONFIG_ATT_ID_FRAME5 = 0x130,
334 CONFIG_ATT_ID_FRAME6 = 0x134,
335};
336
337enum sas_cmd_port_registers {
338 CMD_CMRST_OOB_DET = 0x100,
339 CMD_CMWK_OOB_DET = 0x104,
340 CMD_CMSAS_OOB_DET = 0x108,
341 CMD_BRST_OOB_DET = 0x10c,
342 CMD_OOB_SPACE = 0x110,
343 CMD_OOB_BURST = 0x114,
344 CMD_PHY_TIMER = 0x118,
345 CMD_PHY_CONFIG0 = 0x11c,
346 CMD_PHY_CONFIG1 = 0x120,
347 CMD_SAS_CTL0 = 0x124,
348 CMD_SAS_CTL1 = 0x128,
349 CMD_SAS_CTL2 = 0x12c,
350 CMD_SAS_CTL3 = 0x130,
351 CMD_ID_TEST = 0x134,
352 CMD_PL_TIMER = 0x138,
353 CMD_WD_TIMER = 0x13c,
354 CMD_PORT_SEL_COUNT = 0x140,
355 CMD_APP_MEM_CTL = 0x144,
356 CMD_XOR_MEM_CTL = 0x148,
357 CMD_DMA_MEM_CTL = 0x14c,
358 CMD_PORT_MEM_CTL0 = 0x150,
359 CMD_PORT_MEM_CTL1 = 0x154,
360 CMD_SATA_PORT_MEM_CTL0 = 0x158,
361 CMD_SATA_PORT_MEM_CTL1 = 0x15c,
362 CMD_XOR_MEM_BIST_CTL = 0x160,
363 CMD_XOR_MEM_BIST_STAT = 0x164,
364 CMD_DMA_MEM_BIST_CTL = 0x168,
365 CMD_DMA_MEM_BIST_STAT = 0x16c,
366 CMD_PORT_MEM_BIST_CTL = 0x170,
367 CMD_PORT_MEM_BIST_STAT0 = 0x174,
368 CMD_PORT_MEM_BIST_STAT1 = 0x178,
369 CMD_STP_MEM_BIST_CTL = 0x17c,
370 CMD_STP_MEM_BIST_STAT0 = 0x180,
371 CMD_STP_MEM_BIST_STAT1 = 0x184,
372 CMD_RESET_COUNT = 0x188,
373 CMD_MONTR_DATA_SEL = 0x18C,
374 CMD_PLL_PHY_CONFIG = 0x190,
375 CMD_PHY_CTL = 0x194,
376 CMD_PHY_TEST_COUNT0 = 0x198,
377 CMD_PHY_TEST_COUNT1 = 0x19C,
378 CMD_PHY_TEST_COUNT2 = 0x1A0,
379 CMD_APP_ERR_CONFIG = 0x1A4,
380 CMD_PND_FIFO_CTL0 = 0x1A8,
381 CMD_HOST_CTL = 0x1AC,
382 CMD_HOST_WR_DATA = 0x1B0,
383 CMD_HOST_RD_DATA = 0x1B4,
384 CMD_PHY_MODE_21 = 0x1B8,
385 CMD_SL_MODE0 = 0x1BC,
386 CMD_SL_MODE1 = 0x1C0,
387 CMD_PND_FIFO_CTL1 = 0x1C4,
388};
389
390enum mvs_info_flags {
391 MVF_MSI = (1U << 0),
392 MVF_PHY_PWR_FIX = (1U << 1),
393 MVF_FLAG_SOC = (1U << 2),
394};
395
396enum mvs_event_flags {
397 PHY_PLUG_EVENT = (3U),
398 PHY_PLUG_IN = (1U << 0),
399 PHY_PLUG_OUT = (1U << 1),
400};
401
402enum mvs_port_type {
403 PORT_TGT_MASK = (1U << 5),
404 PORT_INIT_PORT = (1U << 4),
405 PORT_TGT_PORT = (1U << 3),
406 PORT_INIT_TGT_PORT = (PORT_INIT_PORT | PORT_TGT_PORT),
407 PORT_TYPE_SAS = (1U << 1),
408 PORT_TYPE_SATA = (1U << 0),
409};
410
411
412enum ct_format {
413
414 SSP_F_H = 0x00,
415 SSP_F_IU = 0x18,
416 SSP_F_MAX = 0x4D,
417
418 STP_CMD_FIS = 0x00,
419 STP_ATAPI_CMD = 0x40,
420 STP_F_MAX = 0x10,
421
422 SMP_F_T = 0x00,
423 SMP_F_DEP = 0x01,
424 SMP_F_MAX = 0x101,
425};
426
427enum status_buffer {
428 SB_EIR_OFF = 0x00,
429 SB_RFB_OFF = 0x08,
430 SB_RFB_MAX = 0x400,
431};
432
433enum error_info_rec {
434 CMD_ISS_STPD = (1U << 31),
435 CMD_PI_ERR = (1U << 30),
436 RSP_OVER = (1U << 29),
437 RETRY_LIM = (1U << 28),
438 UNK_FIS = (1U << 27),
439 DMA_TERM = (1U << 26),
440 SYNC_ERR = (1U << 25),
441 TFILE_ERR = (1U << 24),
442 R_ERR = (1U << 23),
443 RD_OFS = (1U << 20),
444 XFER_RDY_OFS = (1U << 19),
445 UNEXP_XFER_RDY = (1U << 18),
446 DATA_OVER_UNDER = (1U << 16),
447 INTERLOCK = (1U << 15),
448 NAK = (1U << 14),
449 ACK_NAK_TO = (1U << 13),
450 CXN_CLOSED = (1U << 12),
451 OPEN_TO = (1U << 11),
452 PATH_BLOCKED = (1U << 10),
453 NO_DEST = (1U << 9),
454 STP_RES_BSY = (1U << 8),
455 BREAK = (1U << 7),
456 BAD_DEST = (1U << 6),
457 BAD_PROTO = (1U << 5),
458 BAD_RATE = (1U << 4),
459 WRONG_DEST = (1U << 3),
460 CREDIT_TO = (1U << 2),
461 WDOG_TO = (1U << 1),
462 BUF_PAR = (1U << 0),
463};
464
465enum error_info_rec_2 {
466 SLOT_BSY_ERR = (1U << 31),
467 GRD_CHK_ERR = (1U << 14),
468 APP_CHK_ERR = (1U << 13),
469 REF_CHK_ERR = (1U << 12),
470 USR_BLK_NM = (1U << 0),
471};
472
473enum pci_cfg_register_bits {
474 PCTL_PWR_OFF = (0xFU << 24),
475 PCTL_COM_ON = (0xFU << 20),
476 PCTL_LINK_RST = (0xFU << 16),
477 PCTL_LINK_OFFS = (16),
478 PCTL_PHY_DSBL = (0xFU << 12),
479 PCTL_PHY_DSBL_OFFS = (12),
480 PRD_REQ_SIZE = (0x4000),
481 PRD_REQ_MASK = (0x00007000),
482 PLS_NEG_LINK_WD = (0x3FU << 4),
483 PLS_NEG_LINK_WD_OFFS = 4,
484 PLS_LINK_SPD = (0x0FU << 0),
485 PLS_LINK_SPD_OFFS = 0,
486};
487
488enum open_frame_protocol {
489 PROTOCOL_SMP = 0x0,
490 PROTOCOL_SSP = 0x1,
491 PROTOCOL_STP = 0x2,
492};
493
494
495enum datapres_field {
496 NO_DATA = 0,
497 RESPONSE_DATA = 1,
498 SENSE_DATA = 2,
499};
500
501
502struct mvs_tmf_task{
503 u8 tmf;
504 u16 tag_of_task_to_be_managed;
505};
506#endif
507