1#ifndef _UART_REG_REG_H_ 2#define _UART_REG_REG_H_ 3 4#define RBR_ADDRESS 0x00000000 5#define RBR_OFFSET 0x00000000 6#define RBR_RBR_MSB 7 7#define RBR_RBR_LSB 0 8#define RBR_RBR_MASK 0x000000ff 9#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB) 10#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK) 11 12#define THR_ADDRESS 0x00000000 13#define THR_OFFSET 0x00000000 14#define THR_THR_MSB 7 15#define THR_THR_LSB 0 16#define THR_THR_MASK 0x000000ff 17#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB) 18#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK) 19 20#define DLL_ADDRESS 0x00000000 21#define DLL_OFFSET 0x00000000 22#define DLL_DLL_MSB 7 23#define DLL_DLL_LSB 0 24#define DLL_DLL_MASK 0x000000ff 25#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB) 26#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK) 27 28#define DLH_ADDRESS 0x00000004 29#define DLH_OFFSET 0x00000004 30#define DLH_DLH_MSB 7 31#define DLH_DLH_LSB 0 32#define DLH_DLH_MASK 0x000000ff 33#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB) 34#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK) 35 36#define IER_ADDRESS 0x00000004 37#define IER_OFFSET 0x00000004 38#define IER_EDDSI_MSB 3 39#define IER_EDDSI_LSB 3 40#define IER_EDDSI_MASK 0x00000008 41#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB) 42#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK) 43#define IER_ELSI_MSB 2 44#define IER_ELSI_LSB 2 45#define IER_ELSI_MASK 0x00000004 46#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB) 47#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK) 48#define IER_ETBEI_MSB 1 49#define IER_ETBEI_LSB 1 50#define IER_ETBEI_MASK 0x00000002 51#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB) 52#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK) 53#define IER_ERBFI_MSB 0 54#define IER_ERBFI_LSB 0 55#define IER_ERBFI_MASK 0x00000001 56#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB) 57#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK) 58 59#define IIR_ADDRESS 0x00000008 60#define IIR_OFFSET 0x00000008 61#define IIR_FIFO_STATUS_MSB 7 62#define IIR_FIFO_STATUS_LSB 6 63#define IIR_FIFO_STATUS_MASK 0x000000c0 64#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB) 65#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK) 66#define IIR_IID_MSB 3 67#define IIR_IID_LSB 0 68#define IIR_IID_MASK 0x0000000f 69#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB) 70#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK) 71 72#define FCR_ADDRESS 0x00000008 73#define FCR_OFFSET 0x00000008 74#define FCR_RCVR_TRIG_MSB 7 75#define FCR_RCVR_TRIG_LSB 6 76#define FCR_RCVR_TRIG_MASK 0x000000c0 77#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB) 78#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK) 79#define FCR_DMA_MODE_MSB 3 80#define FCR_DMA_MODE_LSB 3 81#define FCR_DMA_MODE_MASK 0x00000008 82#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB) 83#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK) 84#define FCR_XMIT_FIFO_RST_MSB 2 85#define FCR_XMIT_FIFO_RST_LSB 2 86#define FCR_XMIT_FIFO_RST_MASK 0x00000004 87#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB) 88#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK) 89#define FCR_RCVR_FIFO_RST_MSB 1 90#define FCR_RCVR_FIFO_RST_LSB 1 91#define FCR_RCVR_FIFO_RST_MASK 0x00000002 92#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB) 93#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK) 94#define FCR_FIFO_EN_MSB 0 95#define FCR_FIFO_EN_LSB 0 96#define FCR_FIFO_EN_MASK 0x00000001 97#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB) 98#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK) 99 100#define LCR_ADDRESS 0x0000000c 101#define LCR_OFFSET 0x0000000c 102#define LCR_DLAB_MSB 7 103#define LCR_DLAB_LSB 7 104#define LCR_DLAB_MASK 0x00000080 105#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB) 106#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK) 107#define LCR_BREAK_MSB 6 108#define LCR_BREAK_LSB 6 109#define LCR_BREAK_MASK 0x00000040 110#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB) 111#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK) 112#define LCR_EPS_MSB 4 113#define LCR_EPS_LSB 4 114#define LCR_EPS_MASK 0x00000010 115#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB) 116#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK) 117#define LCR_PEN_MSB 3 118#define LCR_PEN_LSB 3 119#define LCR_PEN_MASK 0x00000008 120#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB) 121#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK) 122#define LCR_STOP_MSB 2 123#define LCR_STOP_LSB 2 124#define LCR_STOP_MASK 0x00000004 125#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB) 126#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK) 127#define LCR_CLS_MSB 1 128#define LCR_CLS_LSB 0 129#define LCR_CLS_MASK 0x00000003 130#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB) 131#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK) 132 133#define MCR_ADDRESS 0x00000010 134#define MCR_OFFSET 0x00000010 135#define MCR_LOOPBACK_MSB 5 136#define MCR_LOOPBACK_LSB 5 137#define MCR_LOOPBACK_MASK 0x00000020 138#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB) 139#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK) 140#define MCR_OUT2_MSB 3 141#define MCR_OUT2_LSB 3 142#define MCR_OUT2_MASK 0x00000008 143#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB) 144#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK) 145#define MCR_OUT1_MSB 2 146#define MCR_OUT1_LSB 2 147#define MCR_OUT1_MASK 0x00000004 148#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB) 149#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK) 150#define MCR_RTS_MSB 1 151#define MCR_RTS_LSB 1 152#define MCR_RTS_MASK 0x00000002 153#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB) 154#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK) 155#define MCR_DTR_MSB 0 156#define MCR_DTR_LSB 0 157#define MCR_DTR_MASK 0x00000001 158#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB) 159#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK) 160 161#define LSR_ADDRESS 0x00000014 162#define LSR_OFFSET 0x00000014 163#define LSR_FERR_MSB 7 164#define LSR_FERR_LSB 7 165#define LSR_FERR_MASK 0x00000080 166#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB) 167#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK) 168#define LSR_TEMT_MSB 6 169#define LSR_TEMT_LSB 6 170#define LSR_TEMT_MASK 0x00000040 171#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB) 172#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK) 173#define LSR_THRE_MSB 5 174#define LSR_THRE_LSB 5 175#define LSR_THRE_MASK 0x00000020 176#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB) 177#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK) 178#define LSR_BI_MSB 4 179#define LSR_BI_LSB 4 180#define LSR_BI_MASK 0x00000010 181#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB) 182#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK) 183#define LSR_FE_MSB 3 184#define LSR_FE_LSB 3 185#define LSR_FE_MASK 0x00000008 186#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB) 187#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK) 188#define LSR_PE_MSB 2 189#define LSR_PE_LSB 2 190#define LSR_PE_MASK 0x00000004 191#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB) 192#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK) 193#define LSR_OE_MSB 1 194#define LSR_OE_LSB 1 195#define LSR_OE_MASK 0x00000002 196#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB) 197#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK) 198#define LSR_DR_MSB 0 199#define LSR_DR_LSB 0 200#define LSR_DR_MASK 0x00000001 201#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB) 202#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK) 203 204#define MSR_ADDRESS 0x00000018 205#define MSR_OFFSET 0x00000018 206#define MSR_DCD_MSB 7 207#define MSR_DCD_LSB 7 208#define MSR_DCD_MASK 0x00000080 209#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB) 210#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK) 211#define MSR_RI_MSB 6 212#define MSR_RI_LSB 6 213#define MSR_RI_MASK 0x00000040 214#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB) 215#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK) 216#define MSR_DSR_MSB 5 217#define MSR_DSR_LSB 5 218#define MSR_DSR_MASK 0x00000020 219#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB) 220#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK) 221#define MSR_CTS_MSB 4 222#define MSR_CTS_LSB 4 223#define MSR_CTS_MASK 0x00000010 224#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB) 225#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK) 226#define MSR_DDCD_MSB 3 227#define MSR_DDCD_LSB 3 228#define MSR_DDCD_MASK 0x00000008 229#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB) 230#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK) 231#define MSR_TERI_MSB 2 232#define MSR_TERI_LSB 2 233#define MSR_TERI_MASK 0x00000004 234#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB) 235#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK) 236#define MSR_DDSR_MSB 1 237#define MSR_DDSR_LSB 1 238#define MSR_DDSR_MASK 0x00000002 239#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB) 240#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK) 241#define MSR_DCTS_MSB 0 242#define MSR_DCTS_LSB 0 243#define MSR_DCTS_MASK 0x00000001 244#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB) 245#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK) 246 247#define SCR_ADDRESS 0x0000001c 248#define SCR_OFFSET 0x0000001c 249#define SCR_SCR_MSB 7 250#define SCR_SCR_LSB 0 251#define SCR_SCR_MASK 0x000000ff 252#define SCR_SCR_GET(x) (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB) 253#define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR_MASK) 254 255#define SRBR_ADDRESS 0x00000020 256#define SRBR_OFFSET 0x00000020 257#define SRBR_SRBR_MSB 7 258#define SRBR_SRBR_LSB 0 259#define SRBR_SRBR_MASK 0x000000ff 260#define SRBR_SRBR_GET(x) (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB) 261#define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK) 262 263#define SIIR_ADDRESS 0x00000028 264#define SIIR_OFFSET 0x00000028 265#define SIIR_SIIR_MSB 7 266#define SIIR_SIIR_LSB 0 267#define SIIR_SIIR_MASK 0x000000ff 268#define SIIR_SIIR_GET(x) (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB) 269#define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK) 270 271#define MWR_ADDRESS 0x0000002c 272#define MWR_OFFSET 0x0000002c 273#define MWR_MWR_MSB 31 274#define MWR_MWR_LSB 0 275#define MWR_MWR_MASK 0xffffffff 276#define MWR_MWR_GET(x) (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB) 277#define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR_MASK) 278 279#define SLSR_ADDRESS 0x00000034 280#define SLSR_OFFSET 0x00000034 281#define SLSR_SLSR_MSB 7 282#define SLSR_SLSR_LSB 0 283#define SLSR_SLSR_MASK 0x000000ff 284#define SLSR_SLSR_GET(x) (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB) 285#define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK) 286 287#define SMSR_ADDRESS 0x00000038 288#define SMSR_OFFSET 0x00000038 289#define SMSR_SMSR_MSB 7 290#define SMSR_SMSR_LSB 0 291#define SMSR_SMSR_MASK 0x000000ff 292#define SMSR_SMSR_GET(x) (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB) 293#define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK) 294 295#define MRR_ADDRESS 0x0000003c 296#define MRR_OFFSET 0x0000003c 297#define MRR_MRR_MSB 31 298#define MRR_MRR_LSB 0 299#define MRR_MRR_MASK 0xffffffff 300#define MRR_MRR_GET(x) (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB) 301#define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR_MASK) 302 303 304#ifndef __ASSEMBLER__ 305 306typedef struct uart_reg_reg_s { 307 volatile unsigned int rbr; 308 volatile unsigned int dlh; 309 volatile unsigned int iir; 310 volatile unsigned int lcr; 311 volatile unsigned int mcr; 312 volatile unsigned int lsr; 313 volatile unsigned int msr; 314 volatile unsigned int scr; 315 volatile unsigned int srbr; 316 unsigned char pad0[4]; /* pad to 0x28 */ 317 volatile unsigned int siir; 318 volatile unsigned int mwr; 319 unsigned char pad1[4]; /* pad to 0x34 */ 320 volatile unsigned int slsr; 321 volatile unsigned int smsr; 322 volatile unsigned int mrr; 323} uart_reg_reg_t; 324 325#endif /* __ASSEMBLER__ */ 326 327#endif /* _UART_REG_H_ */ 328