1#ifndef _RTL819XU_HTTYPE_H_
2#define _RTL819XU_HTTYPE_H_
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12#define HT_OPMODE_NO_PROTECT 0
13#define HT_OPMODE_OPTIONAL 1
14#define HT_OPMODE_40MHZ_PROTECT 2
15#define HT_OPMODE_MIXED 3
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19
20#define MIMO_PS_STATIC 0
21#define MIMO_PS_DYNAMIC 1
22#define MIMO_PS_NOLIMIT 3
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29
30#define sHTCLng 4
31
32
33#define HT_SUPPORTED_MCS_1SS_BITMAP 0x000000ff
34#define HT_SUPPORTED_MCS_2SS_BITMAP 0x0000ff00
35#define HT_SUPPORTED_MCS_1SS_2SS_BITMAP HT_MCS_1SS_BITMAP|HT_MCS_1SS_2SS_BITMAP
36
37
38typedef enum _HT_MCS_RATE{
39 HT_MCS0 = 0x00000001,
40 HT_MCS1 = 0x00000002,
41 HT_MCS2 = 0x00000004,
42 HT_MCS3 = 0x00000008,
43 HT_MCS4 = 0x00000010,
44 HT_MCS5 = 0x00000020,
45 HT_MCS6 = 0x00000040,
46 HT_MCS7 = 0x00000080,
47 HT_MCS8 = 0x00000100,
48 HT_MCS9 = 0x00000200,
49 HT_MCS10 = 0x00000400,
50 HT_MCS11 = 0x00000800,
51 HT_MCS12 = 0x00001000,
52 HT_MCS13 = 0x00002000,
53 HT_MCS14 = 0x00004000,
54 HT_MCS15 = 0x00008000,
55
56}HT_MCS_RATE,*PHT_MCS_RATE;
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60
61typedef enum _HT_CHANNEL_WIDTH{
62 HT_CHANNEL_WIDTH_20 = 0,
63 HT_CHANNEL_WIDTH_20_40 = 1,
64}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH;
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69
70typedef enum _HT_EXTCHNL_OFFSET{
71 HT_EXTCHNL_OFFSET_NO_EXT = 0,
72 HT_EXTCHNL_OFFSET_UPPER = 1,
73 HT_EXTCHNL_OFFSET_NO_DEF = 2,
74 HT_EXTCHNL_OFFSET_LOWER = 3,
75}HT_EXTCHNL_OFFSET, *PHT_EXTCHNL_OFFSET;
76
77typedef enum _CHNLOP{
78 CHNLOP_NONE = 0,
79 CHNLOP_SCAN = 1,
80 CHNLOP_SWBW = 2,
81 CHNLOP_SWCHNL = 3,
82} CHNLOP, *PCHNLOP;
83
84
85#define CHHLOP_IN_PROGRESS(_pHTInfo) \
86 ((_pHTInfo)->ChnlOp > CHNLOP_NONE) ? TRUE : FALSE
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122typedef enum _HT_ACTION{
123 ACT_RECOMMAND_WIDTH = 0,
124 ACT_MIMO_PWR_SAVE = 1,
125 ACT_PSMP = 2,
126 ACT_SET_PCO_PHASE = 3,
127 ACT_MIMO_CHL_MEASURE = 4,
128 ACT_RECIPROCITY_CORRECT = 5,
129 ACT_MIMO_CSI_MATRICS = 6,
130 ACT_MIMO_NOCOMPR_STEER = 7,
131 ACT_MIMO_COMPR_STEER = 8,
132 ACT_ANTENNA_SELECT = 9,
133} HT_ACTION, *PHT_ACTION;
134
135
136
137typedef enum _HT_Bandwidth_40MHZ_Sub_Carrier{
138 SC_MODE_DUPLICATE = 0,
139 SC_MODE_LOWER = 1,
140 SC_MODE_UPPER = 2,
141 SC_MODE_FULL40MHZ = 3,
142}HT_BW40_SC_E;
143
144typedef struct _HT_CAPABILITY_ELE{
145
146
147 u8 AdvCoding:1;
148 u8 ChlWidth:1;
149 u8 MimoPwrSave:2;
150 u8 GreenField:1;
151 u8 ShortGI20Mhz:1;
152 u8 ShortGI40Mhz:1;
153 u8 TxSTBC:1;
154 u8 RxSTBC:2;
155 u8 DelayBA:1;
156 u8 MaxAMSDUSize:1;
157 u8 DssCCk:1;
158 u8 PSMP:1;
159 u8 Rsvd1:1;
160 u8 LSigTxopProtect:1;
161
162
163 u8 MaxRxAMPDUFactor:2;
164 u8 MPDUDensity:3;
165 u8 Rsvd2:3;
166
167
168 u8 MCS[16];
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172 u16 ExtHTCapInfo;
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174
175 u8 TxBFCap[4];
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178 u8 ASCap;
179
180} __attribute__ ((packed)) HT_CAPABILITY_ELE, *PHT_CAPABILITY_ELE;
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186
187typedef struct _HT_INFORMATION_ELE{
188 u8 ControlChl;
189
190 u8 ExtChlOffset:2;
191 u8 RecommemdedTxWidth:1;
192 u8 RIFS:1;
193 u8 PSMPAccessOnly:1;
194 u8 SrvIntGranularity:3;
195
196 u8 OptMode:2;
197 u8 NonGFDevPresent:1;
198 u8 Revd1:5;
199 u8 Revd2:8;
200
201 u8 Rsvd3:6;
202 u8 DualBeacon:1;
203 u8 DualCTSProtect:1;
204
205 u8 SecondaryBeacon:1;
206 u8 LSigTxopProtectFull:1;
207 u8 PcoActive:1;
208 u8 PcoPhase:1;
209 u8 Rsvd4:4;
210
211 u8 BasicMSC[16];
212} __attribute__ ((packed)) HT_INFORMATION_ELE, *PHT_INFORMATION_ELE;
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218typedef struct _MIMOPS_CTRL{
219 u8 MimoPsEnable:1;
220 u8 MimoPsMode:1;
221 u8 Reserved:6;
222} MIMOPS_CTRL, *PMIMOPS_CTRL;
223
224typedef enum _HT_SPEC_VER{
225 HT_SPEC_VER_IEEE = 0,
226 HT_SPEC_VER_EWC = 1,
227}HT_SPEC_VER, *PHT_SPEC_VER;
228
229typedef enum _HT_AGGRE_MODE_E{
230 HT_AGG_AUTO = 0,
231 HT_AGG_FORCE_ENABLE = 1,
232 HT_AGG_FORCE_DISABLE = 2,
233}HT_AGGRE_MODE_E, *PHT_AGGRE_MODE_E;
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241typedef struct _RT_HIGH_THROUGHPUT{
242 u8 bEnableHT;
243 u8 bCurrentHTSupport;
244
245 u8 bRegBW40MHz;
246 u8 bCurBW40MHz;
247
248 u8 bRegShortGI40MHz;
249 u8 bCurShortGI40MHz;
250
251 u8 bRegShortGI20MHz;
252 u8 bCurShortGI20MHz;
253
254 u8 bRegSuppCCK;
255 u8 bCurSuppCCK;
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258 HT_SPEC_VER ePeerHTSpecVer;
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262 HT_CAPABILITY_ELE SelfHTCap;
263 HT_INFORMATION_ELE SelfHTInfo;
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266 u8 PeerHTCapBuf[32];
267 u8 PeerHTInfoBuf[32];
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271 u8 bAMSDU_Support;
272 u16 nAMSDU_MaxSize;
273 u8 bCurrent_AMSDU_Support;
274 u16 nCurrent_AMSDU_MaxSize;
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278 u8 bAMPDUEnable;
279 u8 bCurrentAMPDUEnable;
280 u8 AMPDU_Factor;
281 u8 CurrentAMPDUFactor;
282 u8 MPDU_Density;
283 u8 CurrentMPDUDensity;
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286 HT_AGGRE_MODE_E ForcedAMPDUMode;
287 u8 ForcedAMPDUFactor;
288 u8 ForcedMPDUDensity;
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291 HT_AGGRE_MODE_E ForcedAMSDUMode;
292 u16 ForcedAMSDUMaxSize;
293
294 u8 bForcedShortGI;
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296 u8 CurrentOpMode;
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299 u8 SelfMimoPs;
300 u8 PeerMimoPs;
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303 HT_EXTCHNL_OFFSET CurSTAExtChnlOffset;
304 u8 bCurTxBW40MHz;
305 u8 PeerBandwidth;
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308 u8 bSwBwInProgress;
309 CHNLOP ChnlOp;
310 u8 SwBwStep;
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314 u8 bRegRT2RTAggregation;
315 u8 bCurrentRT2RTAggregation;
316 u8 bCurrentRT2RTLongSlotTime;
317 u8 szRT2RTAggBuffer[10];
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320 u8 bRegRxReorderEnable;
321 u8 bCurRxReorderEnable;
322 u8 RxReorderWinSize;
323 u8 RxReorderPendingTime;
324 u16 RxReorderDropCounter;
325
326#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
327 u8 UsbTxAggrNum;
328#endif
329#ifdef USB_RX_AGGREGATION_SUPPORT
330 u8 UsbRxFwAggrEn;
331 u8 UsbRxFwAggrPageNum;
332 u8 UsbRxFwAggrPacketNum;
333 u8 UsbRxFwAggrTimeout;
334#endif
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337 u8 bIsPeerBcm;
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340 u8 IOTPeer;
341 u32 IOTAction;
342} __attribute__ ((packed)) RT_HIGH_THROUGHPUT, *PRT_HIGH_THROUGHPUT;
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350typedef struct _RT_HTINFO_STA_ENTRY{
351 u8 bEnableHT;
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353 u8 bSupportCck;
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355 u16 AMSDU_MaxSize;
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357 u8 AMPDU_Factor;
358 u8 MPDU_Density;
359
360 u8 HTHighestOperaRate;
361
362 u8 bBw40MHz;
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364 u8 MimoPs;
365
366 u8 McsRateSet[16];
367
368
369}RT_HTINFO_STA_ENTRY, *PRT_HTINFO_STA_ENTRY;
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380typedef struct _BSS_HT{
381
382 u8 bdSupportHT;
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385 u8 bdHTCapBuf[32];
386 u16 bdHTCapLen;
387 u8 bdHTInfoBuf[32];
388 u16 bdHTInfoLen;
389
390 HT_SPEC_VER bdHTSpecVer;
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394 u8 bdRT2RTAggregation;
395 u8 bdRT2RTLongSlotTime;
396} __attribute__ ((packed)) BSS_HT, *PBSS_HT;
397
398typedef struct _MIMO_RSSI{
399 u32 EnableAntenna;
400 u32 AntennaA;
401 u32 AntennaB;
402 u32 AntennaC;
403 u32 AntennaD;
404 u32 Average;
405}MIMO_RSSI, *PMIMO_RSSI;
406
407typedef struct _MIMO_EVM{
408 u32 EVM1;
409 u32 EVM2;
410}MIMO_EVM, *PMIMO_EVM;
411
412typedef struct _FALSE_ALARM_STATISTICS{
413 u32 Cnt_Parity_Fail;
414 u32 Cnt_Rate_Illegal;
415 u32 Cnt_Crc8_fail;
416 u32 Cnt_all;
417}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
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420extern u8 MCS_FILTER_ALL[16];
421extern u8 MCS_FILTER_1SS[16];
422
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425
426#define PICK_RATE(_nLegacyRate, _nMcsRate) \
427 (_nMcsRate==0)?(_nLegacyRate&0x7f):(_nMcsRate)
428
429#define LEGACY_WIRELESS_MODE IEEE_MODE_MASK
430
431#define CURRENT_RATE(WirelessMode, LegacyRate, HTRate) \
432 ((WirelessMode & (LEGACY_WIRELESS_MODE))!=0)?\
433 (LegacyRate):\
434 (PICK_RATE(LegacyRate, HTRate))
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439#define RATE_ADPT_1SS_MASK 0xFF
440#define RATE_ADPT_2SS_MASK 0xF0
441#define RATE_ADPT_MCS32_MASK 0x01
442
443#define IS_11N_MCS_RATE(rate) (rate&0x80)
444
445typedef enum _HT_AGGRE_SIZE{
446 HT_AGG_SIZE_8K = 0,
447 HT_AGG_SIZE_16K = 1,
448 HT_AGG_SIZE_32K = 2,
449 HT_AGG_SIZE_64K = 3,
450}HT_AGGRE_SIZE_E, *PHT_AGGRE_SIZE_E;
451
452
453typedef enum _HT_IOT_PEER
454{
455 HT_IOT_PEER_UNKNOWN = 0,
456 HT_IOT_PEER_REALTEK = 1,
457 HT_IOT_PEER_BROADCOM = 2,
458 HT_IOT_PEER_RALINK = 3,
459 HT_IOT_PEER_ATHEROS = 4,
460 HT_IOT_PEER_CISCO= 5,
461 HT_IOT_PEER_MAX = 6
462}HT_IOT_PEER_E, *PHTIOT_PEER_E;
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467typedef enum _HT_IOT_ACTION{
468 HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
469 HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
470 HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
471 HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
472 HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
473 HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
474 HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
475 HT_IOT_ACT_CDD_FSYNC = 0x00000080,
476 HT_IOT_ACT_PURE_N_MODE = 0x00000100,
477 HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
478}HT_IOT_ACTION_E, *PHT_IOT_ACTION_E;
479
480#endif
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482