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16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/mm.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/proc_fs.h>
22#include <linux/pci.h>
23#include <linux/poll.h>
24#include <linux/dma-mapping.h>
25#include <linux/interrupt.h>
26#include <linux/spinlock.h>
27#include <linux/sched.h>
28#include <linux/slab.h>
29#include <linux/time.h>
30#include <linux/io.h>
31#include <linux/uaccess.h>
32
33#include "../vme.h"
34#include "../vme_bridge.h"
35#include "vme_tsi148.h"
36
37static int __init tsi148_init(void);
38static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
39static void tsi148_remove(struct pci_dev *);
40static void __exit tsi148_exit(void);
41
42
43
44static int err_chk;
45static int geoid;
46
47static char driver_name[] = "vme_tsi148";
48
49static DEFINE_PCI_DEVICE_TABLE(tsi148_ids) = {
50 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
51 { },
52};
53
54static struct pci_driver tsi148_driver = {
55 .name = driver_name,
56 .id_table = tsi148_ids,
57 .probe = tsi148_probe,
58 .remove = tsi148_remove,
59};
60
61static void reg_join(unsigned int high, unsigned int low,
62 unsigned long long *variable)
63{
64 *variable = (unsigned long long)high << 32;
65 *variable |= (unsigned long long)low;
66}
67
68static void reg_split(unsigned long long variable, unsigned int *high,
69 unsigned int *low)
70{
71 *low = (unsigned int)variable & 0xFFFFFFFF;
72 *high = (unsigned int)(variable >> 32);
73}
74
75
76
77
78static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
79 int channel_mask)
80{
81 u32 serviced = 0;
82
83 if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
84 wake_up(&bridge->dma_queue[0]);
85 serviced |= TSI148_LCSR_INTC_DMA0C;
86 }
87 if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
88 wake_up(&bridge->dma_queue[1]);
89 serviced |= TSI148_LCSR_INTC_DMA1C;
90 }
91
92 return serviced;
93}
94
95
96
97
98static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
99{
100 int i;
101 u32 serviced = 0;
102
103 for (i = 0; i < 4; i++) {
104 if (stat & TSI148_LCSR_INTS_LMS[i]) {
105
106 bridge->lm_callback[i](i);
107 serviced |= TSI148_LCSR_INTC_LMC[i];
108 }
109 }
110
111 return serviced;
112}
113
114
115
116
117
118
119static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat)
120{
121 int i;
122 u32 val;
123 u32 serviced = 0;
124 struct tsi148_driver *bridge;
125
126 bridge = tsi148_bridge->driver_priv;
127
128 for (i = 0; i < 4; i++) {
129 if (stat & TSI148_LCSR_INTS_MBS[i]) {
130 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
131 dev_err(tsi148_bridge->parent, "VME Mailbox %d received"
132 ": 0x%x\n", i, val);
133 serviced |= TSI148_LCSR_INTC_MBC[i];
134 }
135 }
136
137 return serviced;
138}
139
140
141
142
143static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge)
144{
145 struct tsi148_driver *bridge;
146
147 bridge = tsi148_bridge->driver_priv;
148
149 dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, "
150 "attributes: %08x\n",
151 ioread32be(bridge->base + TSI148_LCSR_EDPAU),
152 ioread32be(bridge->base + TSI148_LCSR_EDPAL),
153 ioread32be(bridge->base + TSI148_LCSR_EDPAT));
154
155 dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split "
156 "completion reg: %08x\n",
157 ioread32be(bridge->base + TSI148_LCSR_EDPXA),
158 ioread32be(bridge->base + TSI148_LCSR_EDPXS));
159
160 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
161
162 return TSI148_LCSR_INTC_PERRC;
163}
164
165
166
167
168static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
169{
170 unsigned int error_addr_high, error_addr_low;
171 unsigned long long error_addr;
172 u32 error_attrib;
173 struct vme_bus_error *error;
174 struct tsi148_driver *bridge;
175
176 bridge = tsi148_bridge->driver_priv;
177
178 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
179 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
180 error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
181
182 reg_join(error_addr_high, error_addr_low, &error_addr);
183
184
185 if (error_attrib & TSI148_LCSR_VEAT_VEOF) {
186 dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow "
187 "Occurred\n");
188 }
189
190 error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC);
191 if (error) {
192 error->address = error_addr;
193 error->attributes = error_attrib;
194 list_add_tail(&error->list, &tsi148_bridge->vme_errors);
195 } else {
196 dev_err(tsi148_bridge->parent, "Unable to alloc memory for "
197 "VMEbus Error reporting\n");
198 dev_err(tsi148_bridge->parent, "VME Bus Error at address: "
199 "0x%llx, attributes: %08x\n", error_addr, error_attrib);
200 }
201
202
203 iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
204
205 return TSI148_LCSR_INTC_VERRC;
206}
207
208
209
210
211static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
212{
213 wake_up(&bridge->iack_queue);
214
215 return TSI148_LCSR_INTC_IACKC;
216}
217
218
219
220
221static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge,
222 u32 stat)
223{
224 int vec, i, serviced = 0;
225 struct tsi148_driver *bridge;
226
227 bridge = tsi148_bridge->driver_priv;
228
229 for (i = 7; i > 0; i--) {
230 if (stat & (1 << i)) {
231
232
233
234
235
236 vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
237
238 vme_irq_handler(tsi148_bridge, i, vec);
239
240 serviced |= (1 << i);
241 }
242 }
243
244 return serviced;
245}
246
247
248
249
250
251static irqreturn_t tsi148_irqhandler(int irq, void *ptr)
252{
253 u32 stat, enable, serviced = 0;
254 struct vme_bridge *tsi148_bridge;
255 struct tsi148_driver *bridge;
256
257 tsi148_bridge = ptr;
258
259 bridge = tsi148_bridge->driver_priv;
260
261
262 enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
263 stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
264
265
266 stat &= enable;
267
268 if (unlikely(!stat))
269 return IRQ_NONE;
270
271
272
273 if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
274 serviced |= tsi148_DMA_irqhandler(bridge, stat);
275
276
277 if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
278 TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
279 serviced |= tsi148_LM_irqhandler(bridge, stat);
280
281
282 if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
283 TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
284 serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat);
285
286
287 if (stat & TSI148_LCSR_INTS_PERRS)
288 serviced |= tsi148_PERR_irqhandler(tsi148_bridge);
289
290
291 if (stat & TSI148_LCSR_INTS_VERRS)
292 serviced |= tsi148_VERR_irqhandler(tsi148_bridge);
293
294
295 if (stat & TSI148_LCSR_INTS_IACKS)
296 serviced |= tsi148_IACK_irqhandler(bridge);
297
298
299 if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
300 TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
301 TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
302 TSI148_LCSR_INTS_IRQ1S))
303 serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat);
304
305
306 iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
307
308 return IRQ_HANDLED;
309}
310
311static int tsi148_irq_init(struct vme_bridge *tsi148_bridge)
312{
313 int result;
314 unsigned int tmp;
315 struct pci_dev *pdev;
316 struct tsi148_driver *bridge;
317
318 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
319
320 bridge = tsi148_bridge->driver_priv;
321
322
323 INIT_LIST_HEAD(&tsi148_bridge->vme_errors);
324
325 mutex_init(&tsi148_bridge->irq_mtx);
326
327 result = request_irq(pdev->irq,
328 tsi148_irqhandler,
329 IRQF_SHARED,
330 driver_name, tsi148_bridge);
331 if (result) {
332 dev_err(tsi148_bridge->parent, "Can't get assigned pci irq "
333 "vector %02X\n", pdev->irq);
334 return result;
335 }
336
337
338 tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
339 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
340 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
341 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
342 TSI148_LCSR_INTEO_IACKEO;
343
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369
370
371 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
372 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
373
374 return 0;
375}
376
377static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge,
378 struct pci_dev *pdev)
379{
380 struct tsi148_driver *bridge = tsi148_bridge->driver_priv;
381
382
383 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
384 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
385
386
387 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
388
389
390 free_irq(pdev->irq, tsi148_bridge);
391}
392
393
394
395
396static int tsi148_iack_received(struct tsi148_driver *bridge)
397{
398 u32 tmp;
399
400 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
401
402 if (tmp & TSI148_LCSR_VICR_IRQS)
403 return 0;
404 else
405 return 1;
406}
407
408
409
410
411static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
412 int state, int sync)
413{
414 struct pci_dev *pdev;
415 u32 tmp;
416 struct tsi148_driver *bridge;
417
418 bridge = tsi148_bridge->driver_priv;
419
420
421 if (state == 0) {
422 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
423 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
424 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
425
426 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
427 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
428 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
429
430 if (sync != 0) {
431 pdev = container_of(tsi148_bridge->parent,
432 struct pci_dev, dev);
433
434 synchronize_irq(pdev->irq);
435 }
436 } else {
437 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
438 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
439 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
440
441 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
442 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
443 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
444 }
445}
446
447
448
449
450
451static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level,
452 int statid)
453{
454 u32 tmp;
455 struct tsi148_driver *bridge;
456
457 bridge = tsi148_bridge->driver_priv;
458
459 mutex_lock(&bridge->vme_int);
460
461
462 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
463
464
465 tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
466 (statid & TSI148_LCSR_VICR_STID_M);
467 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
468
469
470 tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
471 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
472
473
474 wait_event_interruptible(bridge->iack_queue,
475 tsi148_iack_received(bridge));
476
477 mutex_unlock(&bridge->vme_int);
478
479 return 0;
480}
481
482
483
484
485static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge,
486 vme_address_t aspace, unsigned long long address, size_t count)
487{
488 struct list_head *err_pos;
489 struct vme_bus_error *vme_err, *valid = NULL;
490 unsigned long long bound;
491
492 bound = address + count;
493
494
495
496
497
498
499
500
501 err_pos = NULL;
502
503 list_for_each(err_pos, &tsi148_bridge->vme_errors) {
504 vme_err = list_entry(err_pos, struct vme_bus_error, list);
505 if ((vme_err->address >= address) &&
506 (vme_err->address < bound)) {
507
508 valid = vme_err;
509 break;
510 }
511 }
512
513 return valid;
514}
515
516
517
518
519static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge,
520 vme_address_t aspace, unsigned long long address, size_t count)
521{
522 struct list_head *err_pos, *temp;
523 struct vme_bus_error *vme_err;
524 unsigned long long bound;
525
526 bound = address + count;
527
528
529
530
531
532
533
534
535 err_pos = NULL;
536
537 list_for_each_safe(err_pos, temp, &tsi148_bridge->vme_errors) {
538 vme_err = list_entry(err_pos, struct vme_bus_error, list);
539
540 if ((vme_err->address >= address) &&
541 (vme_err->address < bound)) {
542
543 list_del(err_pos);
544 kfree(vme_err);
545 }
546 }
547}
548
549
550
551
552static int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
553 unsigned long long vme_base, unsigned long long size,
554 dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
555{
556 unsigned int i, addr = 0, granularity = 0;
557 unsigned int temp_ctl = 0;
558 unsigned int vme_base_low, vme_base_high;
559 unsigned int vme_bound_low, vme_bound_high;
560 unsigned int pci_offset_low, pci_offset_high;
561 unsigned long long vme_bound, pci_offset;
562 struct vme_bridge *tsi148_bridge;
563 struct tsi148_driver *bridge;
564
565 tsi148_bridge = image->parent;
566 bridge = tsi148_bridge->driver_priv;
567
568 i = image->number;
569
570 switch (aspace) {
571 case VME_A16:
572 granularity = 0x10;
573 addr |= TSI148_LCSR_ITAT_AS_A16;
574 break;
575 case VME_A24:
576 granularity = 0x1000;
577 addr |= TSI148_LCSR_ITAT_AS_A24;
578 break;
579 case VME_A32:
580 granularity = 0x10000;
581 addr |= TSI148_LCSR_ITAT_AS_A32;
582 break;
583 case VME_A64:
584 granularity = 0x10000;
585 addr |= TSI148_LCSR_ITAT_AS_A64;
586 break;
587 case VME_CRCSR:
588 case VME_USER1:
589 case VME_USER2:
590 case VME_USER3:
591 case VME_USER4:
592 default:
593 dev_err(tsi148_bridge->parent, "Invalid address space\n");
594 return -EINVAL;
595 break;
596 }
597
598
599 reg_split(vme_base, &vme_base_high, &vme_base_low);
600
601
602
603
604
605 vme_bound = vme_base + size - granularity;
606 reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
607 pci_offset = (unsigned long long)pci_base - vme_base;
608 reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
609
610 if (vme_base_low & (granularity - 1)) {
611 dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n");
612 return -EINVAL;
613 }
614 if (vme_bound_low & (granularity - 1)) {
615 dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n");
616 return -EINVAL;
617 }
618 if (pci_offset_low & (granularity - 1)) {
619 dev_err(tsi148_bridge->parent, "Invalid PCI Offset "
620 "alignment\n");
621 return -EINVAL;
622 }
623
624
625 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
626 TSI148_LCSR_OFFSET_ITAT);
627 temp_ctl &= ~TSI148_LCSR_ITAT_EN;
628 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
629 TSI148_LCSR_OFFSET_ITAT);
630
631
632 iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
633 TSI148_LCSR_OFFSET_ITSAU);
634 iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
635 TSI148_LCSR_OFFSET_ITSAL);
636 iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
637 TSI148_LCSR_OFFSET_ITEAU);
638 iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
639 TSI148_LCSR_OFFSET_ITEAL);
640 iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
641 TSI148_LCSR_OFFSET_ITOFU);
642 iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
643 TSI148_LCSR_OFFSET_ITOFL);
644
645
646 temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
647 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
648 case VME_2eSST160:
649 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
650 break;
651 case VME_2eSST267:
652 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
653 break;
654 case VME_2eSST320:
655 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
656 break;
657 }
658
659
660 temp_ctl &= ~(0x1F << 7);
661 if (cycle & VME_BLT)
662 temp_ctl |= TSI148_LCSR_ITAT_BLT;
663 if (cycle & VME_MBLT)
664 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
665 if (cycle & VME_2eVME)
666 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
667 if (cycle & VME_2eSST)
668 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
669 if (cycle & VME_2eSSTB)
670 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
671
672
673 temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
674 temp_ctl |= addr;
675
676 temp_ctl &= ~0xF;
677 if (cycle & VME_SUPER)
678 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
679 if (cycle & VME_USER)
680 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
681 if (cycle & VME_PROG)
682 temp_ctl |= TSI148_LCSR_ITAT_PGM;
683 if (cycle & VME_DATA)
684 temp_ctl |= TSI148_LCSR_ITAT_DATA;
685
686
687 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
688 TSI148_LCSR_OFFSET_ITAT);
689
690 if (enabled)
691 temp_ctl |= TSI148_LCSR_ITAT_EN;
692
693 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
694 TSI148_LCSR_OFFSET_ITAT);
695
696 return 0;
697}
698
699
700
701
702static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
703 unsigned long long *vme_base, unsigned long long *size,
704 dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
705{
706 unsigned int i, granularity = 0, ctl = 0;
707 unsigned int vme_base_low, vme_base_high;
708 unsigned int vme_bound_low, vme_bound_high;
709 unsigned int pci_offset_low, pci_offset_high;
710 unsigned long long vme_bound, pci_offset;
711 struct tsi148_driver *bridge;
712
713 bridge = image->parent->driver_priv;
714
715 i = image->number;
716
717
718 ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
719 TSI148_LCSR_OFFSET_ITAT);
720
721 vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
722 TSI148_LCSR_OFFSET_ITSAU);
723 vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
724 TSI148_LCSR_OFFSET_ITSAL);
725 vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
726 TSI148_LCSR_OFFSET_ITEAU);
727 vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
728 TSI148_LCSR_OFFSET_ITEAL);
729 pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
730 TSI148_LCSR_OFFSET_ITOFU);
731 pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
732 TSI148_LCSR_OFFSET_ITOFL);
733
734
735 reg_join(vme_base_high, vme_base_low, vme_base);
736 reg_join(vme_bound_high, vme_bound_low, &vme_bound);
737 reg_join(pci_offset_high, pci_offset_low, &pci_offset);
738
739 *pci_base = (dma_addr_t)vme_base + pci_offset;
740
741 *enabled = 0;
742 *aspace = 0;
743 *cycle = 0;
744
745 if (ctl & TSI148_LCSR_ITAT_EN)
746 *enabled = 1;
747
748 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
749 granularity = 0x10;
750 *aspace |= VME_A16;
751 }
752 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
753 granularity = 0x1000;
754 *aspace |= VME_A24;
755 }
756 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
757 granularity = 0x10000;
758 *aspace |= VME_A32;
759 }
760 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
761 granularity = 0x10000;
762 *aspace |= VME_A64;
763 }
764
765
766 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
767
768
769 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
770 *cycle |= VME_2eSST160;
771 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
772 *cycle |= VME_2eSST267;
773 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
774 *cycle |= VME_2eSST320;
775
776 if (ctl & TSI148_LCSR_ITAT_BLT)
777 *cycle |= VME_BLT;
778 if (ctl & TSI148_LCSR_ITAT_MBLT)
779 *cycle |= VME_MBLT;
780 if (ctl & TSI148_LCSR_ITAT_2eVME)
781 *cycle |= VME_2eVME;
782 if (ctl & TSI148_LCSR_ITAT_2eSST)
783 *cycle |= VME_2eSST;
784 if (ctl & TSI148_LCSR_ITAT_2eSSTB)
785 *cycle |= VME_2eSSTB;
786
787 if (ctl & TSI148_LCSR_ITAT_SUPR)
788 *cycle |= VME_SUPER;
789 if (ctl & TSI148_LCSR_ITAT_NPRIV)
790 *cycle |= VME_USER;
791 if (ctl & TSI148_LCSR_ITAT_PGM)
792 *cycle |= VME_PROG;
793 if (ctl & TSI148_LCSR_ITAT_DATA)
794 *cycle |= VME_DATA;
795
796 return 0;
797}
798
799
800
801
802static int tsi148_alloc_resource(struct vme_master_resource *image,
803 unsigned long long size)
804{
805 unsigned long long existing_size;
806 int retval = 0;
807 struct pci_dev *pdev;
808 struct vme_bridge *tsi148_bridge;
809
810 tsi148_bridge = image->parent;
811
812 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
813
814 existing_size = (unsigned long long)(image->bus_resource.end -
815 image->bus_resource.start);
816
817
818 if ((size != 0) && (existing_size == (size - 1)))
819 return 0;
820
821 if (existing_size != 0) {
822 iounmap(image->kern_base);
823 image->kern_base = NULL;
824 if (image->bus_resource.name != NULL)
825 kfree(image->bus_resource.name);
826 release_resource(&image->bus_resource);
827 memset(&image->bus_resource, 0, sizeof(struct resource));
828 }
829
830
831 if (size == 0)
832 return 0;
833
834 if (image->bus_resource.name == NULL) {
835 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
836 if (image->bus_resource.name == NULL) {
837 dev_err(tsi148_bridge->parent, "Unable to allocate "
838 "memory for resource name\n");
839 retval = -ENOMEM;
840 goto err_name;
841 }
842 }
843
844 sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name,
845 image->number);
846
847 image->bus_resource.start = 0;
848 image->bus_resource.end = (unsigned long)size;
849 image->bus_resource.flags = IORESOURCE_MEM;
850
851 retval = pci_bus_alloc_resource(pdev->bus,
852 &image->bus_resource, size, size, PCIBIOS_MIN_MEM,
853 0, NULL, NULL);
854 if (retval) {
855 dev_err(tsi148_bridge->parent, "Failed to allocate mem "
856 "resource for window %d size 0x%lx start 0x%lx\n",
857 image->number, (unsigned long)size,
858 (unsigned long)image->bus_resource.start);
859 goto err_resource;
860 }
861
862 image->kern_base = ioremap_nocache(
863 image->bus_resource.start, size);
864 if (image->kern_base == NULL) {
865 dev_err(tsi148_bridge->parent, "Failed to remap resource\n");
866 retval = -ENOMEM;
867 goto err_remap;
868 }
869
870 return 0;
871
872 iounmap(image->kern_base);
873 image->kern_base = NULL;
874err_remap:
875 release_resource(&image->bus_resource);
876err_resource:
877 kfree(image->bus_resource.name);
878 memset(&image->bus_resource, 0, sizeof(struct resource));
879err_name:
880 return retval;
881}
882
883
884
885
886static void tsi148_free_resource(struct vme_master_resource *image)
887{
888 iounmap(image->kern_base);
889 image->kern_base = NULL;
890 release_resource(&image->bus_resource);
891 kfree(image->bus_resource.name);
892 memset(&image->bus_resource, 0, sizeof(struct resource));
893}
894
895
896
897
898static int tsi148_master_set(struct vme_master_resource *image, int enabled,
899 unsigned long long vme_base, unsigned long long size,
900 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
901{
902 int retval = 0;
903 unsigned int i;
904 unsigned int temp_ctl = 0;
905 unsigned int pci_base_low, pci_base_high;
906 unsigned int pci_bound_low, pci_bound_high;
907 unsigned int vme_offset_low, vme_offset_high;
908 unsigned long long pci_bound, vme_offset, pci_base;
909 struct vme_bridge *tsi148_bridge;
910 struct tsi148_driver *bridge;
911
912 tsi148_bridge = image->parent;
913
914 bridge = tsi148_bridge->driver_priv;
915
916
917 if (vme_base & 0xFFFF) {
918 dev_err(tsi148_bridge->parent, "Invalid VME Window "
919 "alignment\n");
920 retval = -EINVAL;
921 goto err_window;
922 }
923
924 if ((size == 0) && (enabled != 0)) {
925 dev_err(tsi148_bridge->parent, "Size must be non-zero for "
926 "enabled windows\n");
927 retval = -EINVAL;
928 goto err_window;
929 }
930
931 spin_lock(&image->lock);
932
933
934
935
936
937 retval = tsi148_alloc_resource(image, size);
938 if (retval) {
939 spin_unlock(&image->lock);
940 dev_err(tsi148_bridge->parent, "Unable to allocate memory for "
941 "resource\n");
942 goto err_res;
943 }
944
945 if (size == 0) {
946 pci_base = 0;
947 pci_bound = 0;
948 vme_offset = 0;
949 } else {
950 pci_base = (unsigned long long)image->bus_resource.start;
951
952
953
954
955
956 pci_bound = pci_base + (size - 0x10000);
957 vme_offset = vme_base - pci_base;
958 }
959
960
961 reg_split(pci_base, &pci_base_high, &pci_base_low);
962 reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
963 reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
964
965 if (pci_base_low & 0xFFFF) {
966 spin_unlock(&image->lock);
967 dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n");
968 retval = -EINVAL;
969 goto err_gran;
970 }
971 if (pci_bound_low & 0xFFFF) {
972 spin_unlock(&image->lock);
973 dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n");
974 retval = -EINVAL;
975 goto err_gran;
976 }
977 if (vme_offset_low & 0xFFFF) {
978 spin_unlock(&image->lock);
979 dev_err(tsi148_bridge->parent, "Invalid VME Offset "
980 "alignment\n");
981 retval = -EINVAL;
982 goto err_gran;
983 }
984
985 i = image->number;
986
987
988 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
989 TSI148_LCSR_OFFSET_OTAT);
990 temp_ctl &= ~TSI148_LCSR_OTAT_EN;
991 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
992 TSI148_LCSR_OFFSET_OTAT);
993
994
995 temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
996 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
997 case VME_2eSST160:
998 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
999 break;
1000 case VME_2eSST267:
1001 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
1002 break;
1003 case VME_2eSST320:
1004 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
1005 break;
1006 }
1007
1008
1009 if (cycle & VME_BLT) {
1010 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1011 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
1012 }
1013 if (cycle & VME_MBLT) {
1014 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1015 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
1016 }
1017 if (cycle & VME_2eVME) {
1018 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1019 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
1020 }
1021 if (cycle & VME_2eSST) {
1022 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1023 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
1024 }
1025 if (cycle & VME_2eSSTB) {
1026 dev_warn(tsi148_bridge->parent, "Currently not setting "
1027 "Broadcast Select Registers\n");
1028 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1029 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
1030 }
1031
1032
1033 temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
1034 switch (dwidth) {
1035 case VME_D16:
1036 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
1037 break;
1038 case VME_D32:
1039 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
1040 break;
1041 default:
1042 spin_unlock(&image->lock);
1043 dev_err(tsi148_bridge->parent, "Invalid data width\n");
1044 retval = -EINVAL;
1045 goto err_dwidth;
1046 }
1047
1048
1049 temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
1050 switch (aspace) {
1051 case VME_A16:
1052 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
1053 break;
1054 case VME_A24:
1055 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
1056 break;
1057 case VME_A32:
1058 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
1059 break;
1060 case VME_A64:
1061 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
1062 break;
1063 case VME_CRCSR:
1064 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
1065 break;
1066 case VME_USER1:
1067 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
1068 break;
1069 case VME_USER2:
1070 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
1071 break;
1072 case VME_USER3:
1073 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
1074 break;
1075 case VME_USER4:
1076 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
1077 break;
1078 default:
1079 spin_unlock(&image->lock);
1080 dev_err(tsi148_bridge->parent, "Invalid address space\n");
1081 retval = -EINVAL;
1082 goto err_aspace;
1083 break;
1084 }
1085
1086 temp_ctl &= ~(3<<4);
1087 if (cycle & VME_SUPER)
1088 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1089 if (cycle & VME_PROG)
1090 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1091
1092
1093 iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
1094 TSI148_LCSR_OFFSET_OTSAU);
1095 iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
1096 TSI148_LCSR_OFFSET_OTSAL);
1097 iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
1098 TSI148_LCSR_OFFSET_OTEAU);
1099 iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
1100 TSI148_LCSR_OFFSET_OTEAL);
1101 iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
1102 TSI148_LCSR_OFFSET_OTOFU);
1103 iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
1104 TSI148_LCSR_OFFSET_OTOFL);
1105
1106
1107 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1108 TSI148_LCSR_OFFSET_OTAT);
1109
1110 if (enabled)
1111 temp_ctl |= TSI148_LCSR_OTAT_EN;
1112
1113 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1114 TSI148_LCSR_OFFSET_OTAT);
1115
1116 spin_unlock(&image->lock);
1117 return 0;
1118
1119err_aspace:
1120err_dwidth:
1121err_gran:
1122 tsi148_free_resource(image);
1123err_res:
1124err_window:
1125 return retval;
1126
1127}
1128
1129
1130
1131
1132
1133
1134static int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
1135 unsigned long long *vme_base, unsigned long long *size,
1136 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1137{
1138 unsigned int i, ctl;
1139 unsigned int pci_base_low, pci_base_high;
1140 unsigned int pci_bound_low, pci_bound_high;
1141 unsigned int vme_offset_low, vme_offset_high;
1142
1143 unsigned long long pci_base, pci_bound, vme_offset;
1144 struct tsi148_driver *bridge;
1145
1146 bridge = image->parent->driver_priv;
1147
1148 i = image->number;
1149
1150 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1151 TSI148_LCSR_OFFSET_OTAT);
1152
1153 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1154 TSI148_LCSR_OFFSET_OTSAU);
1155 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1156 TSI148_LCSR_OFFSET_OTSAL);
1157 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1158 TSI148_LCSR_OFFSET_OTEAU);
1159 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1160 TSI148_LCSR_OFFSET_OTEAL);
1161 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1162 TSI148_LCSR_OFFSET_OTOFU);
1163 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1164 TSI148_LCSR_OFFSET_OTOFL);
1165
1166
1167 reg_join(pci_base_high, pci_base_low, &pci_base);
1168 reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1169 reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1170
1171 *vme_base = pci_base + vme_offset;
1172 *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1173
1174 *enabled = 0;
1175 *aspace = 0;
1176 *cycle = 0;
1177 *dwidth = 0;
1178
1179 if (ctl & TSI148_LCSR_OTAT_EN)
1180 *enabled = 1;
1181
1182
1183 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1184 *aspace |= VME_A16;
1185 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1186 *aspace |= VME_A24;
1187 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1188 *aspace |= VME_A32;
1189 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1190 *aspace |= VME_A64;
1191 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1192 *aspace |= VME_CRCSR;
1193 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1194 *aspace |= VME_USER1;
1195 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1196 *aspace |= VME_USER2;
1197 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1198 *aspace |= VME_USER3;
1199 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1200 *aspace |= VME_USER4;
1201
1202
1203 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1204 *cycle |= VME_2eSST160;
1205 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1206 *cycle |= VME_2eSST267;
1207 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1208 *cycle |= VME_2eSST320;
1209
1210
1211 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT)
1212 *cycle |= VME_SCT;
1213 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT)
1214 *cycle |= VME_BLT;
1215 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT)
1216 *cycle |= VME_MBLT;
1217 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME)
1218 *cycle |= VME_2eVME;
1219 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST)
1220 *cycle |= VME_2eSST;
1221 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB)
1222 *cycle |= VME_2eSSTB;
1223
1224 if (ctl & TSI148_LCSR_OTAT_SUP)
1225 *cycle |= VME_SUPER;
1226 else
1227 *cycle |= VME_USER;
1228
1229 if (ctl & TSI148_LCSR_OTAT_PGM)
1230 *cycle |= VME_PROG;
1231 else
1232 *cycle |= VME_DATA;
1233
1234
1235 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1236 *dwidth = VME_D16;
1237 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1238 *dwidth = VME_D32;
1239
1240 return 0;
1241}
1242
1243
1244static int tsi148_master_get(struct vme_master_resource *image, int *enabled,
1245 unsigned long long *vme_base, unsigned long long *size,
1246 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1247{
1248 int retval;
1249
1250 spin_lock(&image->lock);
1251
1252 retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1253 cycle, dwidth);
1254
1255 spin_unlock(&image->lock);
1256
1257 return retval;
1258}
1259
1260static ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
1261 size_t count, loff_t offset)
1262{
1263 int retval, enabled;
1264 unsigned long long vme_base, size;
1265 vme_address_t aspace;
1266 vme_cycle_t cycle;
1267 vme_width_t dwidth;
1268 struct vme_bus_error *vme_err = NULL;
1269 struct vme_bridge *tsi148_bridge;
1270
1271 tsi148_bridge = image->parent;
1272
1273 spin_lock(&image->lock);
1274
1275 memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
1276 retval = count;
1277
1278 if (!err_chk)
1279 goto skip_chk;
1280
1281 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1282 &dwidth);
1283
1284 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1285 count);
1286 if (vme_err != NULL) {
1287 dev_err(image->parent->parent, "First VME read error detected "
1288 "an at address 0x%llx\n", vme_err->address);
1289 retval = vme_err->address - (vme_base + offset);
1290
1291 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1292 count);
1293 }
1294
1295skip_chk:
1296 spin_unlock(&image->lock);
1297
1298 return retval;
1299}
1300
1301
1302static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
1303 size_t count, loff_t offset)
1304{
1305 int retval = 0, enabled;
1306 unsigned long long vme_base, size;
1307 vme_address_t aspace;
1308 vme_cycle_t cycle;
1309 vme_width_t dwidth;
1310
1311 struct vme_bus_error *vme_err = NULL;
1312 struct vme_bridge *tsi148_bridge;
1313 struct tsi148_driver *bridge;
1314
1315 tsi148_bridge = image->parent;
1316
1317 bridge = tsi148_bridge->driver_priv;
1318
1319 spin_lock(&image->lock);
1320
1321 memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
1322 retval = count;
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335 if (!err_chk)
1336 goto skip_chk;
1337
1338
1339
1340
1341
1342 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1343 &dwidth);
1344
1345 ioread16(bridge->flush_image->kern_base + 0x7F000);
1346
1347 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1348 count);
1349 if (vme_err != NULL) {
1350 dev_warn(tsi148_bridge->parent, "First VME write error detected"
1351 " an at address 0x%llx\n", vme_err->address);
1352 retval = vme_err->address - (vme_base + offset);
1353
1354 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1355 count);
1356 }
1357
1358skip_chk:
1359 spin_unlock(&image->lock);
1360
1361 return retval;
1362}
1363
1364
1365
1366
1367
1368
1369static unsigned int tsi148_master_rmw(struct vme_master_resource *image,
1370 unsigned int mask, unsigned int compare, unsigned int swap,
1371 loff_t offset)
1372{
1373 unsigned long long pci_addr;
1374 unsigned int pci_addr_high, pci_addr_low;
1375 u32 tmp, result;
1376 int i;
1377 struct tsi148_driver *bridge;
1378
1379 bridge = image->parent->driver_priv;
1380
1381
1382 i = image->number;
1383
1384
1385 mutex_lock(&bridge->vme_rmw);
1386
1387
1388 spin_lock(&image->lock);
1389
1390 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1391 TSI148_LCSR_OFFSET_OTSAU);
1392 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1393 TSI148_LCSR_OFFSET_OTSAL);
1394
1395 reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1396 reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1397
1398
1399 iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1400 iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1401 iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1402 iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1403 iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
1404
1405
1406 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1407 tmp |= TSI148_LCSR_VMCTRL_RMWEN;
1408 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1409
1410
1411 result = ioread32be(image->kern_base + offset);
1412
1413
1414 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1415 tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
1416 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1417
1418 spin_unlock(&image->lock);
1419
1420 mutex_unlock(&bridge->vme_rmw);
1421
1422 return result;
1423}
1424
1425static int tsi148_dma_set_vme_src_attributes(struct device *dev, u32 *attr,
1426 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
1427{
1428
1429 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1430 case VME_2eSST160:
1431 *attr |= TSI148_LCSR_DSAT_2eSSTM_160;
1432 break;
1433 case VME_2eSST267:
1434 *attr |= TSI148_LCSR_DSAT_2eSSTM_267;
1435 break;
1436 case VME_2eSST320:
1437 *attr |= TSI148_LCSR_DSAT_2eSSTM_320;
1438 break;
1439 }
1440
1441
1442 if (cycle & VME_SCT)
1443 *attr |= TSI148_LCSR_DSAT_TM_SCT;
1444
1445 if (cycle & VME_BLT)
1446 *attr |= TSI148_LCSR_DSAT_TM_BLT;
1447
1448 if (cycle & VME_MBLT)
1449 *attr |= TSI148_LCSR_DSAT_TM_MBLT;
1450
1451 if (cycle & VME_2eVME)
1452 *attr |= TSI148_LCSR_DSAT_TM_2eVME;
1453
1454 if (cycle & VME_2eSST)
1455 *attr |= TSI148_LCSR_DSAT_TM_2eSST;
1456
1457 if (cycle & VME_2eSSTB) {
1458 dev_err(dev, "Currently not setting Broadcast Select "
1459 "Registers\n");
1460 *attr |= TSI148_LCSR_DSAT_TM_2eSSTB;
1461 }
1462
1463
1464 switch (dwidth) {
1465 case VME_D16:
1466 *attr |= TSI148_LCSR_DSAT_DBW_16;
1467 break;
1468 case VME_D32:
1469 *attr |= TSI148_LCSR_DSAT_DBW_32;
1470 break;
1471 default:
1472 dev_err(dev, "Invalid data width\n");
1473 return -EINVAL;
1474 }
1475
1476
1477 switch (aspace) {
1478 case VME_A16:
1479 *attr |= TSI148_LCSR_DSAT_AMODE_A16;
1480 break;
1481 case VME_A24:
1482 *attr |= TSI148_LCSR_DSAT_AMODE_A24;
1483 break;
1484 case VME_A32:
1485 *attr |= TSI148_LCSR_DSAT_AMODE_A32;
1486 break;
1487 case VME_A64:
1488 *attr |= TSI148_LCSR_DSAT_AMODE_A64;
1489 break;
1490 case VME_CRCSR:
1491 *attr |= TSI148_LCSR_DSAT_AMODE_CRCSR;
1492 break;
1493 case VME_USER1:
1494 *attr |= TSI148_LCSR_DSAT_AMODE_USER1;
1495 break;
1496 case VME_USER2:
1497 *attr |= TSI148_LCSR_DSAT_AMODE_USER2;
1498 break;
1499 case VME_USER3:
1500 *attr |= TSI148_LCSR_DSAT_AMODE_USER3;
1501 break;
1502 case VME_USER4:
1503 *attr |= TSI148_LCSR_DSAT_AMODE_USER4;
1504 break;
1505 default:
1506 dev_err(dev, "Invalid address space\n");
1507 return -EINVAL;
1508 break;
1509 }
1510
1511 if (cycle & VME_SUPER)
1512 *attr |= TSI148_LCSR_DSAT_SUP;
1513 if (cycle & VME_PROG)
1514 *attr |= TSI148_LCSR_DSAT_PGM;
1515
1516 return 0;
1517}
1518
1519static int tsi148_dma_set_vme_dest_attributes(struct device *dev, u32 *attr,
1520 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
1521{
1522
1523 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1524 case VME_2eSST160:
1525 *attr |= TSI148_LCSR_DDAT_2eSSTM_160;
1526 break;
1527 case VME_2eSST267:
1528 *attr |= TSI148_LCSR_DDAT_2eSSTM_267;
1529 break;
1530 case VME_2eSST320:
1531 *attr |= TSI148_LCSR_DDAT_2eSSTM_320;
1532 break;
1533 }
1534
1535
1536 if (cycle & VME_SCT)
1537 *attr |= TSI148_LCSR_DDAT_TM_SCT;
1538
1539 if (cycle & VME_BLT)
1540 *attr |= TSI148_LCSR_DDAT_TM_BLT;
1541
1542 if (cycle & VME_MBLT)
1543 *attr |= TSI148_LCSR_DDAT_TM_MBLT;
1544
1545 if (cycle & VME_2eVME)
1546 *attr |= TSI148_LCSR_DDAT_TM_2eVME;
1547
1548 if (cycle & VME_2eSST)
1549 *attr |= TSI148_LCSR_DDAT_TM_2eSST;
1550
1551 if (cycle & VME_2eSSTB) {
1552 dev_err(dev, "Currently not setting Broadcast Select "
1553 "Registers\n");
1554 *attr |= TSI148_LCSR_DDAT_TM_2eSSTB;
1555 }
1556
1557
1558 switch (dwidth) {
1559 case VME_D16:
1560 *attr |= TSI148_LCSR_DDAT_DBW_16;
1561 break;
1562 case VME_D32:
1563 *attr |= TSI148_LCSR_DDAT_DBW_32;
1564 break;
1565 default:
1566 dev_err(dev, "Invalid data width\n");
1567 return -EINVAL;
1568 }
1569
1570
1571 switch (aspace) {
1572 case VME_A16:
1573 *attr |= TSI148_LCSR_DDAT_AMODE_A16;
1574 break;
1575 case VME_A24:
1576 *attr |= TSI148_LCSR_DDAT_AMODE_A24;
1577 break;
1578 case VME_A32:
1579 *attr |= TSI148_LCSR_DDAT_AMODE_A32;
1580 break;
1581 case VME_A64:
1582 *attr |= TSI148_LCSR_DDAT_AMODE_A64;
1583 break;
1584 case VME_CRCSR:
1585 *attr |= TSI148_LCSR_DDAT_AMODE_CRCSR;
1586 break;
1587 case VME_USER1:
1588 *attr |= TSI148_LCSR_DDAT_AMODE_USER1;
1589 break;
1590 case VME_USER2:
1591 *attr |= TSI148_LCSR_DDAT_AMODE_USER2;
1592 break;
1593 case VME_USER3:
1594 *attr |= TSI148_LCSR_DDAT_AMODE_USER3;
1595 break;
1596 case VME_USER4:
1597 *attr |= TSI148_LCSR_DDAT_AMODE_USER4;
1598 break;
1599 default:
1600 dev_err(dev, "Invalid address space\n");
1601 return -EINVAL;
1602 break;
1603 }
1604
1605 if (cycle & VME_SUPER)
1606 *attr |= TSI148_LCSR_DDAT_SUP;
1607 if (cycle & VME_PROG)
1608 *attr |= TSI148_LCSR_DDAT_PGM;
1609
1610 return 0;
1611}
1612
1613
1614
1615
1616static int tsi148_dma_list_add(struct vme_dma_list *list,
1617 struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
1618{
1619 struct tsi148_dma_entry *entry, *prev;
1620 u32 address_high, address_low;
1621 struct vme_dma_pattern *pattern_attr;
1622 struct vme_dma_pci *pci_attr;
1623 struct vme_dma_vme *vme_attr;
1624 dma_addr_t desc_ptr;
1625 int retval = 0;
1626 struct vme_bridge *tsi148_bridge;
1627
1628 tsi148_bridge = list->parent->parent;
1629
1630
1631 entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL);
1632 if (entry == NULL) {
1633 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
1634 "dma resource structure\n");
1635 retval = -ENOMEM;
1636 goto err_mem;
1637 }
1638
1639
1640 if ((unsigned long)&entry->descriptor & 0x7) {
1641 dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 "
1642 "byte boundary as required: %p\n",
1643 &entry->descriptor);
1644 retval = -EINVAL;
1645 goto err_align;
1646 }
1647
1648
1649
1650
1651 memset(&entry->descriptor, 0, sizeof(struct tsi148_dma_descriptor));
1652
1653
1654 switch (src->type) {
1655 case VME_DMA_PATTERN:
1656 pattern_attr = src->private;
1657
1658 entry->descriptor.dsal = pattern_attr->pattern;
1659 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT;
1660
1661 if (pattern_attr->type & VME_DMA_PATTERN_BYTE)
1662 entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ;
1663
1664
1665 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0)
1666 entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN;
1667
1668 break;
1669 case VME_DMA_PCI:
1670 pci_attr = src->private;
1671
1672 reg_split((unsigned long long)pci_attr->address, &address_high,
1673 &address_low);
1674 entry->descriptor.dsau = address_high;
1675 entry->descriptor.dsal = address_low;
1676 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PCI;
1677 break;
1678 case VME_DMA_VME:
1679 vme_attr = src->private;
1680
1681 reg_split((unsigned long long)vme_attr->address, &address_high,
1682 &address_low);
1683 entry->descriptor.dsau = address_high;
1684 entry->descriptor.dsal = address_low;
1685 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME;
1686
1687 retval = tsi148_dma_set_vme_src_attributes(
1688 tsi148_bridge->parent, &entry->descriptor.dsat,
1689 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1690 if (retval < 0)
1691 goto err_source;
1692 break;
1693 default:
1694 dev_err(tsi148_bridge->parent, "Invalid source type\n");
1695 retval = -EINVAL;
1696 goto err_source;
1697 break;
1698 }
1699
1700
1701 entry->descriptor.dnlau = 0;
1702 entry->descriptor.dnlal = TSI148_LCSR_DNLAL_LLA;
1703
1704
1705
1706 switch (dest->type) {
1707 case VME_DMA_PCI:
1708 pci_attr = dest->private;
1709
1710 reg_split((unsigned long long)pci_attr->address, &address_high,
1711 &address_low);
1712 entry->descriptor.ddau = address_high;
1713 entry->descriptor.ddal = address_low;
1714 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_PCI;
1715 break;
1716 case VME_DMA_VME:
1717 vme_attr = dest->private;
1718
1719 reg_split((unsigned long long)vme_attr->address, &address_high,
1720 &address_low);
1721 entry->descriptor.ddau = address_high;
1722 entry->descriptor.ddal = address_low;
1723 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME;
1724
1725 retval = tsi148_dma_set_vme_dest_attributes(
1726 tsi148_bridge->parent, &entry->descriptor.ddat,
1727 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1728 if (retval < 0)
1729 goto err_dest;
1730 break;
1731 default:
1732 dev_err(tsi148_bridge->parent, "Invalid destination type\n");
1733 retval = -EINVAL;
1734 goto err_dest;
1735 break;
1736 }
1737
1738
1739 entry->descriptor.dcnt = (u32)count;
1740
1741
1742 list_add_tail(&entry->list, &list->entries);
1743
1744
1745 if (entry->list.prev != &list->entries) {
1746 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1747 list);
1748
1749 desc_ptr = virt_to_bus(&entry->descriptor);
1750 reg_split(desc_ptr, &prev->descriptor.dnlau,
1751 &prev->descriptor.dnlal);
1752 }
1753
1754 return 0;
1755
1756err_dest:
1757err_source:
1758err_align:
1759 kfree(entry);
1760err_mem:
1761 return retval;
1762}
1763
1764
1765
1766
1767static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel)
1768{
1769 u32 tmp;
1770 struct tsi148_driver *bridge;
1771
1772 bridge = tsi148_bridge->driver_priv;
1773
1774 tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1775 TSI148_LCSR_OFFSET_DSTA);
1776
1777 if (tmp & TSI148_LCSR_DSTA_BSY)
1778 return 0;
1779 else
1780 return 1;
1781
1782}
1783
1784
1785
1786
1787
1788
1789static int tsi148_dma_list_exec(struct vme_dma_list *list)
1790{
1791 struct vme_dma_resource *ctrlr;
1792 int channel, retval = 0;
1793 struct tsi148_dma_entry *entry;
1794 dma_addr_t bus_addr;
1795 u32 bus_addr_high, bus_addr_low;
1796 u32 val, dctlreg = 0;
1797 struct vme_bridge *tsi148_bridge;
1798 struct tsi148_driver *bridge;
1799
1800 ctrlr = list->parent;
1801
1802 tsi148_bridge = ctrlr->parent;
1803
1804 bridge = tsi148_bridge->driver_priv;
1805
1806 mutex_lock(&ctrlr->mtx);
1807
1808 channel = ctrlr->number;
1809
1810 if (!list_empty(&ctrlr->running)) {
1811
1812
1813
1814
1815
1816
1817 mutex_unlock(&ctrlr->mtx);
1818 return -EBUSY;
1819 } else {
1820 list_add(&list->list, &ctrlr->running);
1821 }
1822
1823
1824 entry = list_first_entry(&list->entries, struct tsi148_dma_entry,
1825 list);
1826
1827 bus_addr = virt_to_bus(&entry->descriptor);
1828
1829 mutex_unlock(&ctrlr->mtx);
1830
1831 reg_split(bus_addr, &bus_addr_high, &bus_addr_low);
1832
1833 iowrite32be(bus_addr_high, bridge->base +
1834 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
1835 iowrite32be(bus_addr_low, bridge->base +
1836 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1837
1838
1839 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
1840 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1841
1842 wait_event_interruptible(bridge->dma_queue[channel],
1843 tsi148_dma_busy(ctrlr->parent, channel));
1844
1845
1846
1847
1848 val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1849 TSI148_LCSR_OFFSET_DSTA);
1850
1851 if (val & TSI148_LCSR_DSTA_VBE) {
1852 dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val);
1853 retval = -EIO;
1854 }
1855
1856
1857 mutex_lock(&ctrlr->mtx);
1858 list_del(&list->list);
1859 mutex_unlock(&ctrlr->mtx);
1860
1861 return retval;
1862}
1863
1864
1865
1866
1867
1868
1869static int tsi148_dma_list_empty(struct vme_dma_list *list)
1870{
1871 struct list_head *pos, *temp;
1872 struct tsi148_dma_entry *entry;
1873
1874
1875 list_for_each_safe(pos, temp, &list->entries) {
1876 list_del(pos);
1877 entry = list_entry(pos, struct tsi148_dma_entry, list);
1878 kfree(entry);
1879 }
1880
1881 return 0;
1882}
1883
1884
1885
1886
1887
1888
1889
1890
1891static int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1892 vme_address_t aspace, vme_cycle_t cycle)
1893{
1894 u32 lm_base_high, lm_base_low, lm_ctl = 0;
1895 int i;
1896 struct vme_bridge *tsi148_bridge;
1897 struct tsi148_driver *bridge;
1898
1899 tsi148_bridge = lm->parent;
1900
1901 bridge = tsi148_bridge->driver_priv;
1902
1903 mutex_lock(&lm->mtx);
1904
1905
1906 for (i = 0; i < lm->monitors; i++) {
1907 if (bridge->lm_callback[i] != NULL) {
1908 mutex_unlock(&lm->mtx);
1909 dev_err(tsi148_bridge->parent, "Location monitor "
1910 "callback attached, can't reset\n");
1911 return -EBUSY;
1912 }
1913 }
1914
1915 switch (aspace) {
1916 case VME_A16:
1917 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
1918 break;
1919 case VME_A24:
1920 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
1921 break;
1922 case VME_A32:
1923 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
1924 break;
1925 case VME_A64:
1926 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
1927 break;
1928 default:
1929 mutex_unlock(&lm->mtx);
1930 dev_err(tsi148_bridge->parent, "Invalid address space\n");
1931 return -EINVAL;
1932 break;
1933 }
1934
1935 if (cycle & VME_SUPER)
1936 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
1937 if (cycle & VME_USER)
1938 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
1939 if (cycle & VME_PROG)
1940 lm_ctl |= TSI148_LCSR_LMAT_PGM;
1941 if (cycle & VME_DATA)
1942 lm_ctl |= TSI148_LCSR_LMAT_DATA;
1943
1944 reg_split(lm_base, &lm_base_high, &lm_base_low);
1945
1946 iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
1947 iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
1948 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
1949
1950 mutex_unlock(&lm->mtx);
1951
1952 return 0;
1953}
1954
1955
1956
1957
1958static int tsi148_lm_get(struct vme_lm_resource *lm,
1959 unsigned long long *lm_base, vme_address_t *aspace, vme_cycle_t *cycle)
1960{
1961 u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
1962 struct tsi148_driver *bridge;
1963
1964 bridge = lm->parent->driver_priv;
1965
1966 mutex_lock(&lm->mtx);
1967
1968 lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
1969 lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
1970 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
1971
1972 reg_join(lm_base_high, lm_base_low, lm_base);
1973
1974 if (lm_ctl & TSI148_LCSR_LMAT_EN)
1975 enabled = 1;
1976
1977 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16)
1978 *aspace |= VME_A16;
1979
1980 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24)
1981 *aspace |= VME_A24;
1982
1983 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32)
1984 *aspace |= VME_A32;
1985
1986 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64)
1987 *aspace |= VME_A64;
1988
1989
1990 if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
1991 *cycle |= VME_SUPER;
1992 if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
1993 *cycle |= VME_USER;
1994 if (lm_ctl & TSI148_LCSR_LMAT_PGM)
1995 *cycle |= VME_PROG;
1996 if (lm_ctl & TSI148_LCSR_LMAT_DATA)
1997 *cycle |= VME_DATA;
1998
1999 mutex_unlock(&lm->mtx);
2000
2001 return enabled;
2002}
2003
2004
2005
2006
2007
2008
2009static int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
2010 void (*callback)(int))
2011{
2012 u32 lm_ctl, tmp;
2013 struct vme_bridge *tsi148_bridge;
2014 struct tsi148_driver *bridge;
2015
2016 tsi148_bridge = lm->parent;
2017
2018 bridge = tsi148_bridge->driver_priv;
2019
2020 mutex_lock(&lm->mtx);
2021
2022
2023 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2024 if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
2025 mutex_unlock(&lm->mtx);
2026 dev_err(tsi148_bridge->parent, "Location monitor not properly "
2027 "configured\n");
2028 return -EINVAL;
2029 }
2030
2031
2032 if (bridge->lm_callback[monitor] != NULL) {
2033 mutex_unlock(&lm->mtx);
2034 dev_err(tsi148_bridge->parent, "Existing callback attached\n");
2035 return -EBUSY;
2036 }
2037
2038
2039 bridge->lm_callback[monitor] = callback;
2040
2041
2042 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2043 tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
2044 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
2045
2046 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2047 tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
2048 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2049
2050
2051 if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2052 lm_ctl |= TSI148_LCSR_LMAT_EN;
2053 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2054 }
2055
2056 mutex_unlock(&lm->mtx);
2057
2058 return 0;
2059}
2060
2061
2062
2063
2064static int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
2065{
2066 u32 lm_en, tmp;
2067 struct tsi148_driver *bridge;
2068
2069 bridge = lm->parent->driver_priv;
2070
2071 mutex_lock(&lm->mtx);
2072
2073
2074 lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2075 lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
2076 iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
2077
2078 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2079 tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
2080 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2081
2082 iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
2083 bridge->base + TSI148_LCSR_INTC);
2084
2085
2086 bridge->lm_callback[monitor] = NULL;
2087
2088
2089 if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2090 TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
2091 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2092 tmp &= ~TSI148_LCSR_LMAT_EN;
2093 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
2094 }
2095
2096 mutex_unlock(&lm->mtx);
2097
2098 return 0;
2099}
2100
2101
2102
2103
2104static int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
2105{
2106 u32 slot = 0;
2107 struct tsi148_driver *bridge;
2108
2109 bridge = tsi148_bridge->driver_priv;
2110
2111 if (!geoid) {
2112 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
2113 slot = slot & TSI148_LCSR_VSTAT_GA_M;
2114 } else
2115 slot = geoid;
2116
2117 return (int)slot;
2118}
2119
2120static int __init tsi148_init(void)
2121{
2122 return pci_register_driver(&tsi148_driver);
2123}
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
2138 struct pci_dev *pdev)
2139{
2140 u32 cbar, crat, vstat;
2141 u32 crcsr_bus_high, crcsr_bus_low;
2142 int retval;
2143 struct tsi148_driver *bridge;
2144
2145 bridge = tsi148_bridge->driver_priv;
2146
2147
2148 bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2149 &bridge->crcsr_bus);
2150 if (bridge->crcsr_kernel == NULL) {
2151 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
2152 "CR/CSR image\n");
2153 return -ENOMEM;
2154 }
2155
2156 memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
2157
2158 reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
2159
2160 iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
2161 iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
2162
2163
2164 cbar = ioread32be(bridge->base + TSI148_CBAR);
2165 cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2166
2167 vstat = tsi148_slot_get(tsi148_bridge);
2168
2169 if (cbar != vstat) {
2170 cbar = vstat;
2171 dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n");
2172 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
2173 }
2174 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
2175
2176 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2177 if (crat & TSI148_LCSR_CRAT_EN) {
2178 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
2179 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
2180 bridge->base + TSI148_LCSR_CRAT);
2181 } else
2182 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
2183
2184
2185
2186
2187
2188 if (err_chk) {
2189 retval = tsi148_master_set(bridge->flush_image, 1,
2190 (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT,
2191 VME_D16);
2192 if (retval)
2193 dev_err(tsi148_bridge->parent, "Configuring flush image"
2194 " failed\n");
2195 }
2196
2197 return 0;
2198
2199}
2200
2201static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge,
2202 struct pci_dev *pdev)
2203{
2204 u32 crat;
2205 struct tsi148_driver *bridge;
2206
2207 bridge = tsi148_bridge->driver_priv;
2208
2209
2210 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2211 iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
2212 bridge->base + TSI148_LCSR_CRAT);
2213
2214
2215 iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
2216 iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
2217
2218 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
2219 bridge->crcsr_bus);
2220}
2221
2222static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2223{
2224 int retval, i, master_num;
2225 u32 data;
2226 struct list_head *pos = NULL;
2227 struct vme_bridge *tsi148_bridge;
2228 struct tsi148_driver *tsi148_device;
2229 struct vme_master_resource *master_image;
2230 struct vme_slave_resource *slave_image;
2231 struct vme_dma_resource *dma_ctrlr;
2232 struct vme_lm_resource *lm;
2233
2234
2235
2236
2237 tsi148_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
2238 if (tsi148_bridge == NULL) {
2239 dev_err(&pdev->dev, "Failed to allocate memory for device "
2240 "structure\n");
2241 retval = -ENOMEM;
2242 goto err_struct;
2243 }
2244
2245 tsi148_device = kzalloc(sizeof(struct tsi148_driver), GFP_KERNEL);
2246 if (tsi148_device == NULL) {
2247 dev_err(&pdev->dev, "Failed to allocate memory for device "
2248 "structure\n");
2249 retval = -ENOMEM;
2250 goto err_driver;
2251 }
2252
2253 tsi148_bridge->driver_priv = tsi148_device;
2254
2255
2256 retval = pci_enable_device(pdev);
2257 if (retval) {
2258 dev_err(&pdev->dev, "Unable to enable device\n");
2259 goto err_enable;
2260 }
2261
2262
2263 retval = pci_request_regions(pdev, driver_name);
2264 if (retval) {
2265 dev_err(&pdev->dev, "Unable to reserve resources\n");
2266 goto err_resource;
2267 }
2268
2269
2270 tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
2271 4096);
2272 if (!tsi148_device->base) {
2273 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2274 retval = -EIO;
2275 goto err_remap;
2276 }
2277
2278
2279 data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF;
2280 if (data != PCI_VENDOR_ID_TUNDRA) {
2281 dev_err(&pdev->dev, "CRG region check failed\n");
2282 retval = -EIO;
2283 goto err_test;
2284 }
2285
2286
2287 init_waitqueue_head(&tsi148_device->dma_queue[0]);
2288 init_waitqueue_head(&tsi148_device->dma_queue[1]);
2289 init_waitqueue_head(&tsi148_device->iack_queue);
2290 mutex_init(&tsi148_device->vme_int);
2291 mutex_init(&tsi148_device->vme_rmw);
2292
2293 tsi148_bridge->parent = &pdev->dev;
2294 strcpy(tsi148_bridge->name, driver_name);
2295
2296
2297 retval = tsi148_irq_init(tsi148_bridge);
2298 if (retval != 0) {
2299 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2300 goto err_irq;
2301 }
2302
2303
2304
2305
2306
2307
2308 master_num = TSI148_MAX_MASTER;
2309 if (err_chk) {
2310 master_num--;
2311
2312 tsi148_device->flush_image =
2313 kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL);
2314 if (tsi148_device->flush_image == NULL) {
2315 dev_err(&pdev->dev, "Failed to allocate memory for "
2316 "flush resource structure\n");
2317 retval = -ENOMEM;
2318 goto err_master;
2319 }
2320 tsi148_device->flush_image->parent = tsi148_bridge;
2321 spin_lock_init(&tsi148_device->flush_image->lock);
2322 tsi148_device->flush_image->locked = 1;
2323 tsi148_device->flush_image->number = master_num;
2324 tsi148_device->flush_image->address_attr = VME_A16 | VME_A24 |
2325 VME_A32 | VME_A64;
2326 tsi148_device->flush_image->cycle_attr = VME_SCT | VME_BLT |
2327 VME_MBLT | VME_2eVME | VME_2eSST | VME_2eSSTB |
2328 VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER |
2329 VME_USER | VME_PROG | VME_DATA;
2330 tsi148_device->flush_image->width_attr = VME_D16 | VME_D32;
2331 memset(&tsi148_device->flush_image->bus_resource, 0,
2332 sizeof(struct resource));
2333 tsi148_device->flush_image->kern_base = NULL;
2334 }
2335
2336
2337 INIT_LIST_HEAD(&tsi148_bridge->master_resources);
2338 for (i = 0; i < master_num; i++) {
2339 master_image = kmalloc(sizeof(struct vme_master_resource),
2340 GFP_KERNEL);
2341 if (master_image == NULL) {
2342 dev_err(&pdev->dev, "Failed to allocate memory for "
2343 "master resource structure\n");
2344 retval = -ENOMEM;
2345 goto err_master;
2346 }
2347 master_image->parent = tsi148_bridge;
2348 spin_lock_init(&master_image->lock);
2349 master_image->locked = 0;
2350 master_image->number = i;
2351 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2352 VME_A64;
2353 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2354 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2355 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2356 VME_PROG | VME_DATA;
2357 master_image->width_attr = VME_D16 | VME_D32;
2358 memset(&master_image->bus_resource, 0,
2359 sizeof(struct resource));
2360 master_image->kern_base = NULL;
2361 list_add_tail(&master_image->list,
2362 &tsi148_bridge->master_resources);
2363 }
2364
2365
2366 INIT_LIST_HEAD(&tsi148_bridge->slave_resources);
2367 for (i = 0; i < TSI148_MAX_SLAVE; i++) {
2368 slave_image = kmalloc(sizeof(struct vme_slave_resource),
2369 GFP_KERNEL);
2370 if (slave_image == NULL) {
2371 dev_err(&pdev->dev, "Failed to allocate memory for "
2372 "slave resource structure\n");
2373 retval = -ENOMEM;
2374 goto err_slave;
2375 }
2376 slave_image->parent = tsi148_bridge;
2377 mutex_init(&slave_image->mtx);
2378 slave_image->locked = 0;
2379 slave_image->number = i;
2380 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2381 VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2382 VME_USER3 | VME_USER4;
2383 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2384 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2385 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2386 VME_PROG | VME_DATA;
2387 list_add_tail(&slave_image->list,
2388 &tsi148_bridge->slave_resources);
2389 }
2390
2391
2392 INIT_LIST_HEAD(&tsi148_bridge->dma_resources);
2393 for (i = 0; i < TSI148_MAX_DMA; i++) {
2394 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
2395 GFP_KERNEL);
2396 if (dma_ctrlr == NULL) {
2397 dev_err(&pdev->dev, "Failed to allocate memory for "
2398 "dma resource structure\n");
2399 retval = -ENOMEM;
2400 goto err_dma;
2401 }
2402 dma_ctrlr->parent = tsi148_bridge;
2403 mutex_init(&dma_ctrlr->mtx);
2404 dma_ctrlr->locked = 0;
2405 dma_ctrlr->number = i;
2406 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
2407 VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME |
2408 VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME |
2409 VME_DMA_PATTERN_TO_MEM;
2410 INIT_LIST_HEAD(&dma_ctrlr->pending);
2411 INIT_LIST_HEAD(&dma_ctrlr->running);
2412 list_add_tail(&dma_ctrlr->list,
2413 &tsi148_bridge->dma_resources);
2414 }
2415
2416
2417 INIT_LIST_HEAD(&tsi148_bridge->lm_resources);
2418 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
2419 if (lm == NULL) {
2420 dev_err(&pdev->dev, "Failed to allocate memory for "
2421 "location monitor resource structure\n");
2422 retval = -ENOMEM;
2423 goto err_lm;
2424 }
2425 lm->parent = tsi148_bridge;
2426 mutex_init(&lm->mtx);
2427 lm->locked = 0;
2428 lm->number = 1;
2429 lm->monitors = 4;
2430 list_add_tail(&lm->list, &tsi148_bridge->lm_resources);
2431
2432 tsi148_bridge->slave_get = tsi148_slave_get;
2433 tsi148_bridge->slave_set = tsi148_slave_set;
2434 tsi148_bridge->master_get = tsi148_master_get;
2435 tsi148_bridge->master_set = tsi148_master_set;
2436 tsi148_bridge->master_read = tsi148_master_read;
2437 tsi148_bridge->master_write = tsi148_master_write;
2438 tsi148_bridge->master_rmw = tsi148_master_rmw;
2439 tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2440 tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2441 tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
2442 tsi148_bridge->irq_set = tsi148_irq_set;
2443 tsi148_bridge->irq_generate = tsi148_irq_generate;
2444 tsi148_bridge->lm_set = tsi148_lm_set;
2445 tsi148_bridge->lm_get = tsi148_lm_get;
2446 tsi148_bridge->lm_attach = tsi148_lm_attach;
2447 tsi148_bridge->lm_detach = tsi148_lm_detach;
2448 tsi148_bridge->slot_get = tsi148_slot_get;
2449
2450 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2451 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
2452 (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not");
2453 if (!geoid)
2454 dev_info(&pdev->dev, "VME geographical address is %d\n",
2455 data & TSI148_LCSR_VSTAT_GA_M);
2456 else
2457 dev_info(&pdev->dev, "VME geographical address is set to %d\n",
2458 geoid);
2459
2460 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2461 err_chk ? "enabled" : "disabled");
2462
2463 if (tsi148_crcsr_init(tsi148_bridge, pdev)) {
2464 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2465 goto err_crcsr;
2466 }
2467
2468 retval = vme_register_bridge(tsi148_bridge);
2469 if (retval != 0) {
2470 dev_err(&pdev->dev, "Chip Registration failed.\n");
2471 goto err_reg;
2472 }
2473
2474 pci_set_drvdata(pdev, tsi148_bridge);
2475
2476
2477 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2478 data &= ~TSI148_LCSR_VSTAT_BRDFL;
2479 data |= TSI148_LCSR_VSTAT_CPURST;
2480 iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);
2481
2482 return 0;
2483
2484err_reg:
2485 tsi148_crcsr_exit(tsi148_bridge, pdev);
2486err_crcsr:
2487err_lm:
2488
2489 list_for_each(pos, &tsi148_bridge->lm_resources) {
2490 lm = list_entry(pos, struct vme_lm_resource, list);
2491 list_del(pos);
2492 kfree(lm);
2493 }
2494err_dma:
2495
2496 list_for_each(pos, &tsi148_bridge->dma_resources) {
2497 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2498 list_del(pos);
2499 kfree(dma_ctrlr);
2500 }
2501err_slave:
2502
2503 list_for_each(pos, &tsi148_bridge->slave_resources) {
2504 slave_image = list_entry(pos, struct vme_slave_resource, list);
2505 list_del(pos);
2506 kfree(slave_image);
2507 }
2508err_master:
2509
2510 list_for_each(pos, &tsi148_bridge->master_resources) {
2511 master_image = list_entry(pos, struct vme_master_resource,
2512 list);
2513 list_del(pos);
2514 kfree(master_image);
2515 }
2516
2517 tsi148_irq_exit(tsi148_bridge, pdev);
2518err_irq:
2519err_test:
2520 iounmap(tsi148_device->base);
2521err_remap:
2522 pci_release_regions(pdev);
2523err_resource:
2524 pci_disable_device(pdev);
2525err_enable:
2526 kfree(tsi148_device);
2527err_driver:
2528 kfree(tsi148_bridge);
2529err_struct:
2530 return retval;
2531
2532}
2533
2534static void tsi148_remove(struct pci_dev *pdev)
2535{
2536 struct list_head *pos = NULL;
2537 struct list_head *tmplist;
2538 struct vme_master_resource *master_image;
2539 struct vme_slave_resource *slave_image;
2540 struct vme_dma_resource *dma_ctrlr;
2541 int i;
2542 struct tsi148_driver *bridge;
2543 struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev);
2544
2545 bridge = tsi148_bridge->driver_priv;
2546
2547
2548 dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
2549
2550
2551
2552
2553 for (i = 0; i < 8; i++) {
2554 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
2555 TSI148_LCSR_OFFSET_ITAT);
2556 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
2557 TSI148_LCSR_OFFSET_OTAT);
2558 }
2559
2560
2561
2562
2563 iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
2564
2565
2566
2567
2568 iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
2569
2570
2571
2572
2573 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
2574 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
2575 iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
2576
2577
2578
2579
2580 if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
2581 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
2582
2583
2584
2585
2586 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
2587 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
2588
2589 tsi148_irq_exit(tsi148_bridge, pdev);
2590
2591 vme_unregister_bridge(tsi148_bridge);
2592
2593 tsi148_crcsr_exit(tsi148_bridge, pdev);
2594
2595
2596 list_for_each_safe(pos, tmplist, &tsi148_bridge->dma_resources) {
2597 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2598 list_del(pos);
2599 kfree(dma_ctrlr);
2600 }
2601
2602
2603 list_for_each_safe(pos, tmplist, &tsi148_bridge->slave_resources) {
2604 slave_image = list_entry(pos, struct vme_slave_resource, list);
2605 list_del(pos);
2606 kfree(slave_image);
2607 }
2608
2609
2610 list_for_each_safe(pos, tmplist, &tsi148_bridge->master_resources) {
2611 master_image = list_entry(pos, struct vme_master_resource,
2612 list);
2613 list_del(pos);
2614 kfree(master_image);
2615 }
2616
2617 iounmap(bridge->base);
2618
2619 pci_release_regions(pdev);
2620
2621 pci_disable_device(pdev);
2622
2623 kfree(tsi148_bridge->driver_priv);
2624
2625 kfree(tsi148_bridge);
2626}
2627
2628static void __exit tsi148_exit(void)
2629{
2630 pci_unregister_driver(&tsi148_driver);
2631}
2632
2633MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2634module_param(err_chk, bool, 0);
2635
2636MODULE_PARM_DESC(geoid, "Override geographical addressing");
2637module_param(geoid, int, 0);
2638
2639MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2640MODULE_LICENSE("GPL");
2641
2642module_init(tsi148_init);
2643module_exit(tsi148_exit);
2644