LXR linux/drivers/tty/serial/jsm/jsm.h

   1/************************************************************************
   2 * Copyright 2003 Digi International (www.digi.com)
   3 *
   4 * Copyright (C) 2004 IBM Corporation. All rights reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2, or (at your option)
   9 * any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
  13 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
  14 * PURPOSE.  See the GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 59 * Temple Place - Suite 330, Boston,
  19 * MA  02111-1307, USA.
  20 *
  21 * Contact Information:
  22 * Scott H Kilau <Scott_Kilau@digi.com>
  23 * Wendy Xiong   <wendyx@us.ibm.com>
  24 *
  25 ***********************************************************************/
  26
  27#ifndef __JSM_DRIVER_H
  28#define __JSM_DRIVER_H
  29
  30#include <linux/kernel.h>
  31#include <linux/types.h>        /* To pick up the varions Linux types */
  32#include <linux/tty.h>
  33#include <linux/serial_core.h>
  34#include <linux/device.h>
  35
  36/*
  37 * Debugging levels can be set using debug insmod variable
  38 * They can also be compiled out completely.
  39 */
  40enum {
  41        DBG_INIT        = 0x01,
  42        DBG_BASIC       = 0x02,
  43        DBG_CORE        = 0x04,
  44        DBG_OPEN        = 0x08,
  45        DBG_CLOSE       = 0x10,
  46        DBG_READ        = 0x20,
  47        DBG_WRITE       = 0x40,
  48        DBG_IOCTL       = 0x80,
  49        DBG_PROC        = 0x100,
  50        DBG_PARAM       = 0x200,
  51        DBG_PSCAN       = 0x400,
  52        DBG_EVENT       = 0x800,
  53        DBG_DRAIN       = 0x1000,
  54        DBG_MSIGS       = 0x2000,
  55        DBG_MGMT        = 0x4000,
  56        DBG_INTR        = 0x8000,
  57        DBG_CARR        = 0x10000,
  58};
  59
  60#define jsm_printk(nlevel, klevel, pdev, fmt, args...)  \
  61        if ((DBG_##nlevel & jsm_debug))                 \
  62        dev_printk(KERN_##klevel, pdev->dev, fmt, ## args)
  63
  64#define MAXLINES        256
  65#define MAXPORTS        8
  66#define MAX_STOPS_SENT  5
  67
  68/* Board type definitions */
  69
  70#define T_NEO           0000
  71#define T_CLASSIC       0001
  72#define T_PCIBUS        0400
  73
  74/* Board State Definitions */
  75
  76#define BD_RUNNING      0x0
  77#define BD_REASON       0x7f
  78#define BD_NOTFOUND     0x1
  79#define BD_NOIOPORT     0x2
  80#define BD_NOMEM        0x3
  81#define BD_NOBIOS       0x4
  82#define BD_NOFEP        0x5
  83#define BD_FAILED       0x6
  84#define BD_ALLOCATED    0x7
  85#define BD_TRIBOOT      0x8
  86#define BD_BADKME       0x80
  87
  88
  89/* 4 extra for alignment play space */
  90#define WRITEBUFLEN     ((4096) + 4)
  91#define MYFLIPLEN       N_TTY_BUF_SIZE
  92
  93#define JSM_VERSION     "jsm: 1.2-1-INKERNEL"
  94#define JSM_PARTNUM     "40002438_A-INKERNEL"
  95
  96struct jsm_board;
  97struct jsm_channel;
  98
  99/************************************************************************
 100 * Per board operations structure                                       *
 101 ************************************************************************/
 102struct board_ops {
 103        irq_handler_t intr;
 104        void (*uart_init) (struct jsm_channel *ch);
 105        void (*uart_off) (struct jsm_channel *ch);
 106        void (*param) (struct jsm_channel *ch);
 107        void (*assert_modem_signals) (struct jsm_channel *ch);
 108        void (*flush_uart_write) (struct jsm_channel *ch);
 109        void (*flush_uart_read) (struct jsm_channel *ch);
 110        void (*disable_receiver) (struct jsm_channel *ch);
 111        void (*enable_receiver) (struct jsm_channel *ch);
 112        void (*send_break) (struct jsm_channel *ch);
 113        void (*clear_break) (struct jsm_channel *ch, int);
 114        void (*send_start_character) (struct jsm_channel *ch);
 115        void (*send_stop_character) (struct jsm_channel *ch);
 116        void (*copy_data_from_queue_to_uart) (struct jsm_channel *ch);
 117        u32 (*get_uart_bytes_left) (struct jsm_channel *ch);
 118        void (*send_immediate_char) (struct jsm_channel *ch, unsigned char);
 119};
 120
 121
 122/*
 123 *      Per-board information
 124 */
 125struct jsm_board
 126{
 127        int             boardnum;       /* Board number: 0-32 */
 128
 129        int             type;           /* Type of board */
 130        u8              rev;            /* PCI revision ID */
 131        struct pci_dev  *pci_dev;
 132        u32             maxports;       /* MAX ports this board can handle */
 133
 134        spinlock_t      bd_intr_lock;   /* Used to protect the poller tasklet and
 135                                         * the interrupt routine from each other.
 136                                         */
 137
 138        u32             nasync;         /* Number of ports on card */
 139
 140        u32             irq;            /* Interrupt request number */
 141
 142        u64             membase;        /* Start of base memory of the card */
 143        u64             membase_end;    /* End of base memory of the card */
 144
 145        u8      __iomem *re_map_membase;/* Remapped memory of the card */
 146
 147        u64             iobase;         /* Start of io base of the card */
 148        u64             iobase_end;     /* End of io base of the card */
 149
 150        u32             bd_uart_offset; /* Space between each UART */
 151
 152        struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */
 153        char            *flipbuf;       /* Our flip buffer, alloced if board is found */
 154
 155        u32             bd_dividend;    /* Board/UARTs specific dividend */
 156
 157        struct board_ops *bd_ops;
 158
 159        struct list_head jsm_board_entry;
 160};
 161
 162/************************************************************************
 163 * Device flag definitions for ch_flags.
 164 ************************************************************************/
 165#define CH_PRON         0x0001          /* Printer on string            */
 166#define CH_STOP         0x0002          /* Output is stopped            */
 167#define CH_STOPI        0x0004          /* Input is stopped             */
 168#define CH_CD           0x0008          /* Carrier is present           */
 169#define CH_FCAR         0x0010          /* Carrier forced on            */
 170#define CH_HANGUP       0x0020          /* Hangup received              */
 171
 172#define CH_RECEIVER_OFF 0x0040          /* Receiver is off              */
 173#define CH_OPENING      0x0080          /* Port in fragile open state   */
 174#define CH_CLOSING      0x0100          /* Port in fragile close state  */
 175#define CH_FIFO_ENABLED 0x0200          /* Port has FIFOs enabled       */
 176#define CH_TX_FIFO_EMPTY 0x0400         /* TX Fifo is completely empty  */
 177#define CH_TX_FIFO_LWM  0x0800          /* TX Fifo is below Low Water   */
 178#define CH_BREAK_SENDING 0x1000         /* Break is being sent          */
 179#define CH_LOOPBACK 0x2000              /* Channel is in lookback mode  */
 180#define CH_FLIPBUF_IN_USE 0x4000        /* Channel's flipbuf is in use  */
 181#define CH_BAUD0        0x08000         /* Used for checking B0 transitions */
 182
 183/* Our Read/Error/Write queue sizes */
 184#define RQUEUEMASK      0x1FFF          /* 8 K - 1 */
 185#define EQUEUEMASK      0x1FFF          /* 8 K - 1 */
 186#define WQUEUEMASK      0x0FFF          /* 4 K - 1 */
 187#define RQUEUESIZE      (RQUEUEMASK + 1)
 188#define EQUEUESIZE      RQUEUESIZE
 189#define WQUEUESIZE      (WQUEUEMASK + 1)
 190
 191
 192/************************************************************************
 193 * Channel information structure.
 194 ************************************************************************/
 195struct jsm_channel {
 196        struct uart_port uart_port;
 197        struct jsm_board        *ch_bd;         /* Board structure pointer      */
 198
 199        spinlock_t      ch_lock;        /* provide for serialization */
 200        wait_queue_head_t ch_flags_wait;
 201
 202        u32             ch_portnum;     /* Port number, 0 offset.       */
 203        u32             ch_open_count;  /* open count                   */
 204        u32             ch_flags;       /* Channel flags                */
 205
 206        u64             ch_close_delay; /* How long we should drop RTS/DTR for */
 207
 208        tcflag_t        ch_c_iflag;     /* channel iflags               */
 209        tcflag_t        ch_c_cflag;     /* channel cflags               */
 210        tcflag_t        ch_c_oflag;     /* channel oflags               */
 211        tcflag_t        ch_c_lflag;     /* channel lflags               */
 212        u8              ch_stopc;       /* Stop character               */
 213        u8              ch_startc;      /* Start character              */
 214
 215        u8              ch_mostat;      /* FEP output modem status      */
 216        u8              ch_mistat;      /* FEP input modem status       */
 217
 218        struct neo_uart_struct __iomem *ch_neo_uart;    /* Pointer to the "mapped" UART struct */
 219        u8              ch_cached_lsr;  /* Cached value of the LSR register */
 220
 221        u8              *ch_rqueue;     /* Our read queue buffer - malloc'ed */
 222        u16             ch_r_head;      /* Head location of the read queue */
 223        u16             ch_r_tail;      /* Tail location of the read queue */
 224
 225        u8              *ch_equeue;     /* Our error queue buffer - malloc'ed */
 226        u16             ch_e_head;      /* Head location of the error queue */
 227        u16             ch_e_tail;      /* Tail location of the error queue */
 228
 229        u8              *ch_wqueue;     /* Our write queue buffer - malloc'ed */
 230        u16             ch_w_head;      /* Head location of the write queue */
 231        u16             ch_w_tail;      /* Tail location of the write queue */
 232
 233        u64             ch_rxcount;     /* total of data received so far */
 234        u64             ch_txcount;     /* total of data transmitted so far */
 235
 236        u8              ch_r_tlevel;    /* Receive Trigger level */
 237        u8              ch_t_tlevel;    /* Transmit Trigger level */
 238
 239        u8              ch_r_watermark; /* Receive Watermark */
 240
 241
 242        u32             ch_stops_sent;  /* How many times I have sent a stop character
 243                                         * to try to stop the other guy sending.
 244                                         */
 245        u64             ch_err_parity;  /* Count of parity errors on channel */
 246        u64             ch_err_frame;   /* Count of framing errors on channel */
 247        u64             ch_err_break;   /* Count of breaks on channel */
 248        u64             ch_err_overrun; /* Count of overruns on channel */
 249
 250        u64             ch_xon_sends;   /* Count of xons transmitted */
 251        u64             ch_xoff_sends;  /* Count of xoffs transmitted */
 252};
 253
 254
 255/************************************************************************
 256 * Per channel/port NEO UART structure                                  *
 257 ************************************************************************
 258 *              Base Structure Entries Usage Meanings to Host           *
 259 *                                                                      *
 260 *      W = read write          R = read only                           *
 261 *                      U = Unused.                                     *
 262 ************************************************************************/
 263
 264struct neo_uart_struct {
 265         u8 txrx;               /* WR   RHR/THR - Holding Reg */
 266         u8 ier;                /* WR   IER - Interrupt Enable Reg */
 267         u8 isr_fcr;            /* WR   ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
 268         u8 lcr;                /* WR   LCR - Line Control Reg */
 269         u8 mcr;                /* WR   MCR - Modem Control Reg */
 270         u8 lsr;                /* WR   LSR - Line Status Reg */
 271         u8 msr;                /* WR   MSR - Modem Status Reg */
 272         u8 spr;                /* WR   SPR - Scratch Pad Reg */
 273         u8 fctr;               /* WR   FCTR - Feature Control Reg */
 274         u8 efr;                /* WR   EFR - Enhanced Function Reg */
 275         u8 tfifo;              /* WR   TXCNT/TXTRG - Transmit FIFO Reg */
 276         u8 rfifo;              /* WR   RXCNT/RXTRG - Recieve FIFO Reg */
 277         u8 xoffchar1;  /* WR   XOFF 1 - XOff Character 1 Reg */
 278         u8 xoffchar2;  /* WR   XOFF 2 - XOff Character 2 Reg */
 279         u8 xonchar1;   /* WR   XON 1 - Xon Character 1 Reg */
 280         u8 xonchar2;   /* WR   XON 2 - XOn Character 2 Reg */
 281
 282         u8 reserved1[0x2ff - 0x200]; /* U      Reserved by Exar */
 283         u8 txrxburst[64];      /* RW   64 bytes of RX/TX FIFO Data */
 284         u8 reserved2[0x37f - 0x340]; /* U      Reserved by Exar */
 285         u8 rxburst_with_errors[64];    /* R    64 bytes of RX FIFO Data + LSR */
 286};
 287
 288/* Where to read the extended interrupt register (32bits instead of 8bits) */
 289#define UART_17158_POLL_ADDR_OFFSET     0x80
 290
 291/*
 292 * These are the redefinitions for the FCTR on the XR17C158, since
 293 * Exar made them different than their earlier design. (XR16C854)
 294 */
 295
 296/* These are only applicable when table D is selected */
 297#define UART_17158_FCTR_RTS_NODELAY     0x00
 298#define UART_17158_FCTR_RTS_4DELAY      0x01
 299#define UART_17158_FCTR_RTS_6DELAY      0x02
 300#define UART_17158_FCTR_RTS_8DELAY      0x03
 301#define UART_17158_FCTR_RTS_12DELAY     0x12
 302#define UART_17158_FCTR_RTS_16DELAY     0x05
 303#define UART_17158_FCTR_RTS_20DELAY     0x13
 304#define UART_17158_FCTR_RTS_24DELAY     0x06
 305#define UART_17158_FCTR_RTS_28DELAY     0x14
 306#define UART_17158_FCTR_RTS_32DELAY     0x07
 307#define UART_17158_FCTR_RTS_36DELAY     0x16
 308#define UART_17158_FCTR_RTS_40DELAY     0x08
 309#define UART_17158_FCTR_RTS_44DELAY     0x09
 310#define UART_17158_FCTR_RTS_48DELAY     0x10
 311#define UART_17158_FCTR_RTS_52DELAY     0x11
 312
 313#define UART_17158_FCTR_RTS_IRDA        0x10
 314#define UART_17158_FCTR_RS485           0x20
 315#define UART_17158_FCTR_TRGA            0x00
 316#define UART_17158_FCTR_TRGB            0x40
 317#define UART_17158_FCTR_TRGC            0x80
 318#define UART_17158_FCTR_TRGD            0xC0
 319
 320/* 17158 trigger table selects.. */
 321#define UART_17158_FCTR_BIT6            0x40
 322#define UART_17158_FCTR_BIT7            0x80
 323
 324/* 17158 TX/RX memmapped buffer offsets */
 325#define UART_17158_RX_FIFOSIZE          64
 326#define UART_17158_TX_FIFOSIZE          64
 327
 328/* 17158 Extended IIR's */
 329#define UART_17158_IIR_RDI_TIMEOUT      0x0C    /* Receiver data TIMEOUT */
 330#define UART_17158_IIR_XONXOFF          0x10    /* Received an XON/XOFF char */
 331#define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */
 332#define UART_17158_IIR_FIFO_ENABLED     0xC0    /* 16550 FIFOs are Enabled */
 333
 334/*
 335 * These are the extended interrupts that get sent
 336 * back to us from the UART's 32bit interrupt register
 337 */
 338#define UART_17158_RX_LINE_STATUS       0x1     /* RX Ready */
 339#define UART_17158_RXRDY_TIMEOUT        0x2     /* RX Ready Timeout */
 340#define UART_17158_TXRDY                0x3     /* TX Ready */
 341#define UART_17158_MSR                  0x4     /* Modem State Change */
 342#define UART_17158_TX_AND_FIFO_CLR      0x40    /* Transmitter Holding Reg Empty */
 343#define UART_17158_RX_FIFO_DATA_ERROR   0x80    /* UART detected an RX FIFO Data error */
 344
 345/*
 346 * These are the EXTENDED definitions for the 17C158's Interrupt
 347 * Enable Register.
 348 */
 349#define UART_17158_EFR_ECB      0x10    /* Enhanced control bit */
 350#define UART_17158_EFR_IXON     0x2     /* Receiver compares Xon1/Xoff1 */
 351#define UART_17158_EFR_IXOFF    0x8     /* Transmit Xon1/Xoff1 */
 352#define UART_17158_EFR_RTSDTR   0x40    /* Auto RTS/DTR Flow Control Enable */
 353#define UART_17158_EFR_CTSDSR   0x80    /* Auto CTS/DSR Flow COntrol Enable */
 354
 355#define UART_17158_XOFF_DETECT  0x1     /* Indicates whether chip saw an incoming XOFF char */
 356#define UART_17158_XON_DETECT   0x2     /* Indicates whether chip saw an incoming XON char */
 357
 358#define UART_17158_IER_RSVD1    0x10    /* Reserved by Exar */
 359#define UART_17158_IER_XOFF     0x20    /* Xoff Interrupt Enable */
 360#define UART_17158_IER_RTSDTR   0x40    /* Output Interrupt Enable */
 361#define UART_17158_IER_CTSDSR   0x80    /* Input Interrupt Enable */
 362
 363#define PCI_DEVICE_NEO_2DB9_PCI_NAME            "Neo 2 - DB9 Universal PCI"
 364#define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME         "Neo 2 - DB9 Universal PCI - Powered Ring Indicator"
 365#define PCI_DEVICE_NEO_2RJ45_PCI_NAME           "Neo 2 - RJ45 Universal PCI"
 366#define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME        "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator"
 367#define PCIE_DEVICE_NEO_IBM_PCI_NAME            "Neo 4 - PCI Express - IBM"
 368
 369/*
 370 * Our Global Variables.
 371 */
 372extern struct   uart_driver jsm_uart_driver;
 373extern struct   board_ops jsm_neo_ops;
 374extern int      jsm_debug;
 375
 376/*************************************************************************
 377 *
 378 * Prototypes for non-static functions used in more than one module
 379 *
 380 *************************************************************************/
 381int jsm_tty_write(struct uart_port *port);
 382int jsm_tty_init(struct jsm_board *);
 383int jsm_uart_port_init(struct jsm_board *);
 384int jsm_remove_uart_port(struct jsm_board *);
 385void jsm_input(struct jsm_channel *ch);
 386void jsm_check_queue_flow_control(struct jsm_channel *ch);
 387
 388#endif
 389