1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#if defined(CONFIG_SERIAL_TXX9_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
23
24#include <linux/module.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/pci.h>
31#include <linux/serial_core.h>
32#include <linux/serial.h>
33
34#include <asm/io.h>
35
36static char *serial_version = "1.11";
37static char *serial_name = "TX39/49 Serial driver";
38
39#define PASS_LIMIT 256
40
41#if !defined(CONFIG_SERIAL_TXX9_STDSERIAL)
42
43#define TXX9_TTY_NAME "ttyTX"
44#define TXX9_TTY_MINOR_START 196
45#define TXX9_TTY_MAJOR 204
46#else
47
48#define TXX9_TTY_NAME "ttyS"
49#define TXX9_TTY_MINOR_START 64
50#define TXX9_TTY_MAJOR TTY_MAJOR
51#endif
52
53
54#define UPF_TXX9_HAVE_CTS_LINE UPF_BUGGY_UART
55#define UPF_TXX9_USE_SCLK UPF_MAGIC_MULTIPLIER
56
57#ifdef CONFIG_PCI
58
59#define ENABLE_SERIAL_TXX9_PCI
60#endif
61
62
63
64
65#define UART_NR CONFIG_SERIAL_TXX9_NR_UARTS
66
67struct uart_txx9_port {
68 struct uart_port port;
69
70};
71
72#define TXX9_REGION_SIZE 0x24
73
74
75#define TXX9_SILCR 0x00
76#define TXX9_SIDICR 0x04
77#define TXX9_SIDISR 0x08
78#define TXX9_SICISR 0x0c
79#define TXX9_SIFCR 0x10
80#define TXX9_SIFLCR 0x14
81#define TXX9_SIBGR 0x18
82#define TXX9_SITFIFO 0x1c
83#define TXX9_SIRFIFO 0x20
84
85
86#define TXX9_SILCR_SCS_MASK 0x00000060
87#define TXX9_SILCR_SCS_IMCLK 0x00000000
88#define TXX9_SILCR_SCS_IMCLK_BG 0x00000020
89#define TXX9_SILCR_SCS_SCLK 0x00000040
90#define TXX9_SILCR_SCS_SCLK_BG 0x00000060
91#define TXX9_SILCR_UEPS 0x00000010
92#define TXX9_SILCR_UPEN 0x00000008
93#define TXX9_SILCR_USBL_MASK 0x00000004
94#define TXX9_SILCR_USBL_1BIT 0x00000000
95#define TXX9_SILCR_USBL_2BIT 0x00000004
96#define TXX9_SILCR_UMODE_MASK 0x00000003
97#define TXX9_SILCR_UMODE_8BIT 0x00000000
98#define TXX9_SILCR_UMODE_7BIT 0x00000001
99
100
101#define TXX9_SIDICR_TDE 0x00008000
102#define TXX9_SIDICR_RDE 0x00004000
103#define TXX9_SIDICR_TIE 0x00002000
104#define TXX9_SIDICR_RIE 0x00001000
105#define TXX9_SIDICR_SPIE 0x00000800
106#define TXX9_SIDICR_CTSAC 0x00000600
107#define TXX9_SIDICR_STIE_MASK 0x0000003f
108#define TXX9_SIDICR_STIE_OERS 0x00000020
109#define TXX9_SIDICR_STIE_CTSS 0x00000010
110#define TXX9_SIDICR_STIE_RBRKD 0x00000008
111#define TXX9_SIDICR_STIE_TRDY 0x00000004
112#define TXX9_SIDICR_STIE_TXALS 0x00000002
113#define TXX9_SIDICR_STIE_UBRKD 0x00000001
114
115
116#define TXX9_SIDISR_UBRK 0x00008000
117#define TXX9_SIDISR_UVALID 0x00004000
118#define TXX9_SIDISR_UFER 0x00002000
119#define TXX9_SIDISR_UPER 0x00001000
120#define TXX9_SIDISR_UOER 0x00000800
121#define TXX9_SIDISR_ERI 0x00000400
122#define TXX9_SIDISR_TOUT 0x00000200
123#define TXX9_SIDISR_TDIS 0x00000100
124#define TXX9_SIDISR_RDIS 0x00000080
125#define TXX9_SIDISR_STIS 0x00000040
126#define TXX9_SIDISR_RFDN_MASK 0x0000001f
127
128
129#define TXX9_SICISR_OERS 0x00000020
130#define TXX9_SICISR_CTSS 0x00000010
131#define TXX9_SICISR_RBRKD 0x00000008
132#define TXX9_SICISR_TRDY 0x00000004
133#define TXX9_SICISR_TXALS 0x00000002
134#define TXX9_SICISR_UBRKD 0x00000001
135
136
137#define TXX9_SIFCR_SWRST 0x00008000
138#define TXX9_SIFCR_RDIL_MASK 0x00000180
139#define TXX9_SIFCR_RDIL_1 0x00000000
140#define TXX9_SIFCR_RDIL_4 0x00000080
141#define TXX9_SIFCR_RDIL_8 0x00000100
142#define TXX9_SIFCR_RDIL_12 0x00000180
143#define TXX9_SIFCR_RDIL_MAX 0x00000180
144#define TXX9_SIFCR_TDIL_MASK 0x00000018
145#define TXX9_SIFCR_TDIL_MASK 0x00000018
146#define TXX9_SIFCR_TDIL_1 0x00000000
147#define TXX9_SIFCR_TDIL_4 0x00000001
148#define TXX9_SIFCR_TDIL_8 0x00000010
149#define TXX9_SIFCR_TDIL_MAX 0x00000010
150#define TXX9_SIFCR_TFRST 0x00000004
151#define TXX9_SIFCR_RFRST 0x00000002
152#define TXX9_SIFCR_FRSTE 0x00000001
153#define TXX9_SIO_TX_FIFO 8
154#define TXX9_SIO_RX_FIFO 16
155
156
157#define TXX9_SIFLCR_RCS 0x00001000
158#define TXX9_SIFLCR_TES 0x00000800
159#define TXX9_SIFLCR_RTSSC 0x00000200
160#define TXX9_SIFLCR_RSDE 0x00000100
161#define TXX9_SIFLCR_TSDE 0x00000080
162#define TXX9_SIFLCR_RTSTL_MASK 0x0000001e
163#define TXX9_SIFLCR_RTSTL_MAX 0x0000001e
164#define TXX9_SIFLCR_TBRK 0x00000001
165
166
167#define TXX9_SIBGR_BCLK_MASK 0x00000300
168#define TXX9_SIBGR_BCLK_T0 0x00000000
169#define TXX9_SIBGR_BCLK_T2 0x00000100
170#define TXX9_SIBGR_BCLK_T4 0x00000200
171#define TXX9_SIBGR_BCLK_T6 0x00000300
172#define TXX9_SIBGR_BRD_MASK 0x000000ff
173
174static inline unsigned int sio_in(struct uart_txx9_port *up, int offset)
175{
176 switch (up->port.iotype) {
177 default:
178 return __raw_readl(up->port.membase + offset);
179 case UPIO_PORT:
180 return inl(up->port.iobase + offset);
181 }
182}
183
184static inline void
185sio_out(struct uart_txx9_port *up, int offset, int value)
186{
187 switch (up->port.iotype) {
188 default:
189 __raw_writel(value, up->port.membase + offset);
190 break;
191 case UPIO_PORT:
192 outl(value, up->port.iobase + offset);
193 break;
194 }
195}
196
197static inline void
198sio_mask(struct uart_txx9_port *up, int offset, unsigned int value)
199{
200 sio_out(up, offset, sio_in(up, offset) & ~value);
201}
202static inline void
203sio_set(struct uart_txx9_port *up, int offset, unsigned int value)
204{
205 sio_out(up, offset, sio_in(up, offset) | value);
206}
207
208static inline void
209sio_quot_set(struct uart_txx9_port *up, int quot)
210{
211 quot >>= 1;
212 if (quot < 256)
213 sio_out(up, TXX9_SIBGR, quot | TXX9_SIBGR_BCLK_T0);
214 else if (quot < (256 << 2))
215 sio_out(up, TXX9_SIBGR, (quot >> 2) | TXX9_SIBGR_BCLK_T2);
216 else if (quot < (256 << 4))
217 sio_out(up, TXX9_SIBGR, (quot >> 4) | TXX9_SIBGR_BCLK_T4);
218 else if (quot < (256 << 6))
219 sio_out(up, TXX9_SIBGR, (quot >> 6) | TXX9_SIBGR_BCLK_T6);
220 else
221 sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6);
222}
223
224static struct uart_txx9_port *to_uart_txx9_port(struct uart_port *port)
225{
226 return container_of(port, struct uart_txx9_port, port);
227}
228
229static void serial_txx9_stop_tx(struct uart_port *port)
230{
231 struct uart_txx9_port *up = to_uart_txx9_port(port);
232 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
233}
234
235static void serial_txx9_start_tx(struct uart_port *port)
236{
237 struct uart_txx9_port *up = to_uart_txx9_port(port);
238 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
239}
240
241static void serial_txx9_stop_rx(struct uart_port *port)
242{
243 struct uart_txx9_port *up = to_uart_txx9_port(port);
244 up->port.read_status_mask &= ~TXX9_SIDISR_RDIS;
245}
246
247static void serial_txx9_enable_ms(struct uart_port *port)
248{
249
250}
251
252static void serial_txx9_initialize(struct uart_port *port)
253{
254 struct uart_txx9_port *up = to_uart_txx9_port(port);
255 unsigned int tmout = 10000;
256
257 sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST);
258
259
260 mmiowb();
261 udelay(1);
262 while ((sio_in(up, TXX9_SIFCR) & TXX9_SIFCR_SWRST) && --tmout)
263 udelay(1);
264
265 sio_set(up, TXX9_SIFCR,
266 TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1);
267
268 sio_out(up, TXX9_SILCR,
269 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
270 ((up->port.flags & UPF_TXX9_USE_SCLK) ?
271 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
272 sio_quot_set(up, uart_get_divisor(port, 9600));
273 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX );
274 sio_out(up, TXX9_SIDICR, 0);
275}
276
277static inline void
278receive_chars(struct uart_txx9_port *up, unsigned int *status)
279{
280 struct tty_struct *tty = up->port.state->port.tty;
281 unsigned char ch;
282 unsigned int disr = *status;
283 int max_count = 256;
284 char flag;
285 unsigned int next_ignore_status_mask;
286
287 do {
288 ch = sio_in(up, TXX9_SIRFIFO);
289 flag = TTY_NORMAL;
290 up->port.icount.rx++;
291
292
293 next_ignore_status_mask =
294 up->port.ignore_status_mask & ~TXX9_SIDISR_RFDN_MASK;
295 if (unlikely(disr & (TXX9_SIDISR_UBRK | TXX9_SIDISR_UPER |
296 TXX9_SIDISR_UFER | TXX9_SIDISR_UOER))) {
297
298
299
300 if (disr & TXX9_SIDISR_UBRK) {
301 disr &= ~(TXX9_SIDISR_UFER | TXX9_SIDISR_UPER);
302 up->port.icount.brk++;
303
304
305
306
307
308
309 if (uart_handle_break(&up->port))
310 goto ignore_char;
311 } else if (disr & TXX9_SIDISR_UPER)
312 up->port.icount.parity++;
313 else if (disr & TXX9_SIDISR_UFER)
314 up->port.icount.frame++;
315 if (disr & TXX9_SIDISR_UOER) {
316 up->port.icount.overrun++;
317
318
319
320
321
322
323 next_ignore_status_mask |=
324 TXX9_SIDISR_RFDN_MASK;
325 }
326
327
328
329
330 disr &= up->port.read_status_mask;
331
332 if (disr & TXX9_SIDISR_UBRK) {
333 flag = TTY_BREAK;
334 } else if (disr & TXX9_SIDISR_UPER)
335 flag = TTY_PARITY;
336 else if (disr & TXX9_SIDISR_UFER)
337 flag = TTY_FRAME;
338 }
339 if (uart_handle_sysrq_char(&up->port, ch))
340 goto ignore_char;
341
342 uart_insert_char(&up->port, disr, TXX9_SIDISR_UOER, ch, flag);
343
344 ignore_char:
345 up->port.ignore_status_mask = next_ignore_status_mask;
346 disr = sio_in(up, TXX9_SIDISR);
347 } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0));
348 spin_unlock(&up->port.lock);
349 tty_flip_buffer_push(tty);
350 spin_lock(&up->port.lock);
351 *status = disr;
352}
353
354static inline void transmit_chars(struct uart_txx9_port *up)
355{
356 struct circ_buf *xmit = &up->port.state->xmit;
357 int count;
358
359 if (up->port.x_char) {
360 sio_out(up, TXX9_SITFIFO, up->port.x_char);
361 up->port.icount.tx++;
362 up->port.x_char = 0;
363 return;
364 }
365 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
366 serial_txx9_stop_tx(&up->port);
367 return;
368 }
369
370 count = TXX9_SIO_TX_FIFO;
371 do {
372 sio_out(up, TXX9_SITFIFO, xmit->buf[xmit->tail]);
373 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
374 up->port.icount.tx++;
375 if (uart_circ_empty(xmit))
376 break;
377 } while (--count > 0);
378
379 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
380 uart_write_wakeup(&up->port);
381
382 if (uart_circ_empty(xmit))
383 serial_txx9_stop_tx(&up->port);
384}
385
386static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id)
387{
388 int pass_counter = 0;
389 struct uart_txx9_port *up = dev_id;
390 unsigned int status;
391
392 while (1) {
393 spin_lock(&up->port.lock);
394 status = sio_in(up, TXX9_SIDISR);
395 if (!(sio_in(up, TXX9_SIDICR) & TXX9_SIDICR_TIE))
396 status &= ~TXX9_SIDISR_TDIS;
397 if (!(status & (TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
398 TXX9_SIDISR_TOUT))) {
399 spin_unlock(&up->port.lock);
400 break;
401 }
402
403 if (status & TXX9_SIDISR_RDIS)
404 receive_chars(up, &status);
405 if (status & TXX9_SIDISR_TDIS)
406 transmit_chars(up);
407
408 sio_mask(up, TXX9_SIDISR,
409 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
410 TXX9_SIDISR_TOUT);
411 spin_unlock(&up->port.lock);
412
413 if (pass_counter++ > PASS_LIMIT)
414 break;
415 }
416
417 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
418}
419
420static unsigned int serial_txx9_tx_empty(struct uart_port *port)
421{
422 struct uart_txx9_port *up = to_uart_txx9_port(port);
423 unsigned long flags;
424 unsigned int ret;
425
426 spin_lock_irqsave(&up->port.lock, flags);
427 ret = (sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS) ? TIOCSER_TEMT : 0;
428 spin_unlock_irqrestore(&up->port.lock, flags);
429
430 return ret;
431}
432
433static unsigned int serial_txx9_get_mctrl(struct uart_port *port)
434{
435 struct uart_txx9_port *up = to_uart_txx9_port(port);
436 unsigned int ret;
437
438
439 ret = TIOCM_CAR | TIOCM_DSR;
440 ret |= (sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS;
441 ret |= (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS;
442
443 return ret;
444}
445
446static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl)
447{
448 struct uart_txx9_port *up = to_uart_txx9_port(port);
449
450 if (mctrl & TIOCM_RTS)
451 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
452 else
453 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
454}
455
456static void serial_txx9_break_ctl(struct uart_port *port, int break_state)
457{
458 struct uart_txx9_port *up = to_uart_txx9_port(port);
459 unsigned long flags;
460
461 spin_lock_irqsave(&up->port.lock, flags);
462 if (break_state == -1)
463 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
464 else
465 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
466 spin_unlock_irqrestore(&up->port.lock, flags);
467}
468
469#if defined(CONFIG_SERIAL_TXX9_CONSOLE) || (CONFIG_CONSOLE_POLL)
470
471
472
473static void wait_for_xmitr(struct uart_txx9_port *up)
474{
475 unsigned int tmout = 10000;
476
477
478 while (--tmout &&
479 !(sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS))
480 udelay(1);
481
482
483 if (up->port.flags & UPF_CONS_FLOW) {
484 tmout = 1000000;
485 while (--tmout &&
486 (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS))
487 udelay(1);
488 }
489}
490#endif
491
492#ifdef CONFIG_CONSOLE_POLL
493
494
495
496
497
498static int serial_txx9_get_poll_char(struct uart_port *port)
499{
500 unsigned int ier;
501 unsigned char c;
502 struct uart_txx9_port *up = to_uart_txx9_port(port);
503
504
505
506
507 ier = sio_in(up, TXX9_SIDICR);
508 sio_out(up, TXX9_SIDICR, 0);
509
510 while (sio_in(up, TXX9_SIDISR) & TXX9_SIDISR_UVALID)
511 ;
512
513 c = sio_in(up, TXX9_SIRFIFO);
514
515
516
517
518
519 sio_mask(up, TXX9_SIDISR, TXX9_SIDISR_RDIS);
520 sio_out(up, TXX9_SIDICR, ier);
521 return c;
522}
523
524
525static void serial_txx9_put_poll_char(struct uart_port *port, unsigned char c)
526{
527 unsigned int ier;
528 struct uart_txx9_port *up = to_uart_txx9_port(port);
529
530
531
532
533 ier = sio_in(up, TXX9_SIDICR);
534 sio_out(up, TXX9_SIDICR, 0);
535
536 wait_for_xmitr(up);
537
538
539
540
541 sio_out(up, TXX9_SITFIFO, c);
542 if (c == 10) {
543 wait_for_xmitr(up);
544 sio_out(up, TXX9_SITFIFO, 13);
545 }
546
547
548
549
550
551 wait_for_xmitr(up);
552 sio_out(up, TXX9_SIDICR, ier);
553}
554
555#endif
556
557static int serial_txx9_startup(struct uart_port *port)
558{
559 struct uart_txx9_port *up = to_uart_txx9_port(port);
560 unsigned long flags;
561 int retval;
562
563
564
565
566
567 sio_set(up, TXX9_SIFCR,
568 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
569
570 sio_mask(up, TXX9_SIFCR,
571 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
572 sio_out(up, TXX9_SIDICR, 0);
573
574
575
576
577 sio_out(up, TXX9_SIDISR, 0);
578
579 retval = request_irq(up->port.irq, serial_txx9_interrupt,
580 IRQF_SHARED, "serial_txx9", up);
581 if (retval)
582 return retval;
583
584
585
586
587 spin_lock_irqsave(&up->port.lock, flags);
588 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
589 spin_unlock_irqrestore(&up->port.lock, flags);
590
591
592 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
593
594
595
596
597 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
598
599 return 0;
600}
601
602static void serial_txx9_shutdown(struct uart_port *port)
603{
604 struct uart_txx9_port *up = to_uart_txx9_port(port);
605 unsigned long flags;
606
607
608
609
610 sio_out(up, TXX9_SIDICR, 0);
611
612 spin_lock_irqsave(&up->port.lock, flags);
613 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
614 spin_unlock_irqrestore(&up->port.lock, flags);
615
616
617
618
619 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
620
621#ifdef CONFIG_SERIAL_TXX9_CONSOLE
622 if (up->port.cons && up->port.line == up->port.cons->index) {
623 free_irq(up->port.irq, up);
624 return;
625 }
626#endif
627
628 sio_set(up, TXX9_SIFCR,
629 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
630
631 sio_mask(up, TXX9_SIFCR,
632 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
633
634
635 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
636
637 free_irq(up->port.irq, up);
638}
639
640static void
641serial_txx9_set_termios(struct uart_port *port, struct ktermios *termios,
642 struct ktermios *old)
643{
644 struct uart_txx9_port *up = to_uart_txx9_port(port);
645 unsigned int cval, fcr = 0;
646 unsigned long flags;
647 unsigned int baud, quot;
648
649
650
651
652 termios->c_cflag &= ~(HUPCL | CMSPAR);
653 termios->c_cflag |= CLOCAL;
654
655 cval = sio_in(up, TXX9_SILCR);
656
657 cval &= ~TXX9_SILCR_UMODE_MASK;
658 switch (termios->c_cflag & CSIZE) {
659 case CS7:
660 cval |= TXX9_SILCR_UMODE_7BIT;
661 break;
662 default:
663 case CS5:
664 case CS6:
665 case CS8:
666 cval |= TXX9_SILCR_UMODE_8BIT;
667 break;
668 }
669
670 cval &= ~TXX9_SILCR_USBL_MASK;
671 if (termios->c_cflag & CSTOPB)
672 cval |= TXX9_SILCR_USBL_2BIT;
673 else
674 cval |= TXX9_SILCR_USBL_1BIT;
675 cval &= ~(TXX9_SILCR_UPEN | TXX9_SILCR_UEPS);
676 if (termios->c_cflag & PARENB)
677 cval |= TXX9_SILCR_UPEN;
678 if (!(termios->c_cflag & PARODD))
679 cval |= TXX9_SILCR_UEPS;
680
681
682
683
684 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16/2);
685 quot = uart_get_divisor(port, baud);
686
687
688
689 fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1;
690
691
692
693
694
695 spin_lock_irqsave(&up->port.lock, flags);
696
697
698
699
700 uart_update_timeout(port, termios->c_cflag, baud);
701
702 up->port.read_status_mask = TXX9_SIDISR_UOER |
703 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS;
704 if (termios->c_iflag & INPCK)
705 up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER;
706 if (termios->c_iflag & (BRKINT | PARMRK))
707 up->port.read_status_mask |= TXX9_SIDISR_UBRK;
708
709
710
711
712 up->port.ignore_status_mask = 0;
713 if (termios->c_iflag & IGNPAR)
714 up->port.ignore_status_mask |= TXX9_SIDISR_UPER | TXX9_SIDISR_UFER;
715 if (termios->c_iflag & IGNBRK) {
716 up->port.ignore_status_mask |= TXX9_SIDISR_UBRK;
717
718
719
720
721 if (termios->c_iflag & IGNPAR)
722 up->port.ignore_status_mask |= TXX9_SIDISR_UOER;
723 }
724
725
726
727
728 if ((termios->c_cflag & CREAD) == 0)
729 up->port.ignore_status_mask |= TXX9_SIDISR_RDIS;
730
731
732 if ((termios->c_cflag & CRTSCTS) &&
733 (up->port.flags & UPF_TXX9_HAVE_CTS_LINE)) {
734 sio_set(up, TXX9_SIFLCR,
735 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
736 } else {
737 sio_mask(up, TXX9_SIFLCR,
738 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
739 }
740
741 sio_out(up, TXX9_SILCR, cval);
742 sio_quot_set(up, quot);
743 sio_out(up, TXX9_SIFCR, fcr);
744
745 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
746 spin_unlock_irqrestore(&up->port.lock, flags);
747}
748
749static void
750serial_txx9_pm(struct uart_port *port, unsigned int state,
751 unsigned int oldstate)
752{
753
754
755
756
757
758
759
760
761 if (state == 0 && oldstate != -1)
762 serial_txx9_initialize(port);
763}
764
765static int serial_txx9_request_resource(struct uart_txx9_port *up)
766{
767 unsigned int size = TXX9_REGION_SIZE;
768 int ret = 0;
769
770 switch (up->port.iotype) {
771 default:
772 if (!up->port.mapbase)
773 break;
774
775 if (!request_mem_region(up->port.mapbase, size, "serial_txx9")) {
776 ret = -EBUSY;
777 break;
778 }
779
780 if (up->port.flags & UPF_IOREMAP) {
781 up->port.membase = ioremap(up->port.mapbase, size);
782 if (!up->port.membase) {
783 release_mem_region(up->port.mapbase, size);
784 ret = -ENOMEM;
785 }
786 }
787 break;
788
789 case UPIO_PORT:
790 if (!request_region(up->port.iobase, size, "serial_txx9"))
791 ret = -EBUSY;
792 break;
793 }
794 return ret;
795}
796
797static void serial_txx9_release_resource(struct uart_txx9_port *up)
798{
799 unsigned int size = TXX9_REGION_SIZE;
800
801 switch (up->port.iotype) {
802 default:
803 if (!up->port.mapbase)
804 break;
805
806 if (up->port.flags & UPF_IOREMAP) {
807 iounmap(up->port.membase);
808 up->port.membase = NULL;
809 }
810
811 release_mem_region(up->port.mapbase, size);
812 break;
813
814 case UPIO_PORT:
815 release_region(up->port.iobase, size);
816 break;
817 }
818}
819
820static void serial_txx9_release_port(struct uart_port *port)
821{
822 struct uart_txx9_port *up = to_uart_txx9_port(port);
823 serial_txx9_release_resource(up);
824}
825
826static int serial_txx9_request_port(struct uart_port *port)
827{
828 struct uart_txx9_port *up = to_uart_txx9_port(port);
829 return serial_txx9_request_resource(up);
830}
831
832static void serial_txx9_config_port(struct uart_port *port, int uflags)
833{
834 struct uart_txx9_port *up = to_uart_txx9_port(port);
835 int ret;
836
837
838
839
840
841 ret = serial_txx9_request_resource(up);
842 if (ret < 0)
843 return;
844 port->type = PORT_TXX9;
845 up->port.fifosize = TXX9_SIO_TX_FIFO;
846
847#ifdef CONFIG_SERIAL_TXX9_CONSOLE
848 if (up->port.line == up->port.cons->index)
849 return;
850#endif
851 serial_txx9_initialize(port);
852}
853
854static const char *
855serial_txx9_type(struct uart_port *port)
856{
857 return "txx9";
858}
859
860static struct uart_ops serial_txx9_pops = {
861 .tx_empty = serial_txx9_tx_empty,
862 .set_mctrl = serial_txx9_set_mctrl,
863 .get_mctrl = serial_txx9_get_mctrl,
864 .stop_tx = serial_txx9_stop_tx,
865 .start_tx = serial_txx9_start_tx,
866 .stop_rx = serial_txx9_stop_rx,
867 .enable_ms = serial_txx9_enable_ms,
868 .break_ctl = serial_txx9_break_ctl,
869 .startup = serial_txx9_startup,
870 .shutdown = serial_txx9_shutdown,
871 .set_termios = serial_txx9_set_termios,
872 .pm = serial_txx9_pm,
873 .type = serial_txx9_type,
874 .release_port = serial_txx9_release_port,
875 .request_port = serial_txx9_request_port,
876 .config_port = serial_txx9_config_port,
877#ifdef CONFIG_CONSOLE_POLL
878 .poll_get_char = serial_txx9_get_poll_char,
879 .poll_put_char = serial_txx9_put_poll_char,
880#endif
881};
882
883static struct uart_txx9_port serial_txx9_ports[UART_NR];
884
885static void __init serial_txx9_register_ports(struct uart_driver *drv,
886 struct device *dev)
887{
888 int i;
889
890 for (i = 0; i < UART_NR; i++) {
891 struct uart_txx9_port *up = &serial_txx9_ports[i];
892
893 up->port.line = i;
894 up->port.ops = &serial_txx9_pops;
895 up->port.dev = dev;
896 if (up->port.iobase || up->port.mapbase)
897 uart_add_one_port(drv, &up->port);
898 }
899}
900
901#ifdef CONFIG_SERIAL_TXX9_CONSOLE
902
903static void serial_txx9_console_putchar(struct uart_port *port, int ch)
904{
905 struct uart_txx9_port *up = to_uart_txx9_port(port);
906
907 wait_for_xmitr(up);
908 sio_out(up, TXX9_SITFIFO, ch);
909}
910
911
912
913
914
915
916
917static void
918serial_txx9_console_write(struct console *co, const char *s, unsigned int count)
919{
920 struct uart_txx9_port *up = &serial_txx9_ports[co->index];
921 unsigned int ier, flcr;
922
923
924
925
926 ier = sio_in(up, TXX9_SIDICR);
927 sio_out(up, TXX9_SIDICR, 0);
928
929
930
931 flcr = sio_in(up, TXX9_SIFLCR);
932 if (!(up->port.flags & UPF_CONS_FLOW) && (flcr & TXX9_SIFLCR_TES))
933 sio_out(up, TXX9_SIFLCR, flcr & ~TXX9_SIFLCR_TES);
934
935 uart_console_write(&up->port, s, count, serial_txx9_console_putchar);
936
937
938
939
940
941 wait_for_xmitr(up);
942 sio_out(up, TXX9_SIFLCR, flcr);
943 sio_out(up, TXX9_SIDICR, ier);
944}
945
946static int __init serial_txx9_console_setup(struct console *co, char *options)
947{
948 struct uart_port *port;
949 struct uart_txx9_port *up;
950 int baud = 9600;
951 int bits = 8;
952 int parity = 'n';
953 int flow = 'n';
954
955
956
957
958
959
960 if (co->index >= UART_NR)
961 co->index = 0;
962 up = &serial_txx9_ports[co->index];
963 port = &up->port;
964 if (!port->ops)
965 return -ENODEV;
966
967 serial_txx9_initialize(&up->port);
968
969 if (options)
970 uart_parse_options(options, &baud, &parity, &bits, &flow);
971
972 return uart_set_options(port, co, baud, parity, bits, flow);
973}
974
975static struct uart_driver serial_txx9_reg;
976static struct console serial_txx9_console = {
977 .name = TXX9_TTY_NAME,
978 .write = serial_txx9_console_write,
979 .device = uart_console_device,
980 .setup = serial_txx9_console_setup,
981 .flags = CON_PRINTBUFFER,
982 .index = -1,
983 .data = &serial_txx9_reg,
984};
985
986static int __init serial_txx9_console_init(void)
987{
988 register_console(&serial_txx9_console);
989 return 0;
990}
991console_initcall(serial_txx9_console_init);
992
993#define SERIAL_TXX9_CONSOLE &serial_txx9_console
994#else
995#define SERIAL_TXX9_CONSOLE NULL
996#endif
997
998static struct uart_driver serial_txx9_reg = {
999 .owner = THIS_MODULE,
1000 .driver_name = "serial_txx9",
1001 .dev_name = TXX9_TTY_NAME,
1002 .major = TXX9_TTY_MAJOR,
1003 .minor = TXX9_TTY_MINOR_START,
1004 .nr = UART_NR,
1005 .cons = SERIAL_TXX9_CONSOLE,
1006};
1007
1008int __init early_serial_txx9_setup(struct uart_port *port)
1009{
1010 if (port->line >= ARRAY_SIZE(serial_txx9_ports))
1011 return -ENODEV;
1012
1013 serial_txx9_ports[port->line].port = *port;
1014 serial_txx9_ports[port->line].port.ops = &serial_txx9_pops;
1015 serial_txx9_ports[port->line].port.flags |=
1016 UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
1017 return 0;
1018}
1019
1020static DEFINE_MUTEX(serial_txx9_mutex);
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033static int __devinit serial_txx9_register_port(struct uart_port *port)
1034{
1035 int i;
1036 struct uart_txx9_port *uart;
1037 int ret = -ENOSPC;
1038
1039 mutex_lock(&serial_txx9_mutex);
1040 for (i = 0; i < UART_NR; i++) {
1041 uart = &serial_txx9_ports[i];
1042 if (uart_match_port(&uart->port, port)) {
1043 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1044 break;
1045 }
1046 }
1047 if (i == UART_NR) {
1048
1049 for (i = 0; i < UART_NR; i++) {
1050 uart = &serial_txx9_ports[i];
1051 if (!(uart->port.iobase || uart->port.mapbase))
1052 break;
1053 }
1054 }
1055 if (i < UART_NR) {
1056 uart->port.iobase = port->iobase;
1057 uart->port.membase = port->membase;
1058 uart->port.irq = port->irq;
1059 uart->port.uartclk = port->uartclk;
1060 uart->port.iotype = port->iotype;
1061 uart->port.flags = port->flags
1062 | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
1063 uart->port.mapbase = port->mapbase;
1064 if (port->dev)
1065 uart->port.dev = port->dev;
1066 ret = uart_add_one_port(&serial_txx9_reg, &uart->port);
1067 if (ret == 0)
1068 ret = uart->port.line;
1069 }
1070 mutex_unlock(&serial_txx9_mutex);
1071 return ret;
1072}
1073
1074
1075
1076
1077
1078
1079
1080
1081static void __devexit serial_txx9_unregister_port(int line)
1082{
1083 struct uart_txx9_port *uart = &serial_txx9_ports[line];
1084
1085 mutex_lock(&serial_txx9_mutex);
1086 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1087 uart->port.flags = 0;
1088 uart->port.type = PORT_UNKNOWN;
1089 uart->port.iobase = 0;
1090 uart->port.mapbase = 0;
1091 uart->port.membase = NULL;
1092 uart->port.dev = NULL;
1093 mutex_unlock(&serial_txx9_mutex);
1094}
1095
1096
1097
1098
1099static int __devinit serial_txx9_probe(struct platform_device *dev)
1100{
1101 struct uart_port *p = dev->dev.platform_data;
1102 struct uart_port port;
1103 int ret, i;
1104
1105 memset(&port, 0, sizeof(struct uart_port));
1106 for (i = 0; p && p->uartclk != 0; p++, i++) {
1107 port.iobase = p->iobase;
1108 port.membase = p->membase;
1109 port.irq = p->irq;
1110 port.uartclk = p->uartclk;
1111 port.iotype = p->iotype;
1112 port.flags = p->flags;
1113 port.mapbase = p->mapbase;
1114 port.dev = &dev->dev;
1115 ret = serial_txx9_register_port(&port);
1116 if (ret < 0) {
1117 dev_err(&dev->dev, "unable to register port at index %d "
1118 "(IO%lx MEM%llx IRQ%d): %d\n", i,
1119 p->iobase, (unsigned long long)p->mapbase,
1120 p->irq, ret);
1121 }
1122 }
1123 return 0;
1124}
1125
1126
1127
1128
1129static int __devexit serial_txx9_remove(struct platform_device *dev)
1130{
1131 int i;
1132
1133 for (i = 0; i < UART_NR; i++) {
1134 struct uart_txx9_port *up = &serial_txx9_ports[i];
1135
1136 if (up->port.dev == &dev->dev)
1137 serial_txx9_unregister_port(i);
1138 }
1139 return 0;
1140}
1141
1142#ifdef CONFIG_PM
1143static int serial_txx9_suspend(struct platform_device *dev, pm_message_t state)
1144{
1145 int i;
1146
1147 for (i = 0; i < UART_NR; i++) {
1148 struct uart_txx9_port *up = &serial_txx9_ports[i];
1149
1150 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1151 uart_suspend_port(&serial_txx9_reg, &up->port);
1152 }
1153
1154 return 0;
1155}
1156
1157static int serial_txx9_resume(struct platform_device *dev)
1158{
1159 int i;
1160
1161 for (i = 0; i < UART_NR; i++) {
1162 struct uart_txx9_port *up = &serial_txx9_ports[i];
1163
1164 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1165 uart_resume_port(&serial_txx9_reg, &up->port);
1166 }
1167
1168 return 0;
1169}
1170#endif
1171
1172static struct platform_driver serial_txx9_plat_driver = {
1173 .probe = serial_txx9_probe,
1174 .remove = __devexit_p(serial_txx9_remove),
1175#ifdef CONFIG_PM
1176 .suspend = serial_txx9_suspend,
1177 .resume = serial_txx9_resume,
1178#endif
1179 .driver = {
1180 .name = "serial_txx9",
1181 .owner = THIS_MODULE,
1182 },
1183};
1184
1185#ifdef ENABLE_SERIAL_TXX9_PCI
1186
1187
1188
1189
1190static int __devinit
1191pciserial_txx9_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1192{
1193 struct uart_port port;
1194 int line;
1195 int rc;
1196
1197 rc = pci_enable_device(dev);
1198 if (rc)
1199 return rc;
1200
1201 memset(&port, 0, sizeof(port));
1202 port.ops = &serial_txx9_pops;
1203 port.flags |= UPF_TXX9_HAVE_CTS_LINE;
1204 port.uartclk = 66670000;
1205 port.irq = dev->irq;
1206 port.iotype = UPIO_PORT;
1207 port.iobase = pci_resource_start(dev, 1);
1208 port.dev = &dev->dev;
1209 line = serial_txx9_register_port(&port);
1210 if (line < 0) {
1211 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), line);
1212 pci_disable_device(dev);
1213 return line;
1214 }
1215 pci_set_drvdata(dev, &serial_txx9_ports[line]);
1216
1217 return 0;
1218}
1219
1220static void __devexit pciserial_txx9_remove_one(struct pci_dev *dev)
1221{
1222 struct uart_txx9_port *up = pci_get_drvdata(dev);
1223
1224 pci_set_drvdata(dev, NULL);
1225
1226 if (up) {
1227 serial_txx9_unregister_port(up->port.line);
1228 pci_disable_device(dev);
1229 }
1230}
1231
1232#ifdef CONFIG_PM
1233static int pciserial_txx9_suspend_one(struct pci_dev *dev, pm_message_t state)
1234{
1235 struct uart_txx9_port *up = pci_get_drvdata(dev);
1236
1237 if (up)
1238 uart_suspend_port(&serial_txx9_reg, &up->port);
1239 pci_save_state(dev);
1240 pci_set_power_state(dev, pci_choose_state(dev, state));
1241 return 0;
1242}
1243
1244static int pciserial_txx9_resume_one(struct pci_dev *dev)
1245{
1246 struct uart_txx9_port *up = pci_get_drvdata(dev);
1247
1248 pci_set_power_state(dev, PCI_D0);
1249 pci_restore_state(dev);
1250 if (up)
1251 uart_resume_port(&serial_txx9_reg, &up->port);
1252 return 0;
1253}
1254#endif
1255
1256static const struct pci_device_id serial_txx9_pci_tbl[] = {
1257 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC) },
1258 { 0, }
1259};
1260
1261static struct pci_driver serial_txx9_pci_driver = {
1262 .name = "serial_txx9",
1263 .probe = pciserial_txx9_init_one,
1264 .remove = __devexit_p(pciserial_txx9_remove_one),
1265#ifdef CONFIG_PM
1266 .suspend = pciserial_txx9_suspend_one,
1267 .resume = pciserial_txx9_resume_one,
1268#endif
1269 .id_table = serial_txx9_pci_tbl,
1270};
1271
1272MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl);
1273#endif
1274
1275static struct platform_device *serial_txx9_plat_devs;
1276
1277static int __init serial_txx9_init(void)
1278{
1279 int ret;
1280
1281 printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
1282
1283 ret = uart_register_driver(&serial_txx9_reg);
1284 if (ret)
1285 goto out;
1286
1287 serial_txx9_plat_devs = platform_device_alloc("serial_txx9", -1);
1288 if (!serial_txx9_plat_devs) {
1289 ret = -ENOMEM;
1290 goto unreg_uart_drv;
1291 }
1292
1293 ret = platform_device_add(serial_txx9_plat_devs);
1294 if (ret)
1295 goto put_dev;
1296
1297 serial_txx9_register_ports(&serial_txx9_reg,
1298 &serial_txx9_plat_devs->dev);
1299
1300 ret = platform_driver_register(&serial_txx9_plat_driver);
1301 if (ret)
1302 goto del_dev;
1303
1304#ifdef ENABLE_SERIAL_TXX9_PCI
1305 ret = pci_register_driver(&serial_txx9_pci_driver);
1306#endif
1307 if (ret == 0)
1308 goto out;
1309
1310 del_dev:
1311 platform_device_del(serial_txx9_plat_devs);
1312 put_dev:
1313 platform_device_put(serial_txx9_plat_devs);
1314 unreg_uart_drv:
1315 uart_unregister_driver(&serial_txx9_reg);
1316 out:
1317 return ret;
1318}
1319
1320static void __exit serial_txx9_exit(void)
1321{
1322 int i;
1323
1324#ifdef ENABLE_SERIAL_TXX9_PCI
1325 pci_unregister_driver(&serial_txx9_pci_driver);
1326#endif
1327 platform_driver_unregister(&serial_txx9_plat_driver);
1328 platform_device_unregister(serial_txx9_plat_devs);
1329 for (i = 0; i < UART_NR; i++) {
1330 struct uart_txx9_port *up = &serial_txx9_ports[i];
1331 if (up->port.iobase || up->port.mapbase)
1332 uart_remove_one_port(&serial_txx9_reg, &up->port);
1333 }
1334
1335 uart_unregister_driver(&serial_txx9_reg);
1336}
1337
1338module_init(serial_txx9_init);
1339module_exit(serial_txx9_exit);
1340
1341MODULE_LICENSE("GPL");
1342MODULE_DESCRIPTION("TX39/49 serial driver");
1343
1344MODULE_ALIAS_CHARDEV_MAJOR(TXX9_TTY_MAJOR);
1345
