1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19#ifndef __LINUX_EHCI_HCD_H
20#define __LINUX_EHCI_HCD_H
21
22
23
24
25
26
27
28
29
30
31
32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33typedef __u32 __bitwise __hc32;
34typedef __u16 __bitwise __hc16;
35#else
36#define __hc32 __le32
37#define __hc16 __le16
38#endif
39
40
41struct ehci_stats {
42
43 unsigned long normal;
44 unsigned long error;
45 unsigned long reclaim;
46 unsigned long lost_iaa;
47
48
49 unsigned long complete;
50 unsigned long unlink;
51};
52
53
54
55
56
57
58
59
60
61
62
63#define EHCI_MAX_ROOT_PORTS 15
64
65struct ehci_hcd {
66
67 struct ehci_caps __iomem *caps;
68 struct ehci_regs __iomem *regs;
69 struct ehci_dbg_port __iomem *debug;
70
71 __u32 hcs_params;
72 spinlock_t lock;
73
74
75 struct ehci_qh *async;
76 struct ehci_qh *dummy;
77 struct ehci_qh *reclaim;
78 unsigned scanning : 1;
79
80
81#define DEFAULT_I_TDPS 1024
82 unsigned periodic_size;
83 __hc32 *periodic;
84 dma_addr_t periodic_dma;
85 unsigned i_thresh;
86
87 union ehci_shadow *pshadow;
88 int next_uframe;
89 unsigned periodic_sched;
90
91
92 struct list_head cached_itd_list;
93 struct list_head cached_sitd_list;
94 unsigned clock_frame;
95
96
97 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
98
99
100 unsigned long bus_suspended;
101
102 unsigned long companion_ports;
103
104 unsigned long owned_ports;
105
106 unsigned long port_c_suspend;
107
108 unsigned long suspended_ports;
109
110
111
112 struct dma_pool *qh_pool;
113 struct dma_pool *qtd_pool;
114 struct dma_pool *itd_pool;
115 struct dma_pool *sitd_pool;
116
117 struct timer_list iaa_watchdog;
118 struct timer_list watchdog;
119 unsigned long actions;
120 unsigned stamp;
121 unsigned random_frame;
122 unsigned long next_statechange;
123 ktime_t last_periodic_enable;
124 u32 command;
125
126
127 unsigned no_selective_suspend:1;
128 unsigned has_fsl_port_bug:1;
129 unsigned big_endian_mmio:1;
130 unsigned big_endian_desc:1;
131 unsigned has_amcc_usb23:1;
132 unsigned need_io_watchdog:1;
133 unsigned broken_periodic:1;
134 unsigned amd_l1_fix:1;
135 unsigned fs_i_thresh:1;
136 unsigned use_dummy_qh:1;
137
138
139 #define OHCI_CTRL_HCFS (3 << 6)
140 #define OHCI_USB_OPER (2 << 6)
141 #define OHCI_USB_SUSPEND (3 << 6)
142
143 #define OHCI_HCCTRL_OFFSET 0x4
144 #define OHCI_HCCTRL_LEN 0x4
145 __hc32 *ohci_hcctrl_reg;
146 unsigned has_hostpc:1;
147 unsigned has_lpm:1;
148 unsigned has_ppcd:1;
149 u8 sbrn;
150
151
152#ifdef EHCI_STATS
153 struct ehci_stats stats;
154# define COUNT(x) do { (x)++; } while (0)
155#else
156# define COUNT(x) do {} while (0)
157#endif
158
159
160#ifdef DEBUG
161 struct dentry *debug_dir;
162#endif
163};
164
165
166static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
167{
168 return (struct ehci_hcd *) (hcd->hcd_priv);
169}
170static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
171{
172 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
173}
174
175
176static inline void
177iaa_watchdog_start(struct ehci_hcd *ehci)
178{
179 WARN_ON(timer_pending(&ehci->iaa_watchdog));
180 mod_timer(&ehci->iaa_watchdog,
181 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
182}
183
184static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
185{
186 del_timer(&ehci->iaa_watchdog);
187}
188
189enum ehci_timer_action {
190 TIMER_IO_WATCHDOG,
191 TIMER_ASYNC_SHRINK,
192 TIMER_ASYNC_OFF,
193};
194
195static inline void
196timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
197{
198 clear_bit (action, &ehci->actions);
199}
200
201static void free_cached_lists(struct ehci_hcd *ehci);
202
203
204
205#include <linux/usb/ehci_def.h>
206
207
208
209#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
210
211
212
213
214
215
216
217
218
219struct ehci_qtd {
220
221 __hc32 hw_next;
222 __hc32 hw_alt_next;
223 __hc32 hw_token;
224#define QTD_TOGGLE (1 << 31)
225#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
226#define QTD_IOC (1 << 15)
227#define QTD_CERR(tok) (((tok)>>10) & 0x3)
228#define QTD_PID(tok) (((tok)>>8) & 0x3)
229#define QTD_STS_ACTIVE (1 << 7)
230#define QTD_STS_HALT (1 << 6)
231#define QTD_STS_DBE (1 << 5)
232#define QTD_STS_BABBLE (1 << 4)
233#define QTD_STS_XACT (1 << 3)
234#define QTD_STS_MMF (1 << 2)
235#define QTD_STS_STS (1 << 1)
236#define QTD_STS_PING (1 << 0)
237
238#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
239#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
240#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
241
242 __hc32 hw_buf [5];
243 __hc32 hw_buf_hi [5];
244
245
246 dma_addr_t qtd_dma;
247 struct list_head qtd_list;
248 struct urb *urb;
249 size_t length;
250} __attribute__ ((aligned (32)));
251
252
253#define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
254
255#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
256
257
258
259
260#define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
261
262
263
264
265
266
267
268
269
270#define Q_TYPE_ITD (0 << 1)
271#define Q_TYPE_QH (1 << 1)
272#define Q_TYPE_SITD (2 << 1)
273#define Q_TYPE_FSTN (3 << 1)
274
275
276#define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
277
278
279#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1)
280
281
282
283
284
285
286
287
288
289union ehci_shadow {
290 struct ehci_qh *qh;
291 struct ehci_itd *itd;
292 struct ehci_sitd *sitd;
293 struct ehci_fstn *fstn;
294 __hc32 *hw_next;
295 void *ptr;
296};
297
298
299
300
301
302
303
304
305
306
307
308
309struct ehci_qh_hw {
310 __hc32 hw_next;
311 __hc32 hw_info1;
312#define QH_HEAD 0x00008000
313 __hc32 hw_info2;
314#define QH_SMASK 0x000000ff
315#define QH_CMASK 0x0000ff00
316#define QH_HUBADDR 0x007f0000
317#define QH_HUBPORT 0x3f800000
318#define QH_MULT 0xc0000000
319 __hc32 hw_current;
320
321
322 __hc32 hw_qtd_next;
323 __hc32 hw_alt_next;
324 __hc32 hw_token;
325 __hc32 hw_buf [5];
326 __hc32 hw_buf_hi [5];
327} __attribute__ ((aligned(32)));
328
329struct ehci_qh {
330 struct ehci_qh_hw *hw;
331
332 dma_addr_t qh_dma;
333 union ehci_shadow qh_next;
334 struct list_head qtd_list;
335 struct ehci_qtd *dummy;
336 struct ehci_qh *reclaim;
337
338 struct ehci_hcd *ehci;
339
340
341
342
343
344
345
346 u32 refcount;
347 unsigned stamp;
348
349 u8 needs_rescan;
350 u8 qh_state;
351#define QH_STATE_LINKED 1
352#define QH_STATE_UNLINK 2
353#define QH_STATE_IDLE 3
354#define QH_STATE_UNLINK_WAIT 4
355#define QH_STATE_COMPLETING 5
356
357 u8 xacterrs;
358#define QH_XACTERR_MAX 32
359
360
361 u8 usecs;
362 u8 gap_uf;
363 u8 c_usecs;
364 u16 tt_usecs;
365 unsigned short period;
366 unsigned short start;
367#define NO_FRAME ((unsigned short)~0)
368
369 struct usb_device *dev;
370 unsigned clearing_tt:1;
371};
372
373
374
375
376struct ehci_iso_packet {
377
378 u64 bufp;
379 __hc32 transaction;
380 u8 cross;
381
382 u32 buf1;
383};
384
385
386
387
388
389struct ehci_iso_sched {
390 struct list_head td_list;
391 unsigned span;
392 struct ehci_iso_packet packet [0];
393};
394
395
396
397
398
399struct ehci_iso_stream {
400
401 struct ehci_qh_hw *hw;
402
403 u32 refcount;
404 u8 bEndpointAddress;
405 u8 highspeed;
406 struct list_head td_list;
407 struct list_head free_list;
408 struct usb_device *udev;
409 struct usb_host_endpoint *ep;
410
411
412 int next_uframe;
413 __hc32 splits;
414
415
416
417
418
419 u8 usecs, c_usecs;
420 u16 interval;
421 u16 tt_usecs;
422 u16 maxp;
423 u16 raw_mask;
424 unsigned bandwidth;
425
426
427 __hc32 buf0;
428 __hc32 buf1;
429 __hc32 buf2;
430
431
432 __hc32 address;
433};
434
435
436
437
438
439
440
441
442
443struct ehci_itd {
444
445 __hc32 hw_next;
446 __hc32 hw_transaction [8];
447#define EHCI_ISOC_ACTIVE (1<<31)
448#define EHCI_ISOC_BUF_ERR (1<<30)
449#define EHCI_ISOC_BABBLE (1<<29)
450#define EHCI_ISOC_XACTERR (1<<28)
451#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
452#define EHCI_ITD_IOC (1 << 15)
453
454#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
455
456 __hc32 hw_bufp [7];
457 __hc32 hw_bufp_hi [7];
458
459
460 dma_addr_t itd_dma;
461 union ehci_shadow itd_next;
462
463 struct urb *urb;
464 struct ehci_iso_stream *stream;
465 struct list_head itd_list;
466
467
468 unsigned frame;
469 unsigned pg;
470 unsigned index[8];
471} __attribute__ ((aligned (32)));
472
473
474
475
476
477
478
479
480
481struct ehci_sitd {
482
483 __hc32 hw_next;
484
485 __hc32 hw_fullspeed_ep;
486 __hc32 hw_uframe;
487 __hc32 hw_results;
488#define SITD_IOC (1 << 31)
489#define SITD_PAGE (1 << 30)
490#define SITD_LENGTH(x) (0x3ff & ((x)>>16))
491#define SITD_STS_ACTIVE (1 << 7)
492#define SITD_STS_ERR (1 << 6)
493#define SITD_STS_DBE (1 << 5)
494#define SITD_STS_BABBLE (1 << 4)
495#define SITD_STS_XACT (1 << 3)
496#define SITD_STS_MMF (1 << 2)
497#define SITD_STS_STS (1 << 1)
498
499#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
500
501 __hc32 hw_buf [2];
502 __hc32 hw_backpointer;
503 __hc32 hw_buf_hi [2];
504
505
506 dma_addr_t sitd_dma;
507 union ehci_shadow sitd_next;
508
509 struct urb *urb;
510 struct ehci_iso_stream *stream;
511 struct list_head sitd_list;
512 unsigned frame;
513 unsigned index;
514} __attribute__ ((aligned (32)));
515
516
517
518
519
520
521
522
523
524
525
526
527struct ehci_fstn {
528 __hc32 hw_next;
529 __hc32 hw_prev;
530
531
532 dma_addr_t fstn_dma;
533 union ehci_shadow fstn_next;
534} __attribute__ ((aligned (32)));
535
536
537
538
539
540#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
541 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
542
543#define ehci_prepare_ports_for_controller_resume(ehci) \
544 ehci_adjust_port_wakeup_flags(ehci, false, false);
545
546
547
548#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
549
550
551
552
553
554
555
556
557#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
558
559
560static inline unsigned int
561ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
562{
563 if (ehci_is_TDI(ehci)) {
564 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
565 case 0:
566 return 0;
567 case 1:
568 return USB_PORT_STAT_LOW_SPEED;
569 case 2:
570 default:
571 return USB_PORT_STAT_HIGH_SPEED;
572 }
573 }
574 return USB_PORT_STAT_HIGH_SPEED;
575}
576
577#else
578
579#define ehci_is_TDI(e) (0)
580
581#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
582#endif
583
584
585
586#ifdef CONFIG_PPC_83xx
587
588
589
590#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
591#else
592#define ehci_has_fsl_portno_bug(e) (0)
593#endif
594
595
596
597
598
599
600
601
602
603
604
605#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
606#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
607#else
608#define ehci_big_endian_mmio(e) 0
609#endif
610
611
612
613
614
615#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
616#define readl_be(addr) __raw_readl((__force unsigned *)addr)
617#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
618#endif
619
620static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
621 __u32 __iomem * regs)
622{
623#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
624 return ehci_big_endian_mmio(ehci) ?
625 readl_be(regs) :
626 readl(regs);
627#else
628 return readl(regs);
629#endif
630}
631
632static inline void ehci_writel(const struct ehci_hcd *ehci,
633 const unsigned int val, __u32 __iomem *regs)
634{
635#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
636 ehci_big_endian_mmio(ehci) ?
637 writel_be(val, regs) :
638 writel(val, regs);
639#else
640 writel(val, regs);
641#endif
642}
643
644
645
646
647
648
649#ifdef CONFIG_44x
650static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
651{
652 u32 hc_control;
653
654 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
655 if (operational)
656 hc_control |= OHCI_USB_OPER;
657 else
658 hc_control |= OHCI_USB_SUSPEND;
659
660 writel_be(hc_control, ehci->ohci_hcctrl_reg);
661 (void) readl_be(ehci->ohci_hcctrl_reg);
662}
663#else
664static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
665{ }
666#endif
667
668
669
670
671
672
673
674
675
676
677#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
678#define ehci_big_endian_desc(e) ((e)->big_endian_desc)
679
680
681static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
682{
683 return ehci_big_endian_desc(ehci)
684 ? (__force __hc32)cpu_to_be32(x)
685 : (__force __hc32)cpu_to_le32(x);
686}
687
688
689static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
690{
691 return ehci_big_endian_desc(ehci)
692 ? be32_to_cpu((__force __be32)x)
693 : le32_to_cpu((__force __le32)x);
694}
695
696static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
697{
698 return ehci_big_endian_desc(ehci)
699 ? be32_to_cpup((__force __be32 *)x)
700 : le32_to_cpup((__force __le32 *)x);
701}
702
703#else
704
705
706static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
707{
708 return cpu_to_le32(x);
709}
710
711
712static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
713{
714 return le32_to_cpu(x);
715}
716
717static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
718{
719 return le32_to_cpup(x);
720}
721
722#endif
723
724
725
726#ifndef DEBUG
727#define STUB_DEBUG_FILES
728#endif
729
730
731
732#endif
733