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67#include <linux/scatterlist.h>
68#include <linux/slab.h>
69#include "xhci.h"
70
71static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
74
75
76
77
78
79dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
80 union xhci_trb *trb)
81{
82 unsigned long segment_offset;
83
84 if (!seg || !trb || trb < seg->trbs)
85 return 0;
86
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
89 return 0;
90 return seg->dma + (segment_offset * sizeof(*trb));
91}
92
93
94
95
96static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
98{
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
102 else
103 return trb->link.control & LINK_TOGGLE;
104}
105
106
107
108
109
110static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
112{
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
115 else
116 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
117}
118
119static inline int enqueue_is_link_trb(struct xhci_ring *ring)
120{
121 struct xhci_link_trb *link = &ring->enqueue->link;
122 return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK));
123}
124
125
126
127
128
129static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
133{
134 if (last_trb(xhci, ring, *seg, *trb)) {
135 *seg = (*seg)->next;
136 *trb = ((*seg)->trbs);
137 } else {
138 (*trb)++;
139 }
140}
141
142
143
144
145
146static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
147{
148 union xhci_trb *next = ++(ring->dequeue);
149 unsigned long long addr;
150
151 ring->deq_updates++;
152
153
154
155 while (last_trb(xhci, ring, ring->deq_seg, next)) {
156 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
157 ring->cycle_state = (ring->cycle_state ? 0 : 1);
158 if (!in_interrupt())
159 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
160 ring,
161 (unsigned int) ring->cycle_state);
162 }
163 ring->deq_seg = ring->deq_seg->next;
164 ring->dequeue = ring->deq_seg->trbs;
165 next = ring->dequeue;
166 }
167 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
168 if (ring == xhci->event_ring)
169 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
170 else if (ring == xhci->cmd_ring)
171 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
172 else
173 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
174}
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
194 bool consumer, bool more_trbs_coming)
195{
196 u32 chain;
197 union xhci_trb *next;
198 unsigned long long addr;
199
200 chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
201 next = ++(ring->enqueue);
202
203 ring->enq_updates++;
204
205
206
207 while (last_trb(xhci, ring, ring->enq_seg, next)) {
208 if (!consumer) {
209 if (ring != xhci->event_ring) {
210
211
212
213
214
215
216
217
218 if (!chain && !more_trbs_coming)
219 break;
220
221
222
223
224
225 if (!xhci_link_trb_quirk(xhci)) {
226 next->link.control &= ~TRB_CHAIN;
227 next->link.control |= chain;
228 }
229
230 wmb();
231 next->link.control ^= TRB_CYCLE;
232 }
233
234 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
235 ring->cycle_state = (ring->cycle_state ? 0 : 1);
236 if (!in_interrupt())
237 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
238 ring,
239 (unsigned int) ring->cycle_state);
240 }
241 }
242 ring->enq_seg = ring->enq_seg->next;
243 ring->enqueue = ring->enq_seg->trbs;
244 next = ring->enqueue;
245 }
246 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
247 if (ring == xhci->event_ring)
248 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
249 else if (ring == xhci->cmd_ring)
250 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
251 else
252 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
253}
254
255
256
257
258
259
260
261static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
262 unsigned int num_trbs)
263{
264 int i;
265 union xhci_trb *enq = ring->enqueue;
266 struct xhci_segment *enq_seg = ring->enq_seg;
267 struct xhci_segment *cur_seg;
268 unsigned int left_on_ring;
269
270
271
272 while (last_trb(xhci, ring, enq_seg, enq)) {
273 enq_seg = enq_seg->next;
274 enq = enq_seg->trbs;
275 }
276
277
278 if (enq == ring->dequeue) {
279
280 left_on_ring = TRBS_PER_SEGMENT - 1;
281 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
282 cur_seg = cur_seg->next)
283 left_on_ring += TRBS_PER_SEGMENT - 1;
284
285
286 left_on_ring -= 1;
287 if (num_trbs > left_on_ring) {
288 xhci_warn(xhci, "Not enough room on ring; "
289 "need %u TRBs, %u TRBs left\n",
290 num_trbs, left_on_ring);
291 return 0;
292 }
293 return 1;
294 }
295
296 for (i = 0; i <= num_trbs; ++i) {
297 if (enq == ring->dequeue)
298 return 0;
299 enq++;
300 while (last_trb(xhci, ring, enq_seg, enq)) {
301 enq_seg = enq_seg->next;
302 enq = enq_seg->trbs;
303 }
304 }
305 return 1;
306}
307
308
309void xhci_ring_cmd_db(struct xhci_hcd *xhci)
310{
311 xhci_dbg(xhci, "// Ding dong!\n");
312 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
313
314 xhci_readl(xhci, &xhci->dba->doorbell[0]);
315}
316
317void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
318 unsigned int slot_id,
319 unsigned int ep_index,
320 unsigned int stream_id)
321{
322 __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
323 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
324 unsigned int ep_state = ep->ep_state;
325
326
327
328
329
330
331
332
333 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
334 (ep_state & EP_HALTED))
335 return;
336 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
337
338
339
340}
341
342
343static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
344 unsigned int slot_id,
345 unsigned int ep_index)
346{
347 unsigned int stream_id;
348 struct xhci_virt_ep *ep;
349
350 ep = &xhci->devs[slot_id]->eps[ep_index];
351
352
353 if (!(ep->ep_state & EP_HAS_STREAMS)) {
354 if (!(list_empty(&ep->ring->td_list)))
355 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
356 return;
357 }
358
359 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
360 stream_id++) {
361 struct xhci_stream_info *stream_info = ep->stream_info;
362 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
363 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
364 stream_id);
365 }
366}
367
368
369
370
371
372
373static struct xhci_segment *find_trb_seg(
374 struct xhci_segment *start_seg,
375 union xhci_trb *trb, int *cycle_state)
376{
377 struct xhci_segment *cur_seg = start_seg;
378 struct xhci_generic_trb *generic_trb;
379
380 while (cur_seg->trbs > trb ||
381 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
382 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
383 if ((generic_trb->field[3] & TRB_TYPE_BITMASK) ==
384 TRB_TYPE(TRB_LINK) &&
385 (generic_trb->field[3] & LINK_TOGGLE))
386 *cycle_state = ~(*cycle_state) & 0x1;
387 cur_seg = cur_seg->next;
388 if (cur_seg == start_seg)
389
390 return NULL;
391 }
392 return cur_seg;
393}
394
395
396static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
397 unsigned int slot_id, unsigned int ep_index,
398 unsigned int stream_id)
399{
400 struct xhci_virt_ep *ep;
401
402 ep = &xhci->devs[slot_id]->eps[ep_index];
403
404 if (!(ep->ep_state & EP_HAS_STREAMS))
405 return ep->ring;
406
407 if (stream_id == 0) {
408 xhci_warn(xhci,
409 "WARN: Slot ID %u, ep index %u has streams, "
410 "but URB has no stream ID.\n",
411 slot_id, ep_index);
412 return NULL;
413 }
414
415 if (stream_id < ep->stream_info->num_streams)
416 return ep->stream_info->stream_rings[stream_id];
417
418 xhci_warn(xhci,
419 "WARN: Slot ID %u, ep index %u has "
420 "stream IDs 1 to %u allocated, "
421 "but stream ID %u is requested.\n",
422 slot_id, ep_index,
423 ep->stream_info->num_streams - 1,
424 stream_id);
425 return NULL;
426}
427
428
429
430
431
432static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
433 struct urb *urb)
434{
435 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
436 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
437}
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
454 unsigned int slot_id, unsigned int ep_index,
455 unsigned int stream_id, struct xhci_td *cur_td,
456 struct xhci_dequeue_state *state)
457{
458 struct xhci_virt_device *dev = xhci->devs[slot_id];
459 struct xhci_ring *ep_ring;
460 struct xhci_generic_trb *trb;
461 struct xhci_ep_ctx *ep_ctx;
462 dma_addr_t addr;
463
464 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
465 ep_index, stream_id);
466 if (!ep_ring) {
467 xhci_warn(xhci, "WARN can't find new dequeue state "
468 "for invalid stream ID %u.\n",
469 stream_id);
470 return;
471 }
472 state->new_cycle_state = 0;
473 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
474 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
475 dev->eps[ep_index].stopped_trb,
476 &state->new_cycle_state);
477 if (!state->new_deq_seg) {
478 WARN_ON(1);
479 return;
480 }
481
482
483 xhci_dbg(xhci, "Finding endpoint context\n");
484 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
485 state->new_cycle_state = 0x1 & ep_ctx->deq;
486
487 state->new_deq_ptr = cur_td->last_trb;
488 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
489 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
490 state->new_deq_ptr,
491 &state->new_cycle_state);
492 if (!state->new_deq_seg) {
493 WARN_ON(1);
494 return;
495 }
496
497 trb = &state->new_deq_ptr->generic;
498 if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
499 (trb->field[3] & LINK_TOGGLE))
500 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
501 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
502
503
504 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
505 state->new_deq_seg);
506 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
507 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
508 (unsigned long long) addr);
509 xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
510 ep_ring->dequeue = state->new_deq_ptr;
511 ep_ring->deq_seg = state->new_deq_seg;
512}
513
514static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
515 struct xhci_td *cur_td)
516{
517 struct xhci_segment *cur_seg;
518 union xhci_trb *cur_trb;
519
520 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
521 true;
522 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
523 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
524 TRB_TYPE(TRB_LINK)) {
525
526
527
528 cur_trb->generic.field[3] &= ~TRB_CHAIN;
529 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
530 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
531 "in seg %p (0x%llx dma)\n",
532 cur_trb,
533 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
534 cur_seg,
535 (unsigned long long)cur_seg->dma);
536 } else {
537 cur_trb->generic.field[0] = 0;
538 cur_trb->generic.field[1] = 0;
539 cur_trb->generic.field[2] = 0;
540
541 cur_trb->generic.field[3] &= TRB_CYCLE;
542 cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
543 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
544 "in seg %p (0x%llx dma)\n",
545 cur_trb,
546 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
547 cur_seg,
548 (unsigned long long)cur_seg->dma);
549 }
550 if (cur_trb == cur_td->last_trb)
551 break;
552 }
553}
554
555static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
556 unsigned int ep_index, unsigned int stream_id,
557 struct xhci_segment *deq_seg,
558 union xhci_trb *deq_ptr, u32 cycle_state);
559
560void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
561 unsigned int slot_id, unsigned int ep_index,
562 unsigned int stream_id,
563 struct xhci_dequeue_state *deq_state)
564{
565 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
566
567 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
568 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
569 deq_state->new_deq_seg,
570 (unsigned long long)deq_state->new_deq_seg->dma,
571 deq_state->new_deq_ptr,
572 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
573 deq_state->new_cycle_state);
574 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
575 deq_state->new_deq_seg,
576 deq_state->new_deq_ptr,
577 (u32) deq_state->new_cycle_state);
578
579
580
581
582
583 ep->ep_state |= SET_DEQ_PENDING;
584}
585
586static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
587 struct xhci_virt_ep *ep)
588{
589 ep->ep_state &= ~EP_HALT_PENDING;
590
591
592
593
594 if (del_timer(&ep->stop_cmd_timer))
595 ep->stop_cmds_pending--;
596}
597
598
599static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
600 struct xhci_td *cur_td, int status, char *adjective)
601{
602 struct usb_hcd *hcd = xhci_to_hcd(xhci);
603 struct urb *urb;
604 struct urb_priv *urb_priv;
605
606 urb = cur_td->urb;
607 urb_priv = urb->hcpriv;
608 urb_priv->td_cnt++;
609
610
611 if (urb_priv->td_cnt == urb_priv->length) {
612 usb_hcd_unlink_urb_from_ep(hcd, urb);
613 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb);
614
615 spin_unlock(&xhci->lock);
616 usb_hcd_giveback_urb(hcd, urb, status);
617 xhci_urb_free_priv(xhci, urb_priv);
618 spin_lock(&xhci->lock);
619 xhci_dbg(xhci, "%s URB given back\n", adjective);
620 }
621}
622
623
624
625
626
627
628
629
630
631
632
633static void handle_stopped_endpoint(struct xhci_hcd *xhci,
634 union xhci_trb *trb, struct xhci_event_cmd *event)
635{
636 unsigned int slot_id;
637 unsigned int ep_index;
638 struct xhci_virt_device *virt_dev;
639 struct xhci_ring *ep_ring;
640 struct xhci_virt_ep *ep;
641 struct list_head *entry;
642 struct xhci_td *cur_td = NULL;
643 struct xhci_td *last_unlinked_td;
644
645 struct xhci_dequeue_state deq_state;
646
647 if (unlikely(TRB_TO_SUSPEND_PORT(
648 xhci->cmd_ring->dequeue->generic.field[3]))) {
649 slot_id = TRB_TO_SLOT_ID(
650 xhci->cmd_ring->dequeue->generic.field[3]);
651 virt_dev = xhci->devs[slot_id];
652 if (virt_dev)
653 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
654 event);
655 else
656 xhci_warn(xhci, "Stop endpoint command "
657 "completion for disabled slot %u\n",
658 slot_id);
659 return;
660 }
661
662 memset(&deq_state, 0, sizeof(deq_state));
663 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
664 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
665 ep = &xhci->devs[slot_id]->eps[ep_index];
666
667 if (list_empty(&ep->cancelled_td_list)) {
668 xhci_stop_watchdog_timer_in_irq(xhci, ep);
669 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
670 return;
671 }
672
673
674
675
676
677
678 list_for_each(entry, &ep->cancelled_td_list) {
679 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
680 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
681 cur_td->first_trb,
682 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
683 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
684 if (!ep_ring) {
685
686
687
688
689
690
691
692
693
694
695
696 xhci_warn(xhci, "WARN Cancelled URB %p "
697 "has invalid stream ID %u.\n",
698 cur_td->urb,
699 cur_td->urb->stream_id);
700 goto remove_finished_td;
701 }
702
703
704
705
706 if (cur_td == ep->stopped_td)
707 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
708 cur_td->urb->stream_id,
709 cur_td, &deq_state);
710 else
711 td_to_noop(xhci, ep_ring, cur_td);
712remove_finished_td:
713
714
715
716
717
718 list_del(&cur_td->td_list);
719 }
720 last_unlinked_td = cur_td;
721 xhci_stop_watchdog_timer_in_irq(xhci, ep);
722
723
724 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
725 xhci_queue_new_dequeue_state(xhci,
726 slot_id, ep_index,
727 ep->stopped_td->urb->stream_id,
728 &deq_state);
729 xhci_ring_cmd_db(xhci);
730 } else {
731
732 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
733 }
734 ep->stopped_td = NULL;
735 ep->stopped_trb = NULL;
736
737
738
739
740
741
742
743 do {
744 cur_td = list_entry(ep->cancelled_td_list.next,
745 struct xhci_td, cancelled_td_list);
746 list_del(&cur_td->cancelled_td_list);
747
748
749
750
751
752 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
753
754
755
756
757 if (xhci->xhc_state & XHCI_STATE_DYING)
758 return;
759 } while (cur_td != last_unlinked_td);
760
761
762}
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783void xhci_stop_endpoint_command_watchdog(unsigned long arg)
784{
785 struct xhci_hcd *xhci;
786 struct xhci_virt_ep *ep;
787 struct xhci_virt_ep *temp_ep;
788 struct xhci_ring *ring;
789 struct xhci_td *cur_td;
790 int ret, i, j;
791
792 ep = (struct xhci_virt_ep *) arg;
793 xhci = ep->xhci;
794
795 spin_lock(&xhci->lock);
796
797 ep->stop_cmds_pending--;
798 if (xhci->xhc_state & XHCI_STATE_DYING) {
799 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
800 "xHCI as DYING, exiting.\n");
801 spin_unlock(&xhci->lock);
802 return;
803 }
804 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
805 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
806 "exiting.\n");
807 spin_unlock(&xhci->lock);
808 return;
809 }
810
811 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
812 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
813
814
815
816 xhci->xhc_state |= XHCI_STATE_DYING;
817
818 xhci_quiesce(xhci);
819 spin_unlock(&xhci->lock);
820
821 ret = xhci_halt(xhci);
822
823 spin_lock(&xhci->lock);
824 if (ret < 0) {
825
826
827
828
829
830
831
832
833 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
834 xhci_warn(xhci, "Completing active URBs anyway.\n");
835
836
837
838
839
840 }
841 for (i = 0; i < MAX_HC_SLOTS; i++) {
842 if (!xhci->devs[i])
843 continue;
844 for (j = 0; j < 31; j++) {
845 temp_ep = &xhci->devs[i]->eps[j];
846 ring = temp_ep->ring;
847 if (!ring)
848 continue;
849 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
850 "ep index %u\n", i, j);
851 while (!list_empty(&ring->td_list)) {
852 cur_td = list_first_entry(&ring->td_list,
853 struct xhci_td,
854 td_list);
855 list_del(&cur_td->td_list);
856 if (!list_empty(&cur_td->cancelled_td_list))
857 list_del(&cur_td->cancelled_td_list);
858 xhci_giveback_urb_in_irq(xhci, cur_td,
859 -ESHUTDOWN, "killed");
860 }
861 while (!list_empty(&temp_ep->cancelled_td_list)) {
862 cur_td = list_first_entry(
863 &temp_ep->cancelled_td_list,
864 struct xhci_td,
865 cancelled_td_list);
866 list_del(&cur_td->cancelled_td_list);
867 xhci_giveback_urb_in_irq(xhci, cur_td,
868 -ESHUTDOWN, "killed");
869 }
870 }
871 }
872 spin_unlock(&xhci->lock);
873 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
874 xhci_dbg(xhci, "Calling usb_hc_died()\n");
875 usb_hc_died(xhci_to_hcd(xhci));
876 xhci_dbg(xhci, "xHCI host controller is dead.\n");
877}
878
879
880
881
882
883
884
885
886static void handle_set_deq_completion(struct xhci_hcd *xhci,
887 struct xhci_event_cmd *event,
888 union xhci_trb *trb)
889{
890 unsigned int slot_id;
891 unsigned int ep_index;
892 unsigned int stream_id;
893 struct xhci_ring *ep_ring;
894 struct xhci_virt_device *dev;
895 struct xhci_ep_ctx *ep_ctx;
896 struct xhci_slot_ctx *slot_ctx;
897
898 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
899 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
900 stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]);
901 dev = xhci->devs[slot_id];
902
903 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
904 if (!ep_ring) {
905 xhci_warn(xhci, "WARN Set TR deq ptr command for "
906 "freed stream ID %u\n",
907 stream_id);
908
909 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
910 return;
911 }
912
913 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
914 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
915
916 if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
917 unsigned int ep_state;
918 unsigned int slot_state;
919
920 switch (GET_COMP_CODE(event->status)) {
921 case COMP_TRB_ERR:
922 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
923 "of stream ID configuration\n");
924 break;
925 case COMP_CTX_STATE:
926 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
927 "to incorrect slot or ep state.\n");
928 ep_state = ep_ctx->ep_info;
929 ep_state &= EP_STATE_MASK;
930 slot_state = slot_ctx->dev_state;
931 slot_state = GET_SLOT_STATE(slot_state);
932 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
933 slot_state, ep_state);
934 break;
935 case COMP_EBADSLT:
936 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
937 "slot %u was not enabled.\n", slot_id);
938 break;
939 default:
940 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
941 "completion code of %u.\n",
942 GET_COMP_CODE(event->status));
943 break;
944 }
945
946
947
948
949
950
951 } else {
952 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
953 ep_ctx->deq);
954 }
955
956 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
957
958 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
959}
960
961static void handle_reset_ep_completion(struct xhci_hcd *xhci,
962 struct xhci_event_cmd *event,
963 union xhci_trb *trb)
964{
965 int slot_id;
966 unsigned int ep_index;
967
968 slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
969 ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
970
971
972
973 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
974 (unsigned int) GET_COMP_CODE(event->status));
975
976
977
978
979
980 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
981 xhci_dbg(xhci, "Queueing configure endpoint command\n");
982 xhci_queue_configure_endpoint(xhci,
983 xhci->devs[slot_id]->in_ctx->dma, slot_id,
984 false);
985 xhci_ring_cmd_db(xhci);
986 } else {
987
988 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
989 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
990 }
991}
992
993
994
995
996
997static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
998 struct xhci_virt_device *virt_dev,
999 struct xhci_event_cmd *event)
1000{
1001 struct xhci_command *command;
1002
1003 if (list_empty(&virt_dev->cmd_list))
1004 return 0;
1005
1006 command = list_entry(virt_dev->cmd_list.next,
1007 struct xhci_command, cmd_list);
1008 if (xhci->cmd_ring->dequeue != command->command_trb)
1009 return 0;
1010
1011 command->status =
1012 GET_COMP_CODE(event->status);
1013 list_del(&command->cmd_list);
1014 if (command->completion)
1015 complete(command->completion);
1016 else
1017 xhci_free_command(xhci, command);
1018 return 1;
1019}
1020
1021static void handle_cmd_completion(struct xhci_hcd *xhci,
1022 struct xhci_event_cmd *event)
1023{
1024 int slot_id = TRB_TO_SLOT_ID(event->flags);
1025 u64 cmd_dma;
1026 dma_addr_t cmd_dequeue_dma;
1027 struct xhci_input_control_ctx *ctrl_ctx;
1028 struct xhci_virt_device *virt_dev;
1029 unsigned int ep_index;
1030 struct xhci_ring *ep_ring;
1031 unsigned int ep_state;
1032
1033 cmd_dma = event->cmd_trb;
1034 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1035 xhci->cmd_ring->dequeue);
1036
1037 if (cmd_dequeue_dma == 0) {
1038 xhci->error_bitmask |= 1 << 4;
1039 return;
1040 }
1041
1042 if (cmd_dma != (u64) cmd_dequeue_dma) {
1043 xhci->error_bitmask |= 1 << 5;
1044 return;
1045 }
1046 switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
1047 case TRB_TYPE(TRB_ENABLE_SLOT):
1048 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
1049 xhci->slot_id = slot_id;
1050 else
1051 xhci->slot_id = 0;
1052 complete(&xhci->addr_dev);
1053 break;
1054 case TRB_TYPE(TRB_DISABLE_SLOT):
1055 if (xhci->devs[slot_id])
1056 xhci_free_virt_device(xhci, slot_id);
1057 break;
1058 case TRB_TYPE(TRB_CONFIG_EP):
1059 virt_dev = xhci->devs[slot_id];
1060 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1061 break;
1062
1063
1064
1065
1066
1067
1068
1069
1070 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1071 virt_dev->in_ctx);
1072
1073 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
1074
1075
1076
1077
1078
1079
1080 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1081 ep_index != (unsigned int) -1 &&
1082 ctrl_ctx->add_flags - SLOT_FLAG ==
1083 ctrl_ctx->drop_flags) {
1084 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1085 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1086 if (!(ep_state & EP_HALTED))
1087 goto bandwidth_change;
1088 xhci_dbg(xhci, "Completed config ep cmd - "
1089 "last ep index = %d, state = %d\n",
1090 ep_index, ep_state);
1091
1092 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1093 ~EP_HALTED;
1094 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1095 break;
1096 }
1097bandwidth_change:
1098 xhci_dbg(xhci, "Completed config ep cmd\n");
1099 xhci->devs[slot_id]->cmd_status =
1100 GET_COMP_CODE(event->status);
1101 complete(&xhci->devs[slot_id]->cmd_completion);
1102 break;
1103 case TRB_TYPE(TRB_EVAL_CONTEXT):
1104 virt_dev = xhci->devs[slot_id];
1105 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1106 break;
1107 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1108 complete(&xhci->devs[slot_id]->cmd_completion);
1109 break;
1110 case TRB_TYPE(TRB_ADDR_DEV):
1111 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1112 complete(&xhci->addr_dev);
1113 break;
1114 case TRB_TYPE(TRB_STOP_RING):
1115 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1116 break;
1117 case TRB_TYPE(TRB_SET_DEQ):
1118 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1119 break;
1120 case TRB_TYPE(TRB_CMD_NOOP):
1121 ++xhci->noops_handled;
1122 break;
1123 case TRB_TYPE(TRB_RESET_EP):
1124 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1125 break;
1126 case TRB_TYPE(TRB_RESET_DEV):
1127 xhci_dbg(xhci, "Completed reset device command.\n");
1128 slot_id = TRB_TO_SLOT_ID(
1129 xhci->cmd_ring->dequeue->generic.field[3]);
1130 virt_dev = xhci->devs[slot_id];
1131 if (virt_dev)
1132 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1133 else
1134 xhci_warn(xhci, "Reset device command completion "
1135 "for disabled slot %u\n", slot_id);
1136 break;
1137 case TRB_TYPE(TRB_NEC_GET_FW):
1138 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1139 xhci->error_bitmask |= 1 << 6;
1140 break;
1141 }
1142 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1143 NEC_FW_MAJOR(event->status),
1144 NEC_FW_MINOR(event->status));
1145 break;
1146 default:
1147
1148 xhci->error_bitmask |= 1 << 6;
1149 break;
1150 }
1151 inc_deq(xhci, xhci->cmd_ring, false);
1152}
1153
1154static void handle_vendor_event(struct xhci_hcd *xhci,
1155 union xhci_trb *event)
1156{
1157 u32 trb_type;
1158
1159 trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]);
1160 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1161 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1162 handle_cmd_completion(xhci, &event->event_cmd);
1163}
1164
1165static void handle_port_status(struct xhci_hcd *xhci,
1166 union xhci_trb *event)
1167{
1168 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1169 u32 port_id;
1170 u32 temp, temp1;
1171 u32 __iomem *addr;
1172 int ports;
1173 int slot_id;
1174
1175
1176 if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1177 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1178 xhci->error_bitmask |= 1 << 8;
1179 }
1180 port_id = GET_PORT_ID(event->generic.field[0]);
1181 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1182
1183 ports = HCS_MAX_PORTS(xhci->hcs_params1);
1184 if ((port_id <= 0) || (port_id > ports)) {
1185 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1186 goto cleanup;
1187 }
1188
1189 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS * (port_id - 1);
1190 temp = xhci_readl(xhci, addr);
1191 if (hcd->state == HC_STATE_SUSPENDED) {
1192 xhci_dbg(xhci, "resume root hub\n");
1193 usb_hcd_resume_root_hub(hcd);
1194 }
1195
1196 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1197 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1198
1199 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1200 if (!(temp1 & CMD_RUN)) {
1201 xhci_warn(xhci, "xHC is not running.\n");
1202 goto cleanup;
1203 }
1204
1205 if (DEV_SUPERSPEED(temp)) {
1206 xhci_dbg(xhci, "resume SS port %d\n", port_id);
1207 temp = xhci_port_state_to_neutral(temp);
1208 temp &= ~PORT_PLS_MASK;
1209 temp |= PORT_LINK_STROBE | XDEV_U0;
1210 xhci_writel(xhci, temp, addr);
1211 slot_id = xhci_find_slot_id_by_port(xhci, port_id);
1212 if (!slot_id) {
1213 xhci_dbg(xhci, "slot_id is zero\n");
1214 goto cleanup;
1215 }
1216 xhci_ring_device(xhci, slot_id);
1217 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1218
1219 temp = xhci_readl(xhci, addr);
1220 temp = xhci_port_state_to_neutral(temp);
1221 temp |= PORT_PLC;
1222 xhci_writel(xhci, temp, addr);
1223 } else {
1224 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1225 xhci->resume_done[port_id - 1] = jiffies +
1226 msecs_to_jiffies(20);
1227 mod_timer(&hcd->rh_timer,
1228 xhci->resume_done[port_id - 1]);
1229
1230 }
1231 }
1232
1233cleanup:
1234
1235 inc_deq(xhci, xhci->event_ring, true);
1236
1237 spin_unlock(&xhci->lock);
1238
1239 usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
1240 spin_lock(&xhci->lock);
1241}
1242
1243
1244
1245
1246
1247
1248
1249struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1250 union xhci_trb *start_trb,
1251 union xhci_trb *end_trb,
1252 dma_addr_t suspect_dma)
1253{
1254 dma_addr_t start_dma;
1255 dma_addr_t end_seg_dma;
1256 dma_addr_t end_trb_dma;
1257 struct xhci_segment *cur_seg;
1258
1259 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1260 cur_seg = start_seg;
1261
1262 do {
1263 if (start_dma == 0)
1264 return NULL;
1265
1266 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1267 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1268
1269 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1270
1271 if (end_trb_dma > 0) {
1272
1273 if (start_dma <= end_trb_dma) {
1274 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1275 return cur_seg;
1276 } else {
1277
1278
1279
1280 if ((suspect_dma >= start_dma &&
1281 suspect_dma <= end_seg_dma) ||
1282 (suspect_dma >= cur_seg->dma &&
1283 suspect_dma <= end_trb_dma))
1284 return cur_seg;
1285 }
1286 return NULL;
1287 } else {
1288
1289 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1290 return cur_seg;
1291 }
1292 cur_seg = cur_seg->next;
1293 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1294 } while (cur_seg != start_seg);
1295
1296 return NULL;
1297}
1298
1299static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1300 unsigned int slot_id, unsigned int ep_index,
1301 unsigned int stream_id,
1302 struct xhci_td *td, union xhci_trb *event_trb)
1303{
1304 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1305 ep->ep_state |= EP_HALTED;
1306 ep->stopped_td = td;
1307 ep->stopped_trb = event_trb;
1308 ep->stopped_stream = stream_id;
1309
1310 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1311 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1312
1313 ep->stopped_td = NULL;
1314 ep->stopped_trb = NULL;
1315 ep->stopped_stream = 0;
1316
1317 xhci_ring_cmd_db(xhci);
1318}
1319
1320
1321
1322
1323
1324
1325
1326static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1327 struct xhci_ep_ctx *ep_ctx,
1328 unsigned int trb_comp_code)
1329{
1330
1331 if (trb_comp_code == COMP_TX_ERR ||
1332 trb_comp_code == COMP_BABBLE ||
1333 trb_comp_code == COMP_SPLIT_ERR)
1334
1335
1336
1337
1338
1339
1340 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1341 return 1;
1342
1343 return 0;
1344}
1345
1346int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1347{
1348 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1349
1350
1351
1352 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1353 trb_comp_code);
1354 xhci_dbg(xhci, "Treating code as success.\n");
1355 return 1;
1356 }
1357 return 0;
1358}
1359
1360
1361
1362
1363
1364static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1365 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1366 struct xhci_virt_ep *ep, int *status, bool skip)
1367{
1368 struct xhci_virt_device *xdev;
1369 struct xhci_ring *ep_ring;
1370 unsigned int slot_id;
1371 int ep_index;
1372 struct urb *urb = NULL;
1373 struct xhci_ep_ctx *ep_ctx;
1374 int ret = 0;
1375 struct urb_priv *urb_priv;
1376 u32 trb_comp_code;
1377
1378 slot_id = TRB_TO_SLOT_ID(event->flags);
1379 xdev = xhci->devs[slot_id];
1380 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1381 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1382 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1383 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1384
1385 if (skip)
1386 goto td_cleanup;
1387
1388 if (trb_comp_code == COMP_STOP_INVAL ||
1389 trb_comp_code == COMP_STOP) {
1390
1391
1392
1393
1394 ep->stopped_td = td;
1395 ep->stopped_trb = event_trb;
1396 return 0;
1397 } else {
1398 if (trb_comp_code == COMP_STALL) {
1399
1400
1401
1402
1403
1404
1405
1406 ep->stopped_td = td;
1407 ep->stopped_trb = event_trb;
1408 ep->stopped_stream = ep_ring->stream_id;
1409 } else if (xhci_requires_manual_halt_cleanup(xhci,
1410 ep_ctx, trb_comp_code)) {
1411
1412
1413
1414
1415
1416 xhci_cleanup_halted_endpoint(xhci,
1417 slot_id, ep_index, ep_ring->stream_id,
1418 td, event_trb);
1419 } else {
1420
1421 while (ep_ring->dequeue != td->last_trb)
1422 inc_deq(xhci, ep_ring, false);
1423 inc_deq(xhci, ep_ring, false);
1424 }
1425
1426td_cleanup:
1427
1428 urb = td->urb;
1429 urb_priv = urb->hcpriv;
1430
1431
1432
1433
1434
1435
1436
1437 if (urb->actual_length > urb->transfer_buffer_length) {
1438 xhci_warn(xhci, "URB transfer length is wrong, "
1439 "xHC issue? req. len = %u, "
1440 "act. len = %u\n",
1441 urb->transfer_buffer_length,
1442 urb->actual_length);
1443 urb->actual_length = 0;
1444 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1445 *status = -EREMOTEIO;
1446 else
1447 *status = 0;
1448 }
1449 list_del(&td->td_list);
1450
1451 if (!list_empty(&td->cancelled_td_list))
1452 list_del(&td->cancelled_td_list);
1453
1454 urb_priv->td_cnt++;
1455
1456 if (urb_priv->td_cnt == urb_priv->length)
1457 ret = 1;
1458 }
1459
1460 return ret;
1461}
1462
1463
1464
1465
1466static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1467 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1468 struct xhci_virt_ep *ep, int *status)
1469{
1470 struct xhci_virt_device *xdev;
1471 struct xhci_ring *ep_ring;
1472 unsigned int slot_id;
1473 int ep_index;
1474 struct xhci_ep_ctx *ep_ctx;
1475 u32 trb_comp_code;
1476
1477 slot_id = TRB_TO_SLOT_ID(event->flags);
1478 xdev = xhci->devs[slot_id];
1479 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1480 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1481 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1482 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1483
1484 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1485 switch (trb_comp_code) {
1486 case COMP_SUCCESS:
1487 if (event_trb == ep_ring->dequeue) {
1488 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1489 "without IOC set??\n");
1490 *status = -ESHUTDOWN;
1491 } else if (event_trb != td->last_trb) {
1492 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1493 "without IOC set??\n");
1494 *status = -ESHUTDOWN;
1495 } else {
1496 xhci_dbg(xhci, "Successful control transfer!\n");
1497 *status = 0;
1498 }
1499 break;
1500 case COMP_SHORT_TX:
1501 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1502 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1503 *status = -EREMOTEIO;
1504 else
1505 *status = 0;
1506 break;
1507 default:
1508 if (!xhci_requires_manual_halt_cleanup(xhci,
1509 ep_ctx, trb_comp_code))
1510 break;
1511 xhci_dbg(xhci, "TRB error code %u, "
1512 "halted endpoint index = %u\n",
1513 trb_comp_code, ep_index);
1514
1515 case COMP_STALL:
1516
1517 if (event_trb != ep_ring->dequeue &&
1518 event_trb != td->last_trb)
1519 td->urb->actual_length =
1520 td->urb->transfer_buffer_length
1521 - TRB_LEN(event->transfer_len);
1522 else
1523 td->urb->actual_length = 0;
1524
1525 xhci_cleanup_halted_endpoint(xhci,
1526 slot_id, ep_index, 0, td, event_trb);
1527 return finish_td(xhci, td, event_trb, event, ep, status, true);
1528 }
1529
1530
1531
1532
1533 if (event_trb != ep_ring->dequeue) {
1534
1535 if (event_trb == td->last_trb) {
1536 if (td->urb->actual_length != 0) {
1537
1538
1539 if ((*status == -EINPROGRESS || *status == 0) &&
1540 (td->urb->transfer_flags
1541 & URB_SHORT_NOT_OK))
1542
1543
1544 *status = -EREMOTEIO;
1545 } else {
1546 td->urb->actual_length =
1547 td->urb->transfer_buffer_length;
1548 }
1549 } else {
1550
1551 if (trb_comp_code != COMP_STOP_INVAL) {
1552
1553 td->urb->actual_length =
1554 td->urb->transfer_buffer_length -
1555 TRB_LEN(event->transfer_len);
1556 xhci_dbg(xhci, "Waiting for status "
1557 "stage event\n");
1558 return 0;
1559 }
1560 }
1561 }
1562
1563 return finish_td(xhci, td, event_trb, event, ep, status, false);
1564}
1565
1566
1567
1568
1569static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1570 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1571 struct xhci_virt_ep *ep, int *status)
1572{
1573 struct xhci_ring *ep_ring;
1574 struct urb_priv *urb_priv;
1575 int idx;
1576 int len = 0;
1577 int skip_td = 0;
1578 union xhci_trb *cur_trb;
1579 struct xhci_segment *cur_seg;
1580 u32 trb_comp_code;
1581
1582 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1583 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1584 urb_priv = td->urb->hcpriv;
1585 idx = urb_priv->td_cnt;
1586
1587 if (ep->skip) {
1588
1589 *status = -EXDEV;
1590 td->urb->iso_frame_desc[idx].status = -EXDEV;
1591 } else {
1592
1593 switch (trb_comp_code) {
1594 case COMP_SUCCESS:
1595 td->urb->iso_frame_desc[idx].status = 0;
1596 xhci_dbg(xhci, "Successful isoc transfer!\n");
1597 break;
1598 case COMP_SHORT_TX:
1599 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1600 td->urb->iso_frame_desc[idx].status =
1601 -EREMOTEIO;
1602 else
1603 td->urb->iso_frame_desc[idx].status = 0;
1604 break;
1605 case COMP_BW_OVER:
1606 td->urb->iso_frame_desc[idx].status = -ECOMM;
1607 skip_td = 1;
1608 break;
1609 case COMP_BUFF_OVER:
1610 case COMP_BABBLE:
1611 td->urb->iso_frame_desc[idx].status = -EOVERFLOW;
1612 skip_td = 1;
1613 break;
1614 case COMP_STALL:
1615 td->urb->iso_frame_desc[idx].status = -EPROTO;
1616 skip_td = 1;
1617 break;
1618 case COMP_STOP:
1619 case COMP_STOP_INVAL:
1620 break;
1621 default:
1622 td->urb->iso_frame_desc[idx].status = -1;
1623 break;
1624 }
1625 }
1626
1627
1628 if (ep->skip) {
1629 td->urb->iso_frame_desc[idx].actual_length = 0;
1630
1631 while (ep_ring->dequeue != td->last_trb)
1632 inc_deq(xhci, ep_ring, false);
1633 inc_deq(xhci, ep_ring, false);
1634 return finish_td(xhci, td, event_trb, event, ep, status, true);
1635 }
1636
1637 if (trb_comp_code == COMP_SUCCESS || skip_td == 1) {
1638 td->urb->iso_frame_desc[idx].actual_length =
1639 td->urb->iso_frame_desc[idx].length;
1640 td->urb->actual_length +=
1641 td->urb->iso_frame_desc[idx].length;
1642 } else {
1643 for (cur_trb = ep_ring->dequeue,
1644 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1645 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1646 if ((cur_trb->generic.field[3] &
1647 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1648 (cur_trb->generic.field[3] &
1649 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1650 len +=
1651 TRB_LEN(cur_trb->generic.field[2]);
1652 }
1653 len += TRB_LEN(cur_trb->generic.field[2]) -
1654 TRB_LEN(event->transfer_len);
1655
1656 if (trb_comp_code != COMP_STOP_INVAL) {
1657 td->urb->iso_frame_desc[idx].actual_length = len;
1658 td->urb->actual_length += len;
1659 }
1660 }
1661
1662 if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS)
1663 *status = 0;
1664
1665 return finish_td(xhci, td, event_trb, event, ep, status, false);
1666}
1667
1668
1669
1670
1671static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1672 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1673 struct xhci_virt_ep *ep, int *status)
1674{
1675 struct xhci_ring *ep_ring;
1676 union xhci_trb *cur_trb;
1677 struct xhci_segment *cur_seg;
1678 u32 trb_comp_code;
1679
1680 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1681 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1682
1683 switch (trb_comp_code) {
1684 case COMP_SUCCESS:
1685
1686 if (event_trb != td->last_trb) {
1687 xhci_warn(xhci, "WARN Successful completion "
1688 "on short TX\n");
1689 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1690 *status = -EREMOTEIO;
1691 else
1692 *status = 0;
1693 } else {
1694 if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1695 xhci_dbg(xhci, "Successful bulk "
1696 "transfer!\n");
1697 else
1698 xhci_dbg(xhci, "Successful interrupt "
1699 "transfer!\n");
1700 *status = 0;
1701 }
1702 break;
1703 case COMP_SHORT_TX:
1704 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1705 *status = -EREMOTEIO;
1706 else
1707 *status = 0;
1708 break;
1709 default:
1710
1711 break;
1712 }
1713 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1714 "%d bytes untransferred\n",
1715 td->urb->ep->desc.bEndpointAddress,
1716 td->urb->transfer_buffer_length,
1717 TRB_LEN(event->transfer_len));
1718
1719 if (event_trb == td->last_trb) {
1720 if (TRB_LEN(event->transfer_len) != 0) {
1721 td->urb->actual_length =
1722 td->urb->transfer_buffer_length -
1723 TRB_LEN(event->transfer_len);
1724 if (td->urb->transfer_buffer_length <
1725 td->urb->actual_length) {
1726 xhci_warn(xhci, "HC gave bad length "
1727 "of %d bytes left\n",
1728 TRB_LEN(event->transfer_len));
1729 td->urb->actual_length = 0;
1730 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1731 *status = -EREMOTEIO;
1732 else
1733 *status = 0;
1734 }
1735
1736 if (*status == -EINPROGRESS) {
1737 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1738 *status = -EREMOTEIO;
1739 else
1740 *status = 0;
1741 }
1742 } else {
1743 td->urb->actual_length =
1744 td->urb->transfer_buffer_length;
1745
1746
1747
1748 if (*status == -EREMOTEIO)
1749 *status = 0;
1750 }
1751 } else {
1752
1753
1754
1755 td->urb->actual_length = 0;
1756 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1757 cur_trb != event_trb;
1758 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1759 if ((cur_trb->generic.field[3] &
1760 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1761 (cur_trb->generic.field[3] &
1762 TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1763 td->urb->actual_length +=
1764 TRB_LEN(cur_trb->generic.field[2]);
1765 }
1766
1767
1768
1769 if (trb_comp_code != COMP_STOP_INVAL)
1770 td->urb->actual_length +=
1771 TRB_LEN(cur_trb->generic.field[2]) -
1772 TRB_LEN(event->transfer_len);
1773 }
1774
1775 return finish_td(xhci, td, event_trb, event, ep, status, false);
1776}
1777
1778
1779
1780
1781
1782
1783static int handle_tx_event(struct xhci_hcd *xhci,
1784 struct xhci_transfer_event *event)
1785{
1786 struct xhci_virt_device *xdev;
1787 struct xhci_virt_ep *ep;
1788 struct xhci_ring *ep_ring;
1789 unsigned int slot_id;
1790 int ep_index;
1791 struct xhci_td *td = NULL;
1792 dma_addr_t event_dma;
1793 struct xhci_segment *event_seg;
1794 union xhci_trb *event_trb;
1795 struct urb *urb = NULL;
1796 int status = -EINPROGRESS;
1797 struct urb_priv *urb_priv;
1798 struct xhci_ep_ctx *ep_ctx;
1799 u32 trb_comp_code;
1800 int ret = 0;
1801
1802 slot_id = TRB_TO_SLOT_ID(event->flags);
1803 xdev = xhci->devs[slot_id];
1804 if (!xdev) {
1805 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1806 return -ENODEV;
1807 }
1808
1809
1810 ep_index = TRB_TO_EP_ID(event->flags) - 1;
1811 xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1812 ep = &xdev->eps[ep_index];
1813 ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1814 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1815 if (!ep_ring ||
1816 (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1817 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1818 "or incorrect stream ring\n");
1819 return -ENODEV;
1820 }
1821
1822 event_dma = event->buffer;
1823 trb_comp_code = GET_COMP_CODE(event->transfer_len);
1824
1825 switch (trb_comp_code) {
1826
1827
1828
1829 case COMP_SUCCESS:
1830 case COMP_SHORT_TX:
1831 break;
1832 case COMP_STOP:
1833 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1834 break;
1835 case COMP_STOP_INVAL:
1836 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1837 break;
1838 case COMP_STALL:
1839 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1840 ep->ep_state |= EP_HALTED;
1841 status = -EPIPE;
1842 break;
1843 case COMP_TRB_ERR:
1844 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1845 status = -EILSEQ;
1846 break;
1847 case COMP_SPLIT_ERR:
1848 case COMP_TX_ERR:
1849 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1850 status = -EPROTO;
1851 break;
1852 case COMP_BABBLE:
1853 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1854 status = -EOVERFLOW;
1855 break;
1856 case COMP_DB_ERR:
1857 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1858 status = -ENOSR;
1859 break;
1860 case COMP_BW_OVER:
1861 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
1862 break;
1863 case COMP_BUFF_OVER:
1864 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
1865 break;
1866 case COMP_UNDERRUN:
1867
1868
1869
1870
1871
1872 xhci_dbg(xhci, "underrun event on endpoint\n");
1873 if (!list_empty(&ep_ring->td_list))
1874 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
1875 "still with TDs queued?\n",
1876 TRB_TO_SLOT_ID(event->flags), ep_index);
1877 goto cleanup;
1878 case COMP_OVERRUN:
1879 xhci_dbg(xhci, "overrun event on endpoint\n");
1880 if (!list_empty(&ep_ring->td_list))
1881 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
1882 "still with TDs queued?\n",
1883 TRB_TO_SLOT_ID(event->flags), ep_index);
1884 goto cleanup;
1885 case COMP_MISSED_INT:
1886
1887
1888
1889
1890
1891
1892 ep->skip = true;
1893 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
1894 goto cleanup;
1895 default:
1896 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
1897 status = 0;
1898 break;
1899 }
1900 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
1901 "busted\n");
1902 goto cleanup;
1903 }
1904
1905 do {
1906
1907
1908
1909 if (list_empty(&ep_ring->td_list)) {
1910 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
1911 "with no TDs queued?\n",
1912 TRB_TO_SLOT_ID(event->flags), ep_index);
1913 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1914 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1915 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
1916 if (ep->skip) {
1917 ep->skip = false;
1918 xhci_dbg(xhci, "td_list is empty while skip "
1919 "flag set. Clear skip flag.\n");
1920 }
1921 ret = 0;
1922 goto cleanup;
1923 }
1924
1925 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
1926
1927 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
1928 td->last_trb, event_dma);
1929 if (event_seg && ep->skip) {
1930 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
1931 ep->skip = false;
1932 }
1933 if (!event_seg &&
1934 (!ep->skip || !usb_endpoint_xfer_isoc(&td->urb->ep->desc))) {
1935
1936 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not "
1937 "part of current TD\n");
1938 return -ESHUTDOWN;
1939 }
1940
1941 if (event_seg) {
1942 event_trb = &event_seg->trbs[(event_dma -
1943 event_seg->dma) / sizeof(*event_trb)];
1944
1945
1946
1947
1948
1949
1950 if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK)
1951 == TRB_TYPE(TRB_TR_NOOP)) {
1952 xhci_dbg(xhci, "event_trb is a no-op TRB. "
1953 "Skip it\n");
1954 goto cleanup;
1955 }
1956 }
1957
1958
1959
1960
1961 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
1962 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
1963 &status);
1964 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
1965 ret = process_isoc_td(xhci, td, event_trb, event, ep,
1966 &status);
1967 else
1968 ret = process_bulk_intr_td(xhci, td, event_trb, event,
1969 ep, &status);
1970
1971cleanup:
1972
1973
1974
1975
1976 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
1977 inc_deq(xhci, xhci->event_ring, true);
1978 }
1979
1980 if (ret) {
1981 urb = td->urb;
1982 urb_priv = urb->hcpriv;
1983
1984
1985
1986
1987
1988 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1989 (trb_comp_code != COMP_STALL &&
1990 trb_comp_code != COMP_BABBLE))
1991 xhci_urb_free_priv(xhci, urb_priv);
1992
1993 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1994 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
1995 "status = %d\n",
1996 urb, urb->actual_length, status);
1997 spin_unlock(&xhci->lock);
1998 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1999 spin_lock(&xhci->lock);
2000 }
2001
2002
2003
2004
2005
2006
2007
2008 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2009
2010 return 0;
2011}
2012
2013
2014
2015
2016
2017static void xhci_handle_event(struct xhci_hcd *xhci)
2018{
2019 union xhci_trb *event;
2020 int update_ptrs = 1;
2021 int ret;
2022
2023 xhci_dbg(xhci, "In %s\n", __func__);
2024 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2025 xhci->error_bitmask |= 1 << 1;
2026 return;
2027 }
2028
2029 event = xhci->event_ring->dequeue;
2030
2031 if ((event->event_cmd.flags & TRB_CYCLE) !=
2032 xhci->event_ring->cycle_state) {
2033 xhci->error_bitmask |= 1 << 2;
2034 return;
2035 }
2036 xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
2037
2038
2039 switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
2040 case TRB_TYPE(TRB_COMPLETION):
2041 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
2042 handle_cmd_completion(xhci, &event->event_cmd);
2043 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
2044 break;
2045 case TRB_TYPE(TRB_PORT_STATUS):
2046 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
2047 handle_port_status(xhci, event);
2048 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
2049 update_ptrs = 0;
2050 break;
2051 case TRB_TYPE(TRB_TRANSFER):
2052 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
2053 ret = handle_tx_event(xhci, &event->trans_event);
2054 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
2055 if (ret < 0)
2056 xhci->error_bitmask |= 1 << 9;
2057 else
2058 update_ptrs = 0;
2059 break;
2060 default:
2061 if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48))
2062 handle_vendor_event(xhci, event);
2063 else
2064 xhci->error_bitmask |= 1 << 3;
2065 }
2066
2067
2068
2069 if (xhci->xhc_state & XHCI_STATE_DYING) {
2070 xhci_dbg(xhci, "xHCI host dying, returning from "
2071 "event handler.\n");
2072 return;
2073 }
2074
2075 if (update_ptrs)
2076
2077 inc_deq(xhci, xhci->event_ring, true);
2078
2079
2080 xhci_handle_event(xhci);
2081}
2082
2083
2084
2085
2086
2087
2088irqreturn_t xhci_irq(struct usb_hcd *hcd)
2089{
2090 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2091 u32 status;
2092 union xhci_trb *trb;
2093 u64 temp_64;
2094 union xhci_trb *event_ring_deq;
2095 dma_addr_t deq;
2096
2097 spin_lock(&xhci->lock);
2098 trb = xhci->event_ring->dequeue;
2099
2100 status = xhci_readl(xhci, &xhci->op_regs->status);
2101 if (status == 0xffffffff)
2102 goto hw_died;
2103
2104 if (!(status & STS_EINT)) {
2105 spin_unlock(&xhci->lock);
2106 return IRQ_NONE;
2107 }
2108 xhci_dbg(xhci, "op reg status = %08x\n", status);
2109 xhci_dbg(xhci, "Event ring dequeue ptr:\n");
2110 xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n",
2111 (unsigned long long)
2112 xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb),
2113 lower_32_bits(trb->link.segment_ptr),
2114 upper_32_bits(trb->link.segment_ptr),
2115 (unsigned int) trb->link.intr_target,
2116 (unsigned int) trb->link.control);
2117
2118 if (status & STS_FATAL) {
2119 xhci_warn(xhci, "WARNING: Host System Error\n");
2120 xhci_halt(xhci);
2121hw_died:
2122 xhci_to_hcd(xhci)->state = HC_STATE_HALT;
2123 spin_unlock(&xhci->lock);
2124 return -ESHUTDOWN;
2125 }
2126
2127
2128
2129
2130
2131
2132 status |= STS_EINT;
2133 xhci_writel(xhci, status, &xhci->op_regs->status);
2134
2135
2136
2137 if (hcd->irq != -1) {
2138 u32 irq_pending;
2139
2140 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2141 irq_pending |= 0x3;
2142 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2143 }
2144
2145 if (xhci->xhc_state & XHCI_STATE_DYING) {
2146 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2147 "Shouldn't IRQs be disabled?\n");
2148
2149
2150
2151 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2152 xhci_write_64(xhci, temp_64 | ERST_EHB,
2153 &xhci->ir_set->erst_dequeue);
2154 spin_unlock(&xhci->lock);
2155
2156 return IRQ_HANDLED;
2157 }
2158
2159 event_ring_deq = xhci->event_ring->dequeue;
2160
2161
2162
2163 xhci_handle_event(xhci);
2164
2165 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2166
2167 if (event_ring_deq != xhci->event_ring->dequeue) {
2168 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2169 xhci->event_ring->dequeue);
2170 if (deq == 0)
2171 xhci_warn(xhci, "WARN something wrong with SW event "
2172 "ring dequeue ptr.\n");
2173
2174 temp_64 &= ERST_PTR_MASK;
2175 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2176 }
2177
2178
2179 temp_64 |= ERST_EHB;
2180 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2181
2182 spin_unlock(&xhci->lock);
2183
2184 return IRQ_HANDLED;
2185}
2186
2187irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2188{
2189 irqreturn_t ret;
2190
2191 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2192
2193 ret = xhci_irq(hcd);
2194
2195 return ret;
2196}
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2208 bool consumer, bool more_trbs_coming,
2209 u32 field1, u32 field2, u32 field3, u32 field4)
2210{
2211 struct xhci_generic_trb *trb;
2212
2213 trb = &ring->enqueue->generic;
2214 trb->field[0] = field1;
2215 trb->field[1] = field2;
2216 trb->field[2] = field3;
2217 trb->field[3] = field4;
2218 inc_enq(xhci, ring, consumer, more_trbs_coming);
2219}
2220
2221
2222
2223
2224
2225static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2226 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2227{
2228
2229 xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
2230 switch (ep_state) {
2231 case EP_STATE_DISABLED:
2232
2233
2234
2235
2236 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2237 return -ENOENT;
2238 case EP_STATE_ERROR:
2239 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2240
2241
2242 return -EINVAL;
2243 case EP_STATE_HALTED:
2244 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2245 case EP_STATE_STOPPED:
2246 case EP_STATE_RUNNING:
2247 break;
2248 default:
2249 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2250
2251
2252
2253
2254 return -EINVAL;
2255 }
2256 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2257
2258 xhci_err(xhci, "ERROR no room on ep ring\n");
2259 return -ENOMEM;
2260 }
2261
2262 if (enqueue_is_link_trb(ep_ring)) {
2263 struct xhci_ring *ring = ep_ring;
2264 union xhci_trb *next;
2265
2266 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
2267 next = ring->enqueue;
2268
2269 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2270
2271
2272
2273
2274 if (!xhci_link_trb_quirk(xhci))
2275 next->link.control &= ~TRB_CHAIN;
2276 else
2277 next->link.control |= TRB_CHAIN;
2278
2279 wmb();
2280 next->link.control ^= (u32) TRB_CYCLE;
2281
2282
2283 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2284 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2285 if (!in_interrupt()) {
2286 xhci_dbg(xhci, "queue_trb: Toggle cycle "
2287 "state for ring %p = %i\n",
2288 ring, (unsigned int)ring->cycle_state);
2289 }
2290 }
2291 ring->enq_seg = ring->enq_seg->next;
2292 ring->enqueue = ring->enq_seg->trbs;
2293 next = ring->enqueue;
2294 }
2295 }
2296
2297 return 0;
2298}
2299
2300static int prepare_transfer(struct xhci_hcd *xhci,
2301 struct xhci_virt_device *xdev,
2302 unsigned int ep_index,
2303 unsigned int stream_id,
2304 unsigned int num_trbs,
2305 struct urb *urb,
2306 unsigned int td_index,
2307 gfp_t mem_flags)
2308{
2309 int ret;
2310 struct urb_priv *urb_priv;
2311 struct xhci_td *td;
2312 struct xhci_ring *ep_ring;
2313 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2314
2315 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2316 if (!ep_ring) {
2317 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2318 stream_id);
2319 return -EINVAL;
2320 }
2321
2322 ret = prepare_ring(xhci, ep_ring,
2323 ep_ctx->ep_info & EP_STATE_MASK,
2324 num_trbs, mem_flags);
2325 if (ret)
2326 return ret;
2327
2328 urb_priv = urb->hcpriv;
2329 td = urb_priv->td[td_index];
2330
2331 INIT_LIST_HEAD(&td->td_list);
2332 INIT_LIST_HEAD(&td->cancelled_td_list);
2333
2334 if (td_index == 0) {
2335 ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
2336 if (unlikely(ret)) {
2337 xhci_urb_free_priv(xhci, urb_priv);
2338 urb->hcpriv = NULL;
2339 return ret;
2340 }
2341 }
2342
2343 td->urb = urb;
2344
2345 list_add_tail(&td->td_list, &ep_ring->td_list);
2346 td->start_seg = ep_ring->enq_seg;
2347 td->first_trb = ep_ring->enqueue;
2348
2349 urb_priv->td[td_index] = td;
2350
2351 return 0;
2352}
2353
2354static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2355{
2356 int num_sgs, num_trbs, running_total, temp, i;
2357 struct scatterlist *sg;
2358
2359 sg = NULL;
2360 num_sgs = urb->num_sgs;
2361 temp = urb->transfer_buffer_length;
2362
2363 xhci_dbg(xhci, "count sg list trbs: \n");
2364 num_trbs = 0;
2365 for_each_sg(urb->sg, sg, num_sgs, i) {
2366 unsigned int previous_total_trbs = num_trbs;
2367 unsigned int len = sg_dma_len(sg);
2368
2369
2370 running_total = TRB_MAX_BUFF_SIZE -
2371 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2372 running_total &= TRB_MAX_BUFF_SIZE - 1;
2373 if (running_total != 0)
2374 num_trbs++;
2375
2376
2377 while (running_total < sg_dma_len(sg) && running_total < temp) {
2378 num_trbs++;
2379 running_total += TRB_MAX_BUFF_SIZE;
2380 }
2381 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2382 i, (unsigned long long)sg_dma_address(sg),
2383 len, len, num_trbs - previous_total_trbs);
2384
2385 len = min_t(int, len, temp);
2386 temp -= len;
2387 if (temp == 0)
2388 break;
2389 }
2390 xhci_dbg(xhci, "\n");
2391 if (!in_interrupt())
2392 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2393 "num_trbs = %d\n",
2394 urb->ep->desc.bEndpointAddress,
2395 urb->transfer_buffer_length,
2396 num_trbs);
2397 return num_trbs;
2398}
2399
2400static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2401{
2402 if (num_trbs != 0)
2403 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2404 "TRBs, %d left\n", __func__,
2405 urb->ep->desc.bEndpointAddress, num_trbs);
2406 if (running_total != urb->transfer_buffer_length)
2407 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2408 "queued %#x (%d), asked for %#x (%d)\n",
2409 __func__,
2410 urb->ep->desc.bEndpointAddress,
2411 running_total, running_total,
2412 urb->transfer_buffer_length,
2413 urb->transfer_buffer_length);
2414}
2415
2416static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2417 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2418 struct xhci_generic_trb *start_trb)
2419{
2420
2421
2422
2423
2424 wmb();
2425 if (start_cycle)
2426 start_trb->field[3] |= start_cycle;
2427 else
2428 start_trb->field[3] &= ~0x1;
2429 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2430}
2431
2432
2433
2434
2435
2436
2437
2438int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2439 struct urb *urb, int slot_id, unsigned int ep_index)
2440{
2441 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2442 xhci->devs[slot_id]->out_ctx, ep_index);
2443 int xhci_interval;
2444 int ep_interval;
2445
2446 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
2447 ep_interval = urb->interval;
2448
2449 if (urb->dev->speed == USB_SPEED_LOW ||
2450 urb->dev->speed == USB_SPEED_FULL)
2451 ep_interval *= 8;
2452
2453
2454
2455 if (xhci_interval != ep_interval) {
2456 if (printk_ratelimit())
2457 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2458 " (%d microframe%s) than xHCI "
2459 "(%d microframe%s)\n",
2460 ep_interval,
2461 ep_interval == 1 ? "" : "s",
2462 xhci_interval,
2463 xhci_interval == 1 ? "" : "s");
2464 urb->interval = xhci_interval;
2465
2466 if (urb->dev->speed == USB_SPEED_LOW ||
2467 urb->dev->speed == USB_SPEED_FULL)
2468 urb->interval /= 8;
2469 }
2470 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2471}
2472
2473
2474
2475
2476
2477
2478static u32 xhci_td_remainder(unsigned int remainder)
2479{
2480 u32 max = (1 << (21 - 17 + 1)) - 1;
2481
2482 if ((remainder >> 10) >= max)
2483 return max << 17;
2484 else
2485 return (remainder >> 10) << 17;
2486}
2487
2488static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2489 struct urb *urb, int slot_id, unsigned int ep_index)
2490{
2491 struct xhci_ring *ep_ring;
2492 unsigned int num_trbs;
2493 struct urb_priv *urb_priv;
2494 struct xhci_td *td;
2495 struct scatterlist *sg;
2496 int num_sgs;
2497 int trb_buff_len, this_sg_len, running_total;
2498 bool first_trb;
2499 u64 addr;
2500 bool more_trbs_coming;
2501
2502 struct xhci_generic_trb *start_trb;
2503 int start_cycle;
2504
2505 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2506 if (!ep_ring)
2507 return -EINVAL;
2508
2509 num_trbs = count_sg_trbs_needed(xhci, urb);
2510 num_sgs = urb->num_sgs;
2511
2512 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2513 ep_index, urb->stream_id,
2514 num_trbs, urb, 0, mem_flags);
2515 if (trb_buff_len < 0)
2516 return trb_buff_len;
2517
2518 urb_priv = urb->hcpriv;
2519 td = urb_priv->td[0];
2520
2521
2522
2523
2524
2525
2526 start_trb = &ep_ring->enqueue->generic;
2527 start_cycle = ep_ring->cycle_state;
2528
2529 running_total = 0;
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539 sg = urb->sg;
2540 addr = (u64) sg_dma_address(sg);
2541 this_sg_len = sg_dma_len(sg);
2542 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2543 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2544 if (trb_buff_len > urb->transfer_buffer_length)
2545 trb_buff_len = urb->transfer_buffer_length;
2546 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2547 trb_buff_len);
2548
2549 first_trb = true;
2550
2551 do {
2552 u32 field = 0;
2553 u32 length_field = 0;
2554 u32 remainder = 0;
2555
2556
2557 if (first_trb) {
2558 first_trb = false;
2559 if (start_cycle == 0)
2560 field |= 0x1;
2561 } else
2562 field |= ep_ring->cycle_state;
2563
2564
2565
2566
2567 if (num_trbs > 1) {
2568 field |= TRB_CHAIN;
2569 } else {
2570
2571 td->last_trb = ep_ring->enqueue;
2572 field |= TRB_IOC;
2573 }
2574 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2575 "64KB boundary at %#x, end dma = %#x\n",
2576 (unsigned int) addr, trb_buff_len, trb_buff_len,
2577 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2578 (unsigned int) addr + trb_buff_len);
2579 if (TRB_MAX_BUFF_SIZE -
2580 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2581 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2582 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2583 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2584 (unsigned int) addr + trb_buff_len);
2585 }
2586 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2587 running_total) ;
2588 length_field = TRB_LEN(trb_buff_len) |
2589 remainder |
2590 TRB_INTR_TARGET(0);
2591 if (num_trbs > 1)
2592 more_trbs_coming = true;
2593 else
2594 more_trbs_coming = false;
2595 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2596 lower_32_bits(addr),
2597 upper_32_bits(addr),
2598 length_field,
2599
2600
2601
2602
2603
2604 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2605 --num_trbs;
2606 running_total += trb_buff_len;
2607
2608
2609
2610
2611 this_sg_len -= trb_buff_len;
2612 if (this_sg_len == 0) {
2613 --num_sgs;
2614 if (num_sgs == 0)
2615 break;
2616 sg = sg_next(sg);
2617 addr = (u64) sg_dma_address(sg);
2618 this_sg_len = sg_dma_len(sg);
2619 } else {
2620 addr += trb_buff_len;
2621 }
2622
2623 trb_buff_len = TRB_MAX_BUFF_SIZE -
2624 (addr & (TRB_MAX_BUFF_SIZE - 1));
2625 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2626 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2627 trb_buff_len =
2628 urb->transfer_buffer_length - running_total;
2629 } while (running_total < urb->transfer_buffer_length);
2630
2631 check_trb_math(urb, num_trbs, running_total);
2632 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2633 start_cycle, start_trb);
2634 return 0;
2635}
2636
2637
2638int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2639 struct urb *urb, int slot_id, unsigned int ep_index)
2640{
2641 struct xhci_ring *ep_ring;
2642 struct urb_priv *urb_priv;
2643 struct xhci_td *td;
2644 int num_trbs;
2645 struct xhci_generic_trb *start_trb;
2646 bool first_trb;
2647 bool more_trbs_coming;
2648 int start_cycle;
2649 u32 field, length_field;
2650
2651 int running_total, trb_buff_len, ret;
2652 u64 addr;
2653
2654 if (urb->num_sgs)
2655 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2656
2657 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2658 if (!ep_ring)
2659 return -EINVAL;
2660
2661 num_trbs = 0;
2662
2663 running_total = TRB_MAX_BUFF_SIZE -
2664 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2665 running_total &= TRB_MAX_BUFF_SIZE - 1;
2666
2667
2668
2669
2670 if (running_total != 0 || urb->transfer_buffer_length == 0)
2671 num_trbs++;
2672
2673 while (running_total < urb->transfer_buffer_length) {
2674 num_trbs++;
2675 running_total += TRB_MAX_BUFF_SIZE;
2676 }
2677
2678
2679 if (!in_interrupt())
2680 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2681 "addr = %#llx, num_trbs = %d\n",
2682 urb->ep->desc.bEndpointAddress,
2683 urb->transfer_buffer_length,
2684 urb->transfer_buffer_length,
2685 (unsigned long long)urb->transfer_dma,
2686 num_trbs);
2687
2688 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2689 ep_index, urb->stream_id,
2690 num_trbs, urb, 0, mem_flags);
2691 if (ret < 0)
2692 return ret;
2693
2694 urb_priv = urb->hcpriv;
2695 td = urb_priv->td[0];
2696
2697
2698
2699
2700
2701
2702 start_trb = &ep_ring->enqueue->generic;
2703 start_cycle = ep_ring->cycle_state;
2704
2705 running_total = 0;
2706
2707 addr = (u64) urb->transfer_dma;
2708 trb_buff_len = TRB_MAX_BUFF_SIZE -
2709 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2710 if (trb_buff_len > urb->transfer_buffer_length)
2711 trb_buff_len = urb->transfer_buffer_length;
2712
2713 first_trb = true;
2714
2715
2716 do {
2717 u32 remainder = 0;
2718 field = 0;
2719
2720
2721 if (first_trb) {
2722 first_trb = false;
2723 if (start_cycle == 0)
2724 field |= 0x1;
2725 } else
2726 field |= ep_ring->cycle_state;
2727
2728
2729
2730
2731 if (num_trbs > 1) {
2732 field |= TRB_CHAIN;
2733 } else {
2734
2735 td->last_trb = ep_ring->enqueue;
2736 field |= TRB_IOC;
2737 }
2738 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2739 running_total);
2740 length_field = TRB_LEN(trb_buff_len) |
2741 remainder |
2742 TRB_INTR_TARGET(0);
2743 if (num_trbs > 1)
2744 more_trbs_coming = true;
2745 else
2746 more_trbs_coming = false;
2747 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2748 lower_32_bits(addr),
2749 upper_32_bits(addr),
2750 length_field,
2751
2752
2753
2754
2755
2756 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2757 --num_trbs;
2758 running_total += trb_buff_len;
2759
2760
2761 addr += trb_buff_len;
2762 trb_buff_len = urb->transfer_buffer_length - running_total;
2763 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2764 trb_buff_len = TRB_MAX_BUFF_SIZE;
2765 } while (running_total < urb->transfer_buffer_length);
2766
2767 check_trb_math(urb, num_trbs, running_total);
2768 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2769 start_cycle, start_trb);
2770 return 0;
2771}
2772
2773
2774int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2775 struct urb *urb, int slot_id, unsigned int ep_index)
2776{
2777 struct xhci_ring *ep_ring;
2778 int num_trbs;
2779 int ret;
2780 struct usb_ctrlrequest *setup;
2781 struct xhci_generic_trb *start_trb;
2782 int start_cycle;
2783 u32 field, length_field;
2784 struct urb_priv *urb_priv;
2785 struct xhci_td *td;
2786
2787 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2788 if (!ep_ring)
2789 return -EINVAL;
2790
2791
2792
2793
2794
2795 if (!urb->setup_packet)
2796 return -EINVAL;
2797
2798 if (!in_interrupt())
2799 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2800 slot_id, ep_index);
2801
2802 num_trbs = 2;
2803
2804
2805
2806
2807
2808 if (urb->transfer_buffer_length > 0)
2809 num_trbs++;
2810 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2811 ep_index, urb->stream_id,
2812 num_trbs, urb, 0, mem_flags);
2813 if (ret < 0)
2814 return ret;
2815
2816 urb_priv = urb->hcpriv;
2817 td = urb_priv->td[0];
2818
2819
2820
2821
2822
2823
2824 start_trb = &ep_ring->enqueue->generic;
2825 start_cycle = ep_ring->cycle_state;
2826
2827
2828
2829 setup = (struct usb_ctrlrequest *) urb->setup_packet;
2830 field = 0;
2831 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
2832 if (start_cycle == 0)
2833 field |= 0x1;
2834 queue_trb(xhci, ep_ring, false, true,
2835
2836 setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2837 setup->wIndex | setup->wLength << 16,
2838 TRB_LEN(8) | TRB_INTR_TARGET(0),
2839
2840 field);
2841
2842
2843 field = 0;
2844 length_field = TRB_LEN(urb->transfer_buffer_length) |
2845 xhci_td_remainder(urb->transfer_buffer_length) |
2846 TRB_INTR_TARGET(0);
2847 if (urb->transfer_buffer_length > 0) {
2848 if (setup->bRequestType & USB_DIR_IN)
2849 field |= TRB_DIR_IN;
2850 queue_trb(xhci, ep_ring, false, true,
2851 lower_32_bits(urb->transfer_dma),
2852 upper_32_bits(urb->transfer_dma),
2853 length_field,
2854
2855 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2856 }
2857
2858
2859 td->last_trb = ep_ring->enqueue;
2860
2861
2862
2863 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2864 field = 0;
2865 else
2866 field = TRB_DIR_IN;
2867 queue_trb(xhci, ep_ring, false, false,
2868 0,
2869 0,
2870 TRB_INTR_TARGET(0),
2871
2872 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2873
2874 giveback_first_trb(xhci, slot_id, ep_index, 0,
2875 start_cycle, start_trb);
2876 return 0;
2877}
2878
2879static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
2880 struct urb *urb, int i)
2881{
2882 int num_trbs = 0;
2883 u64 addr, td_len, running_total;
2884
2885 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
2886 td_len = urb->iso_frame_desc[i].length;
2887
2888 running_total = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2889 running_total &= TRB_MAX_BUFF_SIZE - 1;
2890 if (running_total != 0)
2891 num_trbs++;
2892
2893 while (running_total < td_len) {
2894 num_trbs++;
2895 running_total += TRB_MAX_BUFF_SIZE;
2896 }
2897
2898 return num_trbs;
2899}
2900
2901
2902static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2903 struct urb *urb, int slot_id, unsigned int ep_index)
2904{
2905 struct xhci_ring *ep_ring;
2906 struct urb_priv *urb_priv;
2907 struct xhci_td *td;
2908 int num_tds, trbs_per_td;
2909 struct xhci_generic_trb *start_trb;
2910 bool first_trb;
2911 int start_cycle;
2912 u32 field, length_field;
2913 int running_total, trb_buff_len, td_len, td_remain_len, ret;
2914 u64 start_addr, addr;
2915 int i, j;
2916 bool more_trbs_coming;
2917
2918 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
2919
2920 num_tds = urb->number_of_packets;
2921 if (num_tds < 1) {
2922 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
2923 return -EINVAL;
2924 }
2925
2926 if (!in_interrupt())
2927 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
2928 " addr = %#llx, num_tds = %d\n",
2929 urb->ep->desc.bEndpointAddress,
2930 urb->transfer_buffer_length,
2931 urb->transfer_buffer_length,
2932 (unsigned long long)urb->transfer_dma,
2933 num_tds);
2934
2935 start_addr = (u64) urb->transfer_dma;
2936 start_trb = &ep_ring->enqueue->generic;
2937 start_cycle = ep_ring->cycle_state;
2938
2939
2940 for (i = 0; i < num_tds; i++) {
2941 first_trb = true;
2942
2943 running_total = 0;
2944 addr = start_addr + urb->iso_frame_desc[i].offset;
2945 td_len = urb->iso_frame_desc[i].length;
2946 td_remain_len = td_len;
2947
2948 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
2949
2950 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
2951 urb->stream_id, trbs_per_td, urb, i, mem_flags);
2952 if (ret < 0)
2953 return ret;
2954
2955 urb_priv = urb->hcpriv;
2956 td = urb_priv->td[i];
2957
2958 for (j = 0; j < trbs_per_td; j++) {
2959 u32 remainder = 0;
2960 field = 0;
2961
2962 if (first_trb) {
2963
2964 field |= TRB_TYPE(TRB_ISOC);
2965
2966 field |= TRB_SIA;
2967 if (i == 0) {
2968 if (start_cycle == 0)
2969 field |= 0x1;
2970 } else
2971 field |= ep_ring->cycle_state;
2972 first_trb = false;
2973 } else {
2974
2975 field |= TRB_TYPE(TRB_NORMAL);
2976 field |= ep_ring->cycle_state;
2977 }
2978
2979
2980
2981
2982
2983 if (j < trbs_per_td - 1) {
2984 field |= TRB_CHAIN;
2985 more_trbs_coming = true;
2986 } else {
2987 td->last_trb = ep_ring->enqueue;
2988 field |= TRB_IOC;
2989 more_trbs_coming = false;
2990 }
2991
2992
2993 trb_buff_len = TRB_MAX_BUFF_SIZE -
2994 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2995 if (trb_buff_len > td_remain_len)
2996 trb_buff_len = td_remain_len;
2997
2998 remainder = xhci_td_remainder(td_len - running_total);
2999 length_field = TRB_LEN(trb_buff_len) |
3000 remainder |
3001 TRB_INTR_TARGET(0);
3002 queue_trb(xhci, ep_ring, false, more_trbs_coming,
3003 lower_32_bits(addr),
3004 upper_32_bits(addr),
3005 length_field,
3006
3007
3008
3009
3010
3011 field | TRB_ISP);
3012 running_total += trb_buff_len;
3013
3014 addr += trb_buff_len;
3015 td_remain_len -= trb_buff_len;
3016 }
3017
3018
3019 if (running_total != td_len) {
3020 xhci_err(xhci, "ISOC TD length unmatch\n");
3021 return -EINVAL;
3022 }
3023 }
3024
3025 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3026 start_cycle, start_trb);
3027 return 0;
3028}
3029
3030
3031
3032
3033
3034
3035
3036
3037int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3038 struct urb *urb, int slot_id, unsigned int ep_index)
3039{
3040 struct xhci_virt_device *xdev;
3041 struct xhci_ring *ep_ring;
3042 struct xhci_ep_ctx *ep_ctx;
3043 int start_frame;
3044 int xhci_interval;
3045 int ep_interval;
3046 int num_tds, num_trbs, i;
3047 int ret;
3048
3049 xdev = xhci->devs[slot_id];
3050 ep_ring = xdev->eps[ep_index].ring;
3051 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3052
3053 num_trbs = 0;
3054 num_tds = urb->number_of_packets;
3055 for (i = 0; i < num_tds; i++)
3056 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3057
3058
3059
3060
3061 ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK,
3062 num_trbs, mem_flags);
3063 if (ret)
3064 return ret;
3065
3066 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3067 start_frame &= 0x3fff;
3068
3069 urb->start_frame = start_frame;
3070 if (urb->dev->speed == USB_SPEED_LOW ||
3071 urb->dev->speed == USB_SPEED_FULL)
3072 urb->start_frame >>= 3;
3073
3074 xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
3075 ep_interval = urb->interval;
3076
3077 if (urb->dev->speed == USB_SPEED_LOW ||
3078 urb->dev->speed == USB_SPEED_FULL)
3079 ep_interval *= 8;
3080
3081
3082
3083 if (xhci_interval != ep_interval) {
3084 if (printk_ratelimit())
3085 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3086 " (%d microframe%s) than xHCI "
3087 "(%d microframe%s)\n",
3088 ep_interval,
3089 ep_interval == 1 ? "" : "s",
3090 xhci_interval,
3091 xhci_interval == 1 ? "" : "s");
3092 urb->interval = xhci_interval;
3093
3094 if (urb->dev->speed == USB_SPEED_LOW ||
3095 urb->dev->speed == USB_SPEED_FULL)
3096 urb->interval /= 8;
3097 }
3098 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3099}
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3112 u32 field3, u32 field4, bool command_must_succeed)
3113{
3114 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3115 int ret;
3116
3117 if (!command_must_succeed)
3118 reserved_trbs++;
3119
3120 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3121 reserved_trbs, GFP_ATOMIC);
3122 if (ret < 0) {
3123 xhci_err(xhci, "ERR: No room for command on command ring\n");
3124 if (command_must_succeed)
3125 xhci_err(xhci, "ERR: Reserved TRB counting for "
3126 "unfailable commands failed.\n");
3127 return ret;
3128 }
3129 queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
3130 field4 | xhci->cmd_ring->cycle_state);
3131 return 0;
3132}
3133
3134
3135static int queue_cmd_noop(struct xhci_hcd *xhci)
3136{
3137 return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false);
3138}
3139
3140
3141
3142
3143
3144void *xhci_setup_one_noop(struct xhci_hcd *xhci)
3145{
3146 if (queue_cmd_noop(xhci) < 0)
3147 return NULL;
3148 xhci->noops_submitted++;
3149 return xhci_ring_cmd_db;
3150}
3151
3152
3153int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3154{
3155 return queue_command(xhci, 0, 0, 0,
3156 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3157}
3158
3159
3160int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3161 u32 slot_id)
3162{
3163 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3164 upper_32_bits(in_ctx_ptr), 0,
3165 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3166 false);
3167}
3168
3169int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3170 u32 field1, u32 field2, u32 field3, u32 field4)
3171{
3172 return queue_command(xhci, field1, field2, field3, field4, false);
3173}
3174
3175
3176int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3177{
3178 return queue_command(xhci, 0, 0, 0,
3179 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3180 false);
3181}
3182
3183
3184int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3185 u32 slot_id, bool command_must_succeed)
3186{
3187 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3188 upper_32_bits(in_ctx_ptr), 0,
3189 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3190 command_must_succeed);
3191}
3192
3193
3194int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3195 u32 slot_id)
3196{
3197 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3198 upper_32_bits(in_ctx_ptr), 0,
3199 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3200 false);
3201}
3202
3203
3204
3205
3206
3207int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3208 unsigned int ep_index, int suspend)
3209{
3210 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3211 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3212 u32 type = TRB_TYPE(TRB_STOP_RING);
3213 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3214
3215 return queue_command(xhci, 0, 0, 0,
3216 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3217}
3218
3219
3220
3221
3222static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3223 unsigned int ep_index, unsigned int stream_id,
3224 struct xhci_segment *deq_seg,
3225 union xhci_trb *deq_ptr, u32 cycle_state)
3226{
3227 dma_addr_t addr;
3228 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3229 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3230 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3231 u32 type = TRB_TYPE(TRB_SET_DEQ);
3232
3233 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3234 if (addr == 0) {
3235 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3236 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3237 deq_seg, deq_ptr);
3238 return 0;
3239 }
3240 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3241 upper_32_bits(addr), trb_stream_id,
3242 trb_slot_id | trb_ep_index | type, false);
3243}
3244
3245int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3246 unsigned int ep_index)
3247{
3248 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3249 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3250 u32 type = TRB_TYPE(TRB_RESET_EP);
3251
3252 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3253 false);
3254}
3255