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22#ifndef __HW_H__
23#define __HW_H__
24
25#include <linux/seq_file.h>
26
27#include "viamode.h"
28#include "global.h"
29#include "via_modesetting.h"
30
31#define viafb_read_reg(p, i) via_read_reg(p, i)
32#define viafb_write_reg(i, p, d) via_write_reg(p, i, d)
33#define viafb_write_reg_mask(i, p, d, m) via_write_reg_mask(p, i, d, m)
34
35
36#define VIA_LDVP0 0x00000001
37#define VIA_LDVP1 0x00000002
38#define VIA_DVP0 0x00000004
39#define VIA_CRT 0x00000010
40#define VIA_DVP1 0x00000020
41#define VIA_LVDS1 0x00000040
42#define VIA_LVDS2 0x00000080
43
44
45#define VIA_STATE_ON 0
46#define VIA_STATE_STANDBY 1
47#define VIA_STATE_SUSPEND 2
48#define VIA_STATE_OFF 3
49
50
51#define VIA_HSYNC_NEGATIVE 0x01
52#define VIA_VSYNC_NEGATIVE 0x02
53
54
55
56
57#define IGA1_HOR_TOTAL_FORMULA(x) (((x)/8)-5)
58#define IGA1_HOR_ADDR_FORMULA(x) (((x)/8)-1)
59#define IGA1_HOR_BLANK_START_FORMULA(x) (((x)/8)-1)
60#define IGA1_HOR_BLANK_END_FORMULA(x, y) (((x+y)/8)-1)
61#define IGA1_HOR_SYNC_START_FORMULA(x) ((x)/8)
62#define IGA1_HOR_SYNC_END_FORMULA(x, y) ((x+y)/8)
63
64#define IGA1_VER_TOTAL_FORMULA(x) ((x)-2)
65#define IGA1_VER_ADDR_FORMULA(x) ((x)-1)
66#define IGA1_VER_BLANK_START_FORMULA(x) ((x)-1)
67#define IGA1_VER_BLANK_END_FORMULA(x, y) ((x+y)-1)
68#define IGA1_VER_SYNC_START_FORMULA(x) ((x)-1)
69#define IGA1_VER_SYNC_END_FORMULA(x, y) ((x+y)-1)
70
71
72
73
74#define IGA2_HOR_TOTAL_FORMULA(x) ((x)-1)
75#define IGA2_HOR_ADDR_FORMULA(x) ((x)-1)
76#define IGA2_HOR_BLANK_START_FORMULA(x) ((x)-1)
77#define IGA2_HOR_BLANK_END_FORMULA(x, y) ((x+y)-1)
78#define IGA2_HOR_SYNC_START_FORMULA(x) ((x)-1)
79#define IGA2_HOR_SYNC_END_FORMULA(x, y) ((x+y)-1)
80
81#define IGA2_VER_TOTAL_FORMULA(x) ((x)-1)
82#define IGA2_VER_ADDR_FORMULA(x) ((x)-1)
83#define IGA2_VER_BLANK_START_FORMULA(x) ((x)-1)
84#define IGA2_VER_BLANK_END_FORMULA(x, y) ((x+y)-1)
85#define IGA2_VER_SYNC_START_FORMULA(x) ((x)-1)
86#define IGA2_VER_SYNC_END_FORMULA(x, y) ((x+y)-1)
87
88
89
90
91#define IGA2_HOR_TOTAL_SHADOW_FORMULA(x) ((x/8)-5)
92#define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y) (((x+y)/8)-1)
93#define IGA2_VER_TOTAL_SHADOW_FORMULA(x) ((x)-2)
94#define IGA2_VER_ADDR_SHADOW_FORMULA(x) ((x)-1)
95#define IGA2_VER_BLANK_START_SHADOW_FORMULA(x) ((x)-1)
96#define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y) ((x+y)-1)
97#define IGA2_VER_SYNC_START_SHADOW_FORMULA(x) (x)
98#define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y) (x+y)
99
100
101
102
103#define IGA1_HOR_TOTAL_REG_NUM 2
104
105#define IGA1_HOR_ADDR_REG_NUM 1
106
107#define IGA1_HOR_BLANK_START_REG_NUM 1
108
109#define IGA1_HOR_BLANK_END_REG_NUM 3
110
111#define IGA1_HOR_SYNC_START_REG_NUM 2
112
113#define IGA1_HOR_SYNC_END_REG_NUM 1
114
115#define IGA1_VER_TOTAL_REG_NUM 4
116
117#define IGA1_VER_ADDR_REG_NUM 4
118
119#define IGA1_VER_BLANK_START_REG_NUM 4
120
121#define IGA1_VER_BLANK_END_REG_NUM 1
122
123#define IGA1_VER_SYNC_START_REG_NUM 4
124
125#define IGA1_VER_SYNC_END_REG_NUM 1
126
127
128
129
130#define IGA2_SHADOW_HOR_TOTAL_REG_NUM 2
131
132#define IGA2_SHADOW_HOR_BLANK_END_REG_NUM 1
133
134#define IGA2_SHADOW_VER_TOTAL_REG_NUM 2
135
136#define IGA2_SHADOW_VER_ADDR_REG_NUM 2
137
138#define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2
139
140#define IGA2_SHADOW_VER_BLANK_END_REG_NUM 2
141
142#define IGA2_SHADOW_VER_SYNC_START_REG_NUM 2
143
144#define IGA2_SHADOW_VER_SYNC_END_REG_NUM 1
145
146
147
148
149#define IGA2_HOR_TOTAL_REG_NUM 2
150
151#define IGA2_HOR_ADDR_REG_NUM 2
152
153#define IGA2_HOR_BLANK_START_REG_NUM 2
154
155
156
157#define IGA2_HOR_BLANK_END_REG_NUM 3
158
159
160#define IGA2_HOR_SYNC_START_REG_NUM 4
161
162
163#define IGA2_HOR_SYNC_END_REG_NUM 2
164
165#define IGA2_VER_TOTAL_REG_NUM 2
166
167#define IGA2_VER_ADDR_REG_NUM 2
168
169#define IGA2_VER_BLANK_START_REG_NUM 2
170
171#define IGA2_VER_BLANK_END_REG_NUM 2
172
173#define IGA2_VER_SYNC_START_REG_NUM 2
174
175#define IGA2_VER_SYNC_END_REG_NUM 1
176
177
178
179
180#define IGA1_FETCH_COUNT_REG_NUM 2
181
182#define IGA1_FETCH_COUNT_ALIGN_BYTE 16
183
184#define IGA1_FETCH_COUNT_PATCH_VALUE 4
185#define IGA1_FETCH_COUNT_FORMULA(x, y) \
186 (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
187
188
189#define IGA2_FETCH_COUNT_REG_NUM 2
190#define IGA2_FETCH_COUNT_ALIGN_BYTE 16
191#define IGA2_FETCH_COUNT_PATCH_VALUE 0
192#define IGA2_FETCH_COUNT_FORMULA(x, y) \
193 (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE)
194
195
196
197
198#define IGA1_STARTING_ADDR_REG_NUM 4
199
200#define IGA2_STARTING_ADDR_REG_NUM 3
201
202
203
204
205#define K800_IGA1_FIFO_MAX_DEPTH 384
206
207#define K800_IGA1_FIFO_THRESHOLD 328
208
209#define K800_IGA1_FIFO_HIGH_THRESHOLD 296
210
211
212#define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
213
214
215#define K800_IGA2_FIFO_MAX_DEPTH 384
216
217#define K800_IGA2_FIFO_THRESHOLD 328
218
219#define K800_IGA2_FIFO_HIGH_THRESHOLD 296
220
221#define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
222
223
224#define P880_IGA1_FIFO_MAX_DEPTH 192
225
226#define P880_IGA1_FIFO_THRESHOLD 128
227
228#define P880_IGA1_FIFO_HIGH_THRESHOLD 64
229
230
231#define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
232
233
234#define P880_IGA2_FIFO_MAX_DEPTH 96
235
236#define P880_IGA2_FIFO_THRESHOLD 64
237
238#define P880_IGA2_FIFO_HIGH_THRESHOLD 32
239
240#define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
241
242
243
244
245#define CN700_IGA1_FIFO_MAX_DEPTH 96
246
247#define CN700_IGA1_FIFO_THRESHOLD 80
248
249#define CN700_IGA1_FIFO_HIGH_THRESHOLD 64
250
251
252#define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
253
254#define CN700_IGA2_FIFO_MAX_DEPTH 96
255
256#define CN700_IGA2_FIFO_THRESHOLD 80
257
258#define CN700_IGA2_FIFO_HIGH_THRESHOLD 32
259
260#define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
261
262
263
264#define CX700_IGA1_FIFO_MAX_DEPTH 192
265
266#define CX700_IGA1_FIFO_THRESHOLD 128
267
268#define CX700_IGA1_FIFO_HIGH_THRESHOLD 128
269
270#define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124
271
272
273#define CX700_IGA2_FIFO_MAX_DEPTH 96
274
275#define CX700_IGA2_FIFO_THRESHOLD 64
276
277#define CX700_IGA2_FIFO_HIGH_THRESHOLD 32
278
279#define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
280
281
282
283#define K8M890_IGA1_FIFO_MAX_DEPTH 360
284
285#define K8M890_IGA1_FIFO_THRESHOLD 328
286
287#define K8M890_IGA1_FIFO_HIGH_THRESHOLD 296
288
289#define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124
290
291
292#define K8M890_IGA2_FIFO_MAX_DEPTH 360
293
294#define K8M890_IGA2_FIFO_THRESHOLD 328
295
296#define K8M890_IGA2_FIFO_HIGH_THRESHOLD 296
297
298#define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 124
299
300
301
302#define P4M890_IGA1_FIFO_MAX_DEPTH 96
303
304#define P4M890_IGA1_FIFO_THRESHOLD 76
305
306#define P4M890_IGA1_FIFO_HIGH_THRESHOLD 64
307
308#define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32
309
310#define P4M890_IGA2_FIFO_MAX_DEPTH 96
311
312#define P4M890_IGA2_FIFO_THRESHOLD 76
313
314#define P4M890_IGA2_FIFO_HIGH_THRESHOLD 64
315
316#define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32
317
318
319
320#define P4M900_IGA1_FIFO_MAX_DEPTH 96
321
322#define P4M900_IGA1_FIFO_THRESHOLD 76
323
324#define P4M900_IGA1_FIFO_HIGH_THRESHOLD 76
325
326#define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32
327
328#define P4M900_IGA2_FIFO_MAX_DEPTH 96
329
330#define P4M900_IGA2_FIFO_THRESHOLD 76
331
332#define P4M900_IGA2_FIFO_HIGH_THRESHOLD 76
333
334#define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32
335
336
337
338#define VX800_IGA1_FIFO_MAX_DEPTH 192
339
340#define VX800_IGA1_FIFO_THRESHOLD 152
341
342#define VX800_IGA1_FIFO_HIGH_THRESHOLD 152
343
344#define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 64
345
346#define VX800_IGA2_FIFO_MAX_DEPTH 96
347
348#define VX800_IGA2_FIFO_THRESHOLD 64
349
350#define VX800_IGA2_FIFO_HIGH_THRESHOLD 32
351
352#define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
353
354
355#define VX855_IGA1_FIFO_MAX_DEPTH 400
356#define VX855_IGA1_FIFO_THRESHOLD 320
357#define VX855_IGA1_FIFO_HIGH_THRESHOLD 320
358#define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160
359
360#define VX855_IGA2_FIFO_MAX_DEPTH 200
361#define VX855_IGA2_FIFO_THRESHOLD 160
362#define VX855_IGA2_FIFO_HIGH_THRESHOLD 160
363#define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320
364
365
366#define VX900_IGA1_FIFO_MAX_DEPTH 400
367#define VX900_IGA1_FIFO_THRESHOLD 320
368#define VX900_IGA1_FIFO_HIGH_THRESHOLD 320
369#define VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160
370
371#define VX900_IGA2_FIFO_MAX_DEPTH 192
372#define VX900_IGA2_FIFO_THRESHOLD 160
373#define VX900_IGA2_FIFO_HIGH_THRESHOLD 160
374#define VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320
375
376#define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1
377#define IGA1_FIFO_THRESHOLD_REG_NUM 2
378#define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2
379#define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1
380
381#define IGA2_FIFO_DEPTH_SELECT_REG_NUM 3
382#define IGA2_FIFO_THRESHOLD_REG_NUM 2
383#define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM 2
384#define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1
385
386#define IGA1_FIFO_DEPTH_SELECT_FORMULA(x) ((x/2)-1)
387#define IGA1_FIFO_THRESHOLD_FORMULA(x) (x/4)
388#define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4)
389#define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4)
390#define IGA2_FIFO_DEPTH_SELECT_FORMULA(x) (((x/2)/4)-1)
391#define IGA2_FIFO_THRESHOLD_FORMULA(x) (x/4)
392#define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4)
393#define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4)
394
395
396
397
398
399
400#define LCD_POWER_SEQ_TD0 500000
401
402#define LCD_POWER_SEQ_TD1 50000
403
404#define LCD_POWER_SEQ_TD2 0
405
406#define LCD_POWER_SEQ_TD3 210000
407
408#define CLE266_POWER_SEQ_UNIT 71
409
410#define K800_POWER_SEQ_UNIT 142
411
412#define P880_POWER_SEQ_UNIT 572
413
414#define CLE266_POWER_SEQ_FORMULA(x) ((x)/CLE266_POWER_SEQ_UNIT)
415#define K800_POWER_SEQ_FORMULA(x) ((x)/K800_POWER_SEQ_UNIT)
416#define P880_POWER_SEQ_FORMULA(x) ((x)/P880_POWER_SEQ_UNIT)
417
418
419#define LCD_POWER_SEQ_TD0_REG_NUM 2
420
421#define LCD_POWER_SEQ_TD1_REG_NUM 2
422
423#define LCD_POWER_SEQ_TD2_REG_NUM 2
424
425#define LCD_POWER_SEQ_TD3_REG_NUM 2
426
427
428
429
430
431
432#define CLE266_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1))
433
434#define CLE266_LCD_VER_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1))
435
436#define K800_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*4096)/(y-1))
437
438#define K800_LCD_VER_SCF_FORMULA(x, y) (((x-1)*2048)/(y-1))
439
440
441#define LCD_HOR_SCALING_FACTOR_REG_NUM 3
442
443#define LCD_VER_SCALING_FACTOR_REG_NUM 3
444
445#define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE 2
446
447#define LCD_VER_SCALING_FACTOR_REG_NUM_CLE 2
448
449
450
451
452struct io_register {
453 u8 io_addr;
454 u8 start_bit;
455 u8 end_bit;
456};
457
458
459struct iga1_hor_total {
460 int reg_num;
461 struct io_register reg[IGA1_HOR_TOTAL_REG_NUM];
462};
463
464
465struct iga1_hor_addr {
466 int reg_num;
467 struct io_register reg[IGA1_HOR_ADDR_REG_NUM];
468};
469
470
471struct iga1_hor_blank_start {
472 int reg_num;
473 struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM];
474};
475
476
477struct iga1_hor_blank_end {
478 int reg_num;
479 struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM];
480};
481
482
483struct iga1_hor_sync_start {
484 int reg_num;
485 struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM];
486};
487
488
489struct iga1_hor_sync_end {
490 int reg_num;
491 struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM];
492};
493
494
495struct iga1_ver_total {
496 int reg_num;
497 struct io_register reg[IGA1_VER_TOTAL_REG_NUM];
498};
499
500
501struct iga1_ver_addr {
502 int reg_num;
503 struct io_register reg[IGA1_VER_ADDR_REG_NUM];
504};
505
506
507struct iga1_ver_blank_start {
508 int reg_num;
509 struct io_register reg[IGA1_VER_BLANK_START_REG_NUM];
510};
511
512
513struct iga1_ver_blank_end {
514 int reg_num;
515 struct io_register reg[IGA1_VER_BLANK_END_REG_NUM];
516};
517
518
519struct iga1_ver_sync_start {
520 int reg_num;
521 struct io_register reg[IGA1_VER_SYNC_START_REG_NUM];
522};
523
524
525struct iga1_ver_sync_end {
526 int reg_num;
527 struct io_register reg[IGA1_VER_SYNC_END_REG_NUM];
528};
529
530
531
532
533
534
535struct iga2_shadow_hor_total {
536 int reg_num;
537 struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
538};
539
540
541struct iga2_shadow_hor_blank_end {
542 int reg_num;
543 struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
544};
545
546
547struct iga2_shadow_ver_total {
548 int reg_num;
549 struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
550};
551
552
553struct iga2_shadow_ver_addr {
554 int reg_num;
555 struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
556};
557
558
559struct iga2_shadow_ver_blank_start {
560 int reg_num;
561 struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
562};
563
564
565struct iga2_shadow_ver_blank_end {
566 int reg_num;
567 struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
568};
569
570
571struct iga2_shadow_ver_sync_start {
572 int reg_num;
573 struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
574};
575
576
577struct iga2_shadow_ver_sync_end {
578 int reg_num;
579 struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
580};
581
582
583
584
585
586
587struct iga2_hor_total {
588 int reg_num;
589 struct io_register reg[IGA2_HOR_TOTAL_REG_NUM];
590};
591
592
593struct iga2_hor_addr {
594 int reg_num;
595 struct io_register reg[IGA2_HOR_ADDR_REG_NUM];
596};
597
598
599struct iga2_hor_blank_start {
600 int reg_num;
601 struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM];
602};
603
604
605struct iga2_hor_blank_end {
606 int reg_num;
607 struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM];
608};
609
610
611struct iga2_hor_sync_start {
612 int reg_num;
613 struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM];
614};
615
616
617struct iga2_hor_sync_end {
618 int reg_num;
619 struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM];
620};
621
622
623struct iga2_ver_total {
624 int reg_num;
625 struct io_register reg[IGA2_VER_TOTAL_REG_NUM];
626};
627
628
629struct iga2_ver_addr {
630 int reg_num;
631 struct io_register reg[IGA2_VER_ADDR_REG_NUM];
632};
633
634
635struct iga2_ver_blank_start {
636 int reg_num;
637 struct io_register reg[IGA2_VER_BLANK_START_REG_NUM];
638};
639
640
641struct iga2_ver_blank_end {
642 int reg_num;
643 struct io_register reg[IGA2_VER_BLANK_END_REG_NUM];
644};
645
646
647struct iga2_ver_sync_start {
648 int reg_num;
649 struct io_register reg[IGA2_VER_SYNC_START_REG_NUM];
650};
651
652
653struct iga2_ver_sync_end {
654 int reg_num;
655 struct io_register reg[IGA2_VER_SYNC_END_REG_NUM];
656};
657
658
659struct iga1_fetch_count {
660 int reg_num;
661 struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
662};
663
664
665struct iga2_fetch_count {
666 int reg_num;
667 struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
668};
669
670struct fetch_count {
671 struct iga1_fetch_count iga1_fetch_count_reg;
672 struct iga2_fetch_count iga2_fetch_count_reg;
673};
674
675
676struct iga1_starting_addr {
677 int reg_num;
678 struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
679};
680
681struct iga2_starting_addr {
682 int reg_num;
683 struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
684};
685
686struct starting_addr {
687 struct iga1_starting_addr iga1_starting_addr_reg;
688 struct iga2_starting_addr iga2_starting_addr_reg;
689};
690
691
692struct lcd_pwd_seq_td0 {
693 int reg_num;
694 struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
695};
696
697struct lcd_pwd_seq_td1 {
698 int reg_num;
699 struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
700};
701
702struct lcd_pwd_seq_td2 {
703 int reg_num;
704 struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
705};
706
707struct lcd_pwd_seq_td3 {
708 int reg_num;
709 struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
710};
711
712struct _lcd_pwd_seq_timer {
713 struct lcd_pwd_seq_td0 td0;
714 struct lcd_pwd_seq_td1 td1;
715 struct lcd_pwd_seq_td2 td2;
716 struct lcd_pwd_seq_td3 td3;
717};
718
719
720struct _lcd_hor_scaling_factor {
721 int reg_num;
722 struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
723};
724
725struct _lcd_ver_scaling_factor {
726 int reg_num;
727 struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
728};
729
730struct _lcd_scaling_factor {
731 struct _lcd_hor_scaling_factor lcd_hor_scaling_factor;
732 struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
733};
734
735struct pll_config {
736 u16 multiplier;
737 u8 divisor;
738 u8 rshift;
739};
740
741struct pll_map {
742 u32 clk;
743 struct pll_config cle266_pll;
744 struct pll_config k800_pll;
745 struct pll_config cx700_pll;
746 struct pll_config vx855_pll;
747};
748
749struct rgbLUT {
750 u8 red;
751 u8 green;
752 u8 blue;
753};
754
755struct lcd_pwd_seq_timer {
756 u16 td0;
757 u16 td1;
758 u16 td2;
759 u16 td3;
760};
761
762
763struct iga1_fifo_depth_select {
764 int reg_num;
765 struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
766};
767
768struct iga1_fifo_threshold_select {
769 int reg_num;
770 struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
771};
772
773struct iga1_fifo_high_threshold_select {
774 int reg_num;
775 struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
776};
777
778struct iga1_display_queue_expire_num {
779 int reg_num;
780 struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
781};
782
783struct iga2_fifo_depth_select {
784 int reg_num;
785 struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
786};
787
788struct iga2_fifo_threshold_select {
789 int reg_num;
790 struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
791};
792
793struct iga2_fifo_high_threshold_select {
794 int reg_num;
795 struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
796};
797
798struct iga2_display_queue_expire_num {
799 int reg_num;
800 struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
801};
802
803struct fifo_depth_select {
804 struct iga1_fifo_depth_select iga1_fifo_depth_select_reg;
805 struct iga2_fifo_depth_select iga2_fifo_depth_select_reg;
806};
807
808struct fifo_threshold_select {
809 struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
810 struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
811};
812
813struct fifo_high_threshold_select {
814 struct iga1_fifo_high_threshold_select
815 iga1_fifo_high_threshold_select_reg;
816 struct iga2_fifo_high_threshold_select
817 iga2_fifo_high_threshold_select_reg;
818};
819
820struct display_queue_expire_num {
821 struct iga1_display_queue_expire_num
822 iga1_display_queue_expire_num_reg;
823 struct iga2_display_queue_expire_num
824 iga2_display_queue_expire_num_reg;
825};
826
827struct iga1_crtc_timing {
828 struct iga1_hor_total hor_total;
829 struct iga1_hor_addr hor_addr;
830 struct iga1_hor_blank_start hor_blank_start;
831 struct iga1_hor_blank_end hor_blank_end;
832 struct iga1_hor_sync_start hor_sync_start;
833 struct iga1_hor_sync_end hor_sync_end;
834 struct iga1_ver_total ver_total;
835 struct iga1_ver_addr ver_addr;
836 struct iga1_ver_blank_start ver_blank_start;
837 struct iga1_ver_blank_end ver_blank_end;
838 struct iga1_ver_sync_start ver_sync_start;
839 struct iga1_ver_sync_end ver_sync_end;
840};
841
842struct iga2_shadow_crtc_timing {
843 struct iga2_shadow_hor_total hor_total_shadow;
844 struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
845 struct iga2_shadow_ver_total ver_total_shadow;
846 struct iga2_shadow_ver_addr ver_addr_shadow;
847 struct iga2_shadow_ver_blank_start ver_blank_start_shadow;
848 struct iga2_shadow_ver_blank_end ver_blank_end_shadow;
849 struct iga2_shadow_ver_sync_start ver_sync_start_shadow;
850 struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
851};
852
853struct iga2_crtc_timing {
854 struct iga2_hor_total hor_total;
855 struct iga2_hor_addr hor_addr;
856 struct iga2_hor_blank_start hor_blank_start;
857 struct iga2_hor_blank_end hor_blank_end;
858 struct iga2_hor_sync_start hor_sync_start;
859 struct iga2_hor_sync_end hor_sync_end;
860 struct iga2_ver_total ver_total;
861 struct iga2_ver_addr ver_addr;
862 struct iga2_ver_blank_start ver_blank_start;
863 struct iga2_ver_blank_end ver_blank_end;
864 struct iga2_ver_sync_start ver_sync_start;
865 struct iga2_ver_sync_end ver_sync_end;
866};
867
868
869#define CLE266_FUNCTION3 0x3123
870#define KM400_FUNCTION3 0x3205
871#define CN400_FUNCTION2 0x2259
872#define CN400_FUNCTION3 0x3259
873
874#define CN700_FUNCTION2 0x2314
875#define CN700_FUNCTION3 0x3208
876
877#define CX700_FUNCTION2 0x2324
878#define CX700_FUNCTION3 0x3324
879
880#define KM800_FUNCTION3 0x3204
881
882#define KM890_FUNCTION3 0x3336
883
884#define P4M890_FUNCTION3 0x3327
885
886#define CN750_FUNCTION3 0x3208
887
888#define P4M900_FUNCTION3 0x3364
889
890#define VX800_FUNCTION3 0x3353
891
892#define VX855_FUNCTION3 0x3409
893
894#define VX900_FUNCTION3 0x3410
895
896#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
897
898struct IODATA {
899 u8 Index;
900 u8 Mask;
901 u8 Data;
902};
903
904struct pci_device_id_info {
905 u32 vendor;
906 u32 device;
907 u32 chip_index;
908};
909
910struct via_device_mapping {
911 u32 device;
912 const char *name;
913};
914
915extern unsigned int viafb_second_virtual_xres;
916extern int viafb_SAMM_ON;
917extern int viafb_dual_fb;
918extern int viafb_LCD2_ON;
919extern int viafb_LCD_ON;
920extern int viafb_DVI_ON;
921extern int viafb_hotplug;
922
923void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
924 struct VideoModeTable *video_mode, int bpp_byte, int set_iga);
925
926void viafb_set_vclock(u32 CLK, int set_iga);
927void viafb_load_reg(int timing_value, int viafb_load_reg_num,
928 struct io_register *reg,
929 int io_type);
930void via_set_source(u32 devices, u8 iga);
931void via_set_state(u32 devices, u8 state);
932void via_set_sync_polarity(u32 devices, u8 polarity);
933u32 via_parse_odev(char *input, char **end);
934void via_odev_to_seq(struct seq_file *m, u32 odev);
935void init_ad9389(void);
936
937void viafb_lock_crt(void);
938void viafb_unlock_crt(void);
939void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
940void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
941u32 viafb_get_clk_value(int clk);
942void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
943void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
944 *p_gfx_dpa_setting);
945
946int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
947 struct VideoModeTable *vmode_tbl1, int video_bpp1);
948void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
949 struct VideoModeTable *vmode_tbl);
950void __devinit viafb_init_chip_info(int chip_type);
951void __devinit viafb_init_dac(int set_iga);
952int viafb_get_pixclock(int hres, int vres, int vmode_refresh);
953int viafb_get_refresh(int hres, int vres, u32 float_refresh);
954void viafb_update_device_setting(int hres, int vres, int bpp,
955 int vmode_refresh, int flag);
956
957void viafb_set_iga_path(void);
958void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue);
959void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue);
960void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
961
962#endif
963