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17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
20#include <linux/pci_regs.h>
21
22
23
24
25
26
27
28
29
30#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32#define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34
35#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00)
37#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01)
38#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02)
39#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03)
40
41#ifdef __KERNEL__
42
43#include <linux/mod_devicetable.h>
44
45#include <linux/types.h>
46#include <linux/init.h>
47#include <linux/ioport.h>
48#include <linux/list.h>
49#include <linux/compiler.h>
50#include <linux/errno.h>
51#include <linux/kobject.h>
52#include <asm/atomic.h>
53#include <linux/device.h>
54#include <linux/io.h>
55#include <linux/irqreturn.h>
56
57
58#include <linux/pci_ids.h>
59
60
61struct pci_slot {
62 struct pci_bus *bus;
63 struct list_head list;
64 struct hotplug_slot *hotplug;
65 unsigned char number;
66 struct kobject kobj;
67};
68
69static inline const char *pci_slot_name(const struct pci_slot *slot)
70{
71 return kobject_name(&slot->kobj);
72}
73
74
75enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78};
79
80
81#define PCI_DMA_BIDIRECTIONAL 0
82#define PCI_DMA_TODEVICE 1
83#define PCI_DMA_FROMDEVICE 2
84#define PCI_DMA_NONE 3
85
86
87
88
89enum {
90
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94
95 PCI_ROM_RESOURCE,
96
97
98#ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101#endif
102
103
104#define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110
111 PCI_NUM_RESOURCES,
112
113
114 DEVICE_COUNT_RESOURCE
115};
116
117typedef int __bitwise pci_power_t;
118
119#define PCI_D0 ((pci_power_t __force) 0)
120#define PCI_D1 ((pci_power_t __force) 1)
121#define PCI_D2 ((pci_power_t __force) 2)
122#define PCI_D3hot ((pci_power_t __force) 3)
123#define PCI_D3cold ((pci_power_t __force) 4)
124#define PCI_UNKNOWN ((pci_power_t __force) 5)
125#define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127
128extern const char *pci_power_names[];
129
130static inline const char *pci_power_name(pci_power_t state)
131{
132 return pci_power_names[1 + (int) state];
133}
134
135#define PCI_PM_D2_DELAY 200
136#define PCI_PM_D3_WAIT 10
137#define PCI_PM_BUS_WAIT 50
138
139
140
141
142
143typedef unsigned int __bitwise pci_channel_state_t;
144
145enum pci_channel_state {
146
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154};
155
156typedef unsigned int __bitwise pcie_reset_state_t;
157
158enum pcie_reset_state {
159
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167};
168
169typedef unsigned short __bitwise pci_dev_flags_t;
170enum pci_dev_flags {
171
172
173
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177};
178
179enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182};
183
184typedef unsigned short __bitwise pci_bus_flags_t;
185enum pci_bus_flags {
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
188};
189
190
191enum pci_bus_speed {
192 PCI_SPEED_33MHz = 0x00,
193 PCI_SPEED_66MHz = 0x01,
194 PCI_SPEED_66MHz_PCIX = 0x02,
195 PCI_SPEED_100MHz_PCIX = 0x03,
196 PCI_SPEED_133MHz_PCIX = 0x04,
197 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
198 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
199 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
200 PCI_SPEED_66MHz_PCIX_266 = 0x09,
201 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
202 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
203 AGP_UNKNOWN = 0x0c,
204 AGP_1X = 0x0d,
205 AGP_2X = 0x0e,
206 AGP_4X = 0x0f,
207 AGP_8X = 0x10,
208 PCI_SPEED_66MHz_PCIX_533 = 0x11,
209 PCI_SPEED_100MHz_PCIX_533 = 0x12,
210 PCI_SPEED_133MHz_PCIX_533 = 0x13,
211 PCIE_SPEED_2_5GT = 0x14,
212 PCIE_SPEED_5_0GT = 0x15,
213 PCIE_SPEED_8_0GT = 0x16,
214 PCI_SPEED_UNKNOWN = 0xff,
215};
216
217struct pci_cap_saved_state {
218 struct hlist_node next;
219 char cap_nr;
220 u32 data[0];
221};
222
223struct pcie_link_state;
224struct pci_vpd;
225struct pci_sriov;
226struct pci_ats;
227
228
229
230
231struct pci_dev {
232 struct list_head bus_list;
233 struct pci_bus *bus;
234 struct pci_bus *subordinate;
235
236 void *sysdata;
237 struct proc_dir_entry *procent;
238 struct pci_slot *slot;
239
240 unsigned int devfn;
241 unsigned short vendor;
242 unsigned short device;
243 unsigned short subsystem_vendor;
244 unsigned short subsystem_device;
245 unsigned int class;
246 u8 revision;
247 u8 hdr_type;
248 u8 pcie_cap;
249 u8 pcie_type;
250 u8 rom_base_reg;
251 u8 pin;
252
253 struct pci_driver *driver;
254 u64 dma_mask;
255
256
257
258
259
260 struct device_dma_parameters dma_parms;
261
262 pci_power_t current_state;
263
264
265 int pm_cap;
266
267 unsigned int pme_support:5;
268
269 unsigned int pme_interrupt:1;
270 unsigned int d1_support:1;
271 unsigned int d2_support:1;
272 unsigned int no_d1d2:1;
273 unsigned int mmio_always_on:1;
274
275 unsigned int wakeup_prepared:1;
276 unsigned int d3_delay;
277
278#ifdef CONFIG_PCIEASPM
279 struct pcie_link_state *link_state;
280#endif
281
282 pci_channel_state_t error_state;
283 struct device dev;
284
285 int cfg_size;
286
287
288
289
290
291 unsigned int irq;
292 struct resource resource[DEVICE_COUNT_RESOURCE];
293 resource_size_t fw_addr[DEVICE_COUNT_RESOURCE];
294
295
296 unsigned int transparent:1;
297 unsigned int multifunction:1;
298
299 unsigned int is_added:1;
300 unsigned int is_busmaster:1;
301 unsigned int no_msi:1;
302 unsigned int block_ucfg_access:1;
303 unsigned int broken_parity_status:1;
304 unsigned int irq_reroute_variant:2;
305 unsigned int msi_enabled:1;
306 unsigned int msix_enabled:1;
307 unsigned int ari_enabled:1;
308 unsigned int is_managed:1;
309 unsigned int is_pcie:1;
310
311 unsigned int needs_freset:1;
312 unsigned int state_saved:1;
313 unsigned int is_physfn:1;
314 unsigned int is_virtfn:1;
315 unsigned int reset_fn:1;
316 unsigned int is_hotplug_bridge:1;
317 unsigned int __aer_firmware_first_valid:1;
318 unsigned int __aer_firmware_first:1;
319 pci_dev_flags_t dev_flags;
320 atomic_t enable_cnt;
321
322 u32 saved_config_space[16];
323 struct hlist_head saved_cap_space;
324 struct bin_attribute *rom_attr;
325 int rom_attr_enabled;
326 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE];
327 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE];
328#ifdef CONFIG_PCI_MSI
329 struct list_head msi_list;
330#endif
331 struct pci_vpd *vpd;
332#ifdef CONFIG_PCI_IOV
333 union {
334 struct pci_sriov *sriov;
335 struct pci_dev *physfn;
336 };
337 struct pci_ats *ats;
338#endif
339};
340
341static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
342{
343#ifdef CONFIG_PCI_IOV
344 if (dev->is_virtfn)
345 dev = dev->physfn;
346#endif
347
348 return dev;
349}
350
351extern struct pci_dev *alloc_pci_dev(void);
352
353#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
354#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
355#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
356
357static inline int pci_channel_offline(struct pci_dev *pdev)
358{
359 return (pdev->error_state != pci_channel_io_normal);
360}
361
362static inline struct pci_cap_saved_state *pci_find_saved_cap(
363 struct pci_dev *pci_dev, char cap)
364{
365 struct pci_cap_saved_state *tmp;
366 struct hlist_node *pos;
367
368 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
369 if (tmp->cap_nr == cap)
370 return tmp;
371 }
372 return NULL;
373}
374
375static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
376 struct pci_cap_saved_state *new_cap)
377{
378 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
379}
380
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391
392
393
394#define PCI_SUBTRACTIVE_DECODE 0x1
395
396struct pci_bus_resource {
397 struct list_head list;
398 struct resource *res;
399 unsigned int flags;
400};
401
402#define PCI_REGION_FLAG_MASK 0x0fU
403
404struct pci_bus {
405 struct list_head node;
406 struct pci_bus *parent;
407 struct list_head children;
408 struct list_head devices;
409 struct pci_dev *self;
410 struct list_head slots;
411 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
412 struct list_head resources;
413
414 struct pci_ops *ops;
415 void *sysdata;
416 struct proc_dir_entry *procdir;
417
418 unsigned char number;
419 unsigned char primary;
420 unsigned char secondary;
421 unsigned char subordinate;
422 unsigned char max_bus_speed;
423 unsigned char cur_bus_speed;
424
425 char name[48];
426
427 unsigned short bridge_ctl;
428 pci_bus_flags_t bus_flags;
429 struct device *bridge;
430 struct device dev;
431 struct bin_attribute *legacy_io;
432 struct bin_attribute *legacy_mem;
433 unsigned int is_added:1;
434};
435
436#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
437#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
438
439
440
441
442
443static inline bool pci_is_root_bus(struct pci_bus *pbus)
444{
445 return !(pbus->parent);
446}
447
448#ifdef CONFIG_PCI_MSI
449static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
450{
451 return pci_dev->msi_enabled || pci_dev->msix_enabled;
452}
453#else
454static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
455#endif
456
457
458
459
460#define PCIBIOS_SUCCESSFUL 0x00
461#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
462#define PCIBIOS_BAD_VENDOR_ID 0x83
463#define PCIBIOS_DEVICE_NOT_FOUND 0x86
464#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
465#define PCIBIOS_SET_FAILED 0x88
466#define PCIBIOS_BUFFER_TOO_SMALL 0x89
467
468
469
470struct pci_ops {
471 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
472 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
473};
474
475
476
477
478
479extern int raw_pci_read(unsigned int domain, unsigned int bus,
480 unsigned int devfn, int reg, int len, u32 *val);
481extern int raw_pci_write(unsigned int domain, unsigned int bus,
482 unsigned int devfn, int reg, int len, u32 val);
483
484struct pci_bus_region {
485 resource_size_t start;
486 resource_size_t end;
487};
488
489struct pci_dynids {
490 spinlock_t lock;
491 struct list_head list;
492};
493
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498
499
500
501typedef unsigned int __bitwise pci_ers_result_t;
502
503enum pci_ers_result {
504
505 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
506
507
508 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
509
510
511 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
512
513
514 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
515
516
517 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
518};
519
520
521struct pci_error_handlers {
522
523 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
524 enum pci_channel_state error);
525
526
527 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
528
529
530 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
531
532
533 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
534
535
536 void (*resume)(struct pci_dev *dev);
537};
538
539
540
541struct module;
542struct pci_driver {
543 struct list_head node;
544 const char *name;
545 const struct pci_device_id *id_table;
546 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id);
547 void (*remove) (struct pci_dev *dev);
548 int (*suspend) (struct pci_dev *dev, pm_message_t state);
549 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
550 int (*resume_early) (struct pci_dev *dev);
551 int (*resume) (struct pci_dev *dev);
552 void (*shutdown) (struct pci_dev *dev);
553 struct pci_error_handlers *err_handler;
554 struct device_driver driver;
555 struct pci_dynids dynids;
556};
557
558#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
559
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565
566
567#define DEFINE_PCI_DEVICE_TABLE(_table) \
568 const struct pci_device_id _table[] __devinitconst
569
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577
578
579#define PCI_DEVICE(vend,dev) \
580 .vendor = (vend), .device = (dev), \
581 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
582
583
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590
591
592#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
593 .class = (dev_class), .class_mask = (dev_class_mask), \
594 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
595 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
596
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606
607
608#define PCI_VDEVICE(vendor, device) \
609 PCI_VENDOR_ID_##vendor, (device), \
610 PCI_ANY_ID, PCI_ANY_ID, 0, 0
611
612
613#ifdef CONFIG_PCI
614
615extern struct bus_type pci_bus_type;
616
617
618
619extern struct list_head pci_root_buses;
620
621extern int no_pci_devices(void);
622
623void pcibios_fixup_bus(struct pci_bus *);
624int __must_check pcibios_enable_device(struct pci_dev *, int mask);
625char *pcibios_setup(char *str);
626
627
628resource_size_t pcibios_align_resource(void *, const struct resource *,
629 resource_size_t,
630 resource_size_t);
631void pcibios_update_irq(struct pci_dev *, int irq);
632
633
634void pci_fixup_cardbus(struct pci_bus *);
635
636
637
638void pcibios_scan_specific_bus(int busn);
639extern struct pci_bus *pci_find_bus(int domain, int busnr);
640void pci_bus_add_devices(const struct pci_bus *bus);
641struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
642 struct pci_ops *ops, void *sysdata);
643static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
644 void *sysdata)
645{
646 struct pci_bus *root_bus;
647 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
648 if (root_bus)
649 pci_bus_add_devices(root_bus);
650 return root_bus;
651}
652struct pci_bus *pci_create_bus(struct device *parent, int bus,
653 struct pci_ops *ops, void *sysdata);
654struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
655 int busnr);
656void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
657struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
658 const char *name,
659 struct hotplug_slot *hotplug);
660void pci_destroy_slot(struct pci_slot *slot);
661void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
662int pci_scan_slot(struct pci_bus *bus, int devfn);
663struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
664void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
665unsigned int pci_scan_child_bus(struct pci_bus *bus);
666int __must_check pci_bus_add_device(struct pci_dev *dev);
667void pci_read_bridge_bases(struct pci_bus *child);
668struct resource *pci_find_parent_resource(const struct pci_dev *dev,
669 struct resource *res);
670u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
671int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
672u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
673extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
674extern void pci_dev_put(struct pci_dev *dev);
675extern void pci_remove_bus(struct pci_bus *b);
676extern void pci_remove_bus_device(struct pci_dev *dev);
677extern void pci_stop_bus_device(struct pci_dev *dev);
678void pci_setup_cardbus(struct pci_bus *bus);
679extern void pci_sort_breadthfirst(void);
680#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
681#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
682#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
683
684
685
686enum pci_lost_interrupt_reason {
687 PCI_LOST_IRQ_NO_INFORMATION = 0,
688 PCI_LOST_IRQ_DISABLE_MSI,
689 PCI_LOST_IRQ_DISABLE_MSIX,
690 PCI_LOST_IRQ_DISABLE_ACPI,
691};
692enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
693int pci_find_capability(struct pci_dev *dev, int cap);
694int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
695int pci_find_ext_capability(struct pci_dev *dev, int cap);
696int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
697 int cap);
698int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
699int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
700struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
701
702struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
703 struct pci_dev *from);
704struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
705 unsigned int ss_vendor, unsigned int ss_device,
706 struct pci_dev *from);
707struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
708struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
709 unsigned int devfn);
710static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
711 unsigned int devfn)
712{
713 return pci_get_domain_bus_and_slot(0, bus, devfn);
714}
715struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
716int pci_dev_present(const struct pci_device_id *ids);
717
718int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
719 int where, u8 *val);
720int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
721 int where, u16 *val);
722int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
723 int where, u32 *val);
724int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
725 int where, u8 val);
726int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
727 int where, u16 val);
728int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
729 int where, u32 val);
730struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
731
732static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
733{
734 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
735}
736static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
737{
738 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
739}
740static inline int pci_read_config_dword(struct pci_dev *dev, int where,
741 u32 *val)
742{
743 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
744}
745static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
746{
747 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
748}
749static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
750{
751 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
752}
753static inline int pci_write_config_dword(struct pci_dev *dev, int where,
754 u32 val)
755{
756 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
757}
758
759int __must_check pci_enable_device(struct pci_dev *dev);
760int __must_check pci_enable_device_io(struct pci_dev *dev);
761int __must_check pci_enable_device_mem(struct pci_dev *dev);
762int __must_check pci_reenable_device(struct pci_dev *);
763int __must_check pcim_enable_device(struct pci_dev *pdev);
764void pcim_pin_device(struct pci_dev *pdev);
765
766static inline int pci_is_enabled(struct pci_dev *pdev)
767{
768 return (atomic_read(&pdev->enable_cnt) > 0);
769}
770
771static inline int pci_is_managed(struct pci_dev *pdev)
772{
773 return pdev->is_managed;
774}
775
776void pci_disable_device(struct pci_dev *dev);
777void pci_set_master(struct pci_dev *dev);
778void pci_clear_master(struct pci_dev *dev);
779int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
780int pci_set_cacheline_size(struct pci_dev *dev);
781#define HAVE_PCI_SET_MWI
782int __must_check pci_set_mwi(struct pci_dev *dev);
783int pci_try_set_mwi(struct pci_dev *dev);
784void pci_clear_mwi(struct pci_dev *dev);
785void pci_intx(struct pci_dev *dev, int enable);
786void pci_msi_off(struct pci_dev *dev);
787int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
788int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
789int pcix_get_max_mmrbc(struct pci_dev *dev);
790int pcix_get_mmrbc(struct pci_dev *dev);
791int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
792int pcie_get_readrq(struct pci_dev *dev);
793int pcie_set_readrq(struct pci_dev *dev, int rq);
794int __pci_reset_function(struct pci_dev *dev);
795int pci_reset_function(struct pci_dev *dev);
796void pci_update_resource(struct pci_dev *dev, int resno);
797int __must_check pci_assign_resource(struct pci_dev *dev, int i);
798int pci_select_bars(struct pci_dev *dev, unsigned long flags);
799
800
801int pci_enable_rom(struct pci_dev *pdev);
802void pci_disable_rom(struct pci_dev *pdev);
803void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
804void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
805size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
806
807
808int pci_save_state(struct pci_dev *dev);
809void pci_restore_state(struct pci_dev *dev);
810int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
811int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
812pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
813bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
814void pci_pme_active(struct pci_dev *dev, bool enable);
815int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
816 bool runtime, bool enable);
817int pci_wake_from_d3(struct pci_dev *dev, bool enable);
818pci_power_t pci_target_state(struct pci_dev *dev);
819int pci_prepare_to_sleep(struct pci_dev *dev);
820int pci_back_from_sleep(struct pci_dev *dev);
821bool pci_dev_run_wake(struct pci_dev *dev);
822bool pci_check_pme_status(struct pci_dev *dev);
823void pci_pme_wakeup_bus(struct pci_bus *bus);
824
825static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
826 bool enable)
827{
828 return __pci_enable_wake(dev, state, false, enable);
829}
830
831
832void set_pcie_port_type(struct pci_dev *pdev);
833void set_pcie_hotplug_bridge(struct pci_dev *pdev);
834
835
836int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
837#ifdef CONFIG_HOTPLUG
838unsigned int pci_rescan_bus(struct pci_bus *bus);
839#endif
840
841
842ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
843ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
844int pci_vpd_truncate(struct pci_dev *dev, size_t size);
845
846
847void pci_bus_assign_resources(const struct pci_bus *bus);
848void pci_bus_size_bridges(struct pci_bus *bus);
849int pci_claim_resource(struct pci_dev *, int);
850void pci_assign_unassigned_resources(void);
851void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
852void pdev_enable_device(struct pci_dev *);
853void pdev_sort_resources(struct pci_dev *, struct resource_list *);
854int pci_enable_resources(struct pci_dev *, int mask);
855void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
856 int (*)(struct pci_dev *, u8, u8));
857#define HAVE_PCI_REQ_REGIONS 2
858int __must_check pci_request_regions(struct pci_dev *, const char *);
859int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
860void pci_release_regions(struct pci_dev *);
861int __must_check pci_request_region(struct pci_dev *, int, const char *);
862int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
863void pci_release_region(struct pci_dev *, int);
864int pci_request_selected_regions(struct pci_dev *, int, const char *);
865int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
866void pci_release_selected_regions(struct pci_dev *, int);
867
868
869void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
870struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
871void pci_bus_remove_resources(struct pci_bus *bus);
872
873#define pci_bus_for_each_resource(bus, res, i) \
874 for (i = 0; \
875 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
876 i++)
877
878int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
879 struct resource *res, resource_size_t size,
880 resource_size_t align, resource_size_t min,
881 unsigned int type_mask,
882 resource_size_t (*alignf)(void *,
883 const struct resource *,
884 resource_size_t,
885 resource_size_t),
886 void *alignf_data);
887void pci_enable_bridges(struct pci_bus *bus);
888
889
890int __must_check __pci_register_driver(struct pci_driver *, struct module *,
891 const char *mod_name);
892
893
894
895
896#define pci_register_driver(driver) \
897 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
898
899void pci_unregister_driver(struct pci_driver *dev);
900void pci_remove_behind_bridge(struct pci_dev *dev);
901struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
902int pci_add_dynid(struct pci_driver *drv,
903 unsigned int vendor, unsigned int device,
904 unsigned int subvendor, unsigned int subdevice,
905 unsigned int class, unsigned int class_mask,
906 unsigned long driver_data);
907const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
908 struct pci_dev *dev);
909int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
910 int pass);
911
912void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
913 void *userdata);
914int pci_cfg_space_size_ext(struct pci_dev *dev);
915int pci_cfg_space_size(struct pci_dev *dev);
916unsigned char pci_bus_max_busnr(struct pci_bus *bus);
917
918int pci_set_vga_state(struct pci_dev *pdev, bool decode,
919 unsigned int command_bits, bool change_bridge);
920
921
922#include <linux/pci-dma.h>
923#include <linux/dmapool.h>
924
925#define pci_pool dma_pool
926#define pci_pool_create(name, pdev, size, align, allocation) \
927 dma_pool_create(name, &pdev->dev, size, align, allocation)
928#define pci_pool_destroy(pool) dma_pool_destroy(pool)
929#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
930#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
931
932enum pci_dma_burst_strategy {
933 PCI_DMA_BURST_INFINITY,
934
935 PCI_DMA_BURST_BOUNDARY,
936
937 PCI_DMA_BURST_MULTIPLE,
938
939};
940
941struct msix_entry {
942 u32 vector;
943 u16 entry;
944};
945
946
947#ifndef CONFIG_PCI_MSI
948static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
949{
950 return -1;
951}
952
953static inline void pci_msi_shutdown(struct pci_dev *dev)
954{ }
955static inline void pci_disable_msi(struct pci_dev *dev)
956{ }
957
958static inline int pci_msix_table_size(struct pci_dev *dev)
959{
960 return 0;
961}
962static inline int pci_enable_msix(struct pci_dev *dev,
963 struct msix_entry *entries, int nvec)
964{
965 return -1;
966}
967
968static inline void pci_msix_shutdown(struct pci_dev *dev)
969{ }
970static inline void pci_disable_msix(struct pci_dev *dev)
971{ }
972
973static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
974{ }
975
976static inline void pci_restore_msi_state(struct pci_dev *dev)
977{ }
978static inline int pci_msi_enabled(void)
979{
980 return 0;
981}
982#else
983extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
984extern void pci_msi_shutdown(struct pci_dev *dev);
985extern void pci_disable_msi(struct pci_dev *dev);
986extern int pci_msix_table_size(struct pci_dev *dev);
987extern int pci_enable_msix(struct pci_dev *dev,
988 struct msix_entry *entries, int nvec);
989extern void pci_msix_shutdown(struct pci_dev *dev);
990extern void pci_disable_msix(struct pci_dev *dev);
991extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
992extern void pci_restore_msi_state(struct pci_dev *dev);
993extern int pci_msi_enabled(void);
994#endif
995
996#ifdef CONFIG_PCIEPORTBUS
997extern bool pcie_ports_disabled;
998extern bool pcie_ports_auto;
999#else
1000#define pcie_ports_disabled true
1001#define pcie_ports_auto false
1002#endif
1003
1004#ifndef CONFIG_PCIEASPM
1005static inline int pcie_aspm_enabled(void)
1006{
1007 return 0;
1008}
1009#else
1010extern int pcie_aspm_enabled(void);
1011#endif
1012
1013#ifdef CONFIG_PCIEAER
1014void pci_no_aer(void);
1015bool pci_aer_available(void);
1016#else
1017static inline void pci_no_aer(void) { }
1018static inline bool pci_aer_available(void) { return false; }
1019#endif
1020
1021#ifndef CONFIG_PCIE_ECRC
1022static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1023{
1024 return;
1025}
1026static inline void pcie_ecrc_get_policy(char *str) {};
1027#else
1028extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1029extern void pcie_ecrc_get_policy(char *str);
1030#endif
1031
1032#define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1033
1034#ifdef CONFIG_HT_IRQ
1035
1036int ht_create_irq(struct pci_dev *dev, int idx);
1037void ht_destroy_irq(unsigned int irq);
1038#endif
1039
1040extern void pci_block_user_cfg_access(struct pci_dev *dev);
1041extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
1042
1043
1044
1045
1046
1047
1048#ifdef CONFIG_PCI_DOMAINS
1049extern int pci_domains_supported;
1050#else
1051enum { pci_domains_supported = 0 };
1052static inline int pci_domain_nr(struct pci_bus *bus)
1053{
1054 return 0;
1055}
1056
1057static inline int pci_proc_domain(struct pci_bus *bus)
1058{
1059 return 0;
1060}
1061#endif
1062
1063
1064typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1065 unsigned int command_bits, bool change_bridge);
1066extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1067
1068#else
1069
1070
1071
1072
1073
1074
1075#define _PCI_NOP(o, s, t) \
1076 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1077 int where, t val) \
1078 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1079
1080#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1081 _PCI_NOP(o, word, u16 x) \
1082 _PCI_NOP(o, dword, u32 x)
1083_PCI_NOP_ALL(read, *)
1084_PCI_NOP_ALL(write,)
1085
1086static inline struct pci_dev *pci_get_device(unsigned int vendor,
1087 unsigned int device,
1088 struct pci_dev *from)
1089{
1090 return NULL;
1091}
1092
1093static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1094 unsigned int device,
1095 unsigned int ss_vendor,
1096 unsigned int ss_device,
1097 struct pci_dev *from)
1098{
1099 return NULL;
1100}
1101
1102static inline struct pci_dev *pci_get_class(unsigned int class,
1103 struct pci_dev *from)
1104{
1105 return NULL;
1106}
1107
1108#define pci_dev_present(ids) (0)
1109#define no_pci_devices() (1)
1110#define pci_dev_put(dev) do { } while (0)
1111
1112static inline void pci_set_master(struct pci_dev *dev)
1113{ }
1114
1115static inline int pci_enable_device(struct pci_dev *dev)
1116{
1117 return -EIO;
1118}
1119
1120static inline void pci_disable_device(struct pci_dev *dev)
1121{ }
1122
1123static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1124{
1125 return -EIO;
1126}
1127
1128static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1129{
1130 return -EIO;
1131}
1132
1133static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1134 unsigned int size)
1135{
1136 return -EIO;
1137}
1138
1139static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1140 unsigned long mask)
1141{
1142 return -EIO;
1143}
1144
1145static inline int pci_assign_resource(struct pci_dev *dev, int i)
1146{
1147 return -EBUSY;
1148}
1149
1150static inline int __pci_register_driver(struct pci_driver *drv,
1151 struct module *owner)
1152{
1153 return 0;
1154}
1155
1156static inline int pci_register_driver(struct pci_driver *drv)
1157{
1158 return 0;
1159}
1160
1161static inline void pci_unregister_driver(struct pci_driver *drv)
1162{ }
1163
1164static inline int pci_find_capability(struct pci_dev *dev, int cap)
1165{
1166 return 0;
1167}
1168
1169static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1170 int cap)
1171{
1172 return 0;
1173}
1174
1175static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1176{
1177 return 0;
1178}
1179
1180
1181static inline int pci_save_state(struct pci_dev *dev)
1182{
1183 return 0;
1184}
1185
1186static inline void pci_restore_state(struct pci_dev *dev)
1187{ }
1188
1189static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1190{
1191 return 0;
1192}
1193
1194static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1195 pm_message_t state)
1196{
1197 return PCI_D0;
1198}
1199
1200static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1201 int enable)
1202{
1203 return 0;
1204}
1205
1206static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1207{
1208 return -EIO;
1209}
1210
1211static inline void pci_release_regions(struct pci_dev *dev)
1212{ }
1213
1214#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1215
1216static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1217{ }
1218
1219static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1220{ }
1221
1222static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1223{ return NULL; }
1224
1225static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1226 unsigned int devfn)
1227{ return NULL; }
1228
1229static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1230 unsigned int devfn)
1231{ return NULL; }
1232
1233static inline int pci_domain_nr(struct pci_bus *bus)
1234{ return 0; }
1235
1236#define dev_is_pci(d) (false)
1237#define dev_is_pf(d) (false)
1238#define dev_num_vf(d) (0)
1239#endif
1240
1241
1242
1243#include <asm/pci.h>
1244
1245#ifndef PCIBIOS_MAX_MEM_32
1246#define PCIBIOS_MAX_MEM_32 (-1)
1247#endif
1248
1249
1250
1251#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1252#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1253#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1254#define pci_resource_len(dev,bar) \
1255 ((pci_resource_start((dev), (bar)) == 0 && \
1256 pci_resource_end((dev), (bar)) == \
1257 pci_resource_start((dev), (bar))) ? 0 : \
1258 \
1259 (pci_resource_end((dev), (bar)) - \
1260 pci_resource_start((dev), (bar)) + 1))
1261
1262
1263
1264
1265
1266static inline void *pci_get_drvdata(struct pci_dev *pdev)
1267{
1268 return dev_get_drvdata(&pdev->dev);
1269}
1270
1271static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1272{
1273 dev_set_drvdata(&pdev->dev, data);
1274}
1275
1276
1277
1278
1279static inline const char *pci_name(const struct pci_dev *pdev)
1280{
1281 return dev_name(&pdev->dev);
1282}
1283
1284
1285
1286
1287
1288#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1289static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1290 const struct resource *rsrc, resource_size_t *start,
1291 resource_size_t *end)
1292{
1293 *start = rsrc->start;
1294 *end = rsrc->end;
1295}
1296#endif
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306struct pci_fixup {
1307 u16 vendor, device;
1308 void (*hook)(struct pci_dev *dev);
1309};
1310
1311enum pci_fixup_pass {
1312 pci_fixup_early,
1313 pci_fixup_header,
1314 pci_fixup_final,
1315 pci_fixup_enable,
1316 pci_fixup_resume,
1317 pci_fixup_suspend,
1318 pci_fixup_resume_early,
1319};
1320
1321
1322#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1323 static const struct pci_fixup __pci_fixup_##name __used \
1324 __attribute__((__section__(#section))) = { vendor, device, hook };
1325#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1326 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1327 vendor##device##hook, vendor, device, hook)
1328#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1329 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1330 vendor##device##hook, vendor, device, hook)
1331#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1332 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1333 vendor##device##hook, vendor, device, hook)
1334#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1335 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1336 vendor##device##hook, vendor, device, hook)
1337#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1338 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1339 resume##vendor##device##hook, vendor, device, hook)
1340#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1341 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1342 resume_early##vendor##device##hook, vendor, device, hook)
1343#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1344 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1345 suspend##vendor##device##hook, vendor, device, hook)
1346
1347#ifdef CONFIG_PCI_QUIRKS
1348void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1349#else
1350static inline void pci_fixup_device(enum pci_fixup_pass pass,
1351 struct pci_dev *dev) {}
1352#endif
1353
1354void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1355void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1356void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1357int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1358int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1359 const char *name);
1360void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1361
1362extern int pci_pci_problems;
1363#define PCIPCI_FAIL 1
1364#define PCIPCI_TRITON 2
1365#define PCIPCI_NATOMA 4
1366#define PCIPCI_VIAETBF 8
1367#define PCIPCI_VSFX 16
1368#define PCIPCI_ALIMAGIK 32
1369#define PCIAGP_FAIL 64
1370
1371extern unsigned long pci_cardbus_io_size;
1372extern unsigned long pci_cardbus_mem_size;
1373extern u8 __devinitdata pci_dfl_cache_line_size;
1374extern u8 pci_cache_line_size;
1375
1376extern unsigned long pci_hotplug_io_size;
1377extern unsigned long pci_hotplug_mem_size;
1378
1379int pcibios_add_platform_entries(struct pci_dev *dev);
1380void pcibios_disable_device(struct pci_dev *dev);
1381int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1382 enum pcie_reset_state state);
1383
1384#ifdef CONFIG_PCI_MMCONFIG
1385extern void __init pci_mmcfg_early_init(void);
1386extern void __init pci_mmcfg_late_init(void);
1387#else
1388static inline void pci_mmcfg_early_init(void) { }
1389static inline void pci_mmcfg_late_init(void) { }
1390#endif
1391
1392int pci_ext_cfg_avail(struct pci_dev *dev);
1393
1394void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1395
1396#ifdef CONFIG_PCI_IOV
1397extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1398extern void pci_disable_sriov(struct pci_dev *dev);
1399extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1400extern int pci_num_vf(struct pci_dev *dev);
1401#else
1402static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1403{
1404 return -ENODEV;
1405}
1406static inline void pci_disable_sriov(struct pci_dev *dev)
1407{
1408}
1409static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1410{
1411 return IRQ_NONE;
1412}
1413static inline int pci_num_vf(struct pci_dev *dev)
1414{
1415 return 0;
1416}
1417#endif
1418
1419#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1420extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1421extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1422#endif
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1434
1435static inline int pci_pcie_cap(struct pci_dev *dev)
1436{
1437 return dev->pcie_cap;
1438}
1439
1440
1441
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1444
1445
1446static inline bool pci_is_pcie(struct pci_dev *dev)
1447{
1448 return !!pci_pcie_cap(dev);
1449}
1450
1451void pci_request_acs(void);
1452
1453
1454#define PCI_VPD_LRDT 0x80
1455#define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1456
1457
1458#define PCI_VPD_LTIN_ID_STRING 0x02
1459#define PCI_VPD_LTIN_RO_DATA 0x10
1460#define PCI_VPD_LTIN_RW_DATA 0x11
1461
1462#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1463#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1464#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1465
1466
1467#define PCI_VPD_STIN_END 0x78
1468
1469#define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1470
1471#define PCI_VPD_SRDT_TIN_MASK 0x78
1472#define PCI_VPD_SRDT_LEN_MASK 0x07
1473
1474#define PCI_VPD_LRDT_TAG_SIZE 3
1475#define PCI_VPD_SRDT_TAG_SIZE 1
1476
1477#define PCI_VPD_INFO_FLD_HDR_SIZE 3
1478
1479#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1480#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1481#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1482
1483
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1488
1489static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1490{
1491 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1492}
1493
1494
1495
1496
1497
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1499
1500static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1501{
1502 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1503}
1504
1505
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1510
1511static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1512{
1513 return info_field[2];
1514}
1515
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1525
1526int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
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1537
1538int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1539 unsigned int len, const char *kw);
1540
1541#endif
1542#endif
1543