1#ifndef __SOUND_EMU10K1_H
2#define __SOUND_EMU10K1_H
3
4#include <linux/types.h>
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28#ifdef __KERNEL__
29
30#include <sound/pcm.h>
31#include <sound/rawmidi.h>
32#include <sound/hwdep.h>
33#include <sound/ac97_codec.h>
34#include <sound/util_mem.h>
35#include <sound/pcm-indirect.h>
36#include <sound/timer.h>
37#include <linux/interrupt.h>
38#include <linux/mutex.h>
39
40#include <asm/io.h>
41
42
43
44#define EMUPAGESIZE 4096
45#define MAXREQVOICES 8
46#define MAXPAGES 8192
47#define RESERVED 0
48#define NUM_MIDI 16
49#define NUM_G 64
50#define NUM_FXSENDS 4
51#define NUM_EFX_PLAYBACK 16
52
53
54#define EMU10K1_DMA_MASK 0x7fffffffUL
55#define AUDIGY_DMA_MASK 0x7fffffffUL
56
57
58#define TMEMSIZE 256*1024
59#define TMEMSIZEREG 4
60
61#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
62
63
64
65
66
67
68
69#define PTR 0x00
70
71
72#define PTR_CHANNELNUM_MASK 0x0000003f
73
74
75
76#define PTR_ADDRESS_MASK 0x07ff0000
77#define A_PTR_ADDRESS_MASK 0x0fff0000
78
79#define DATA 0x04
80
81#define IPR 0x08
82
83
84#define IPR_P16V 0x80000000
85
86#define IPR_GPIOMSG 0x20000000
87
88
89
90#define IPR_A_MIDITRANSBUFEMPTY2 0x10000000
91#define IPR_A_MIDIRECVBUFEMPTY2 0x08000000
92
93#define IPR_SPDIFBUFFULL 0x04000000
94#define IPR_SPDIFBUFHALFFULL 0x02000000
95
96#define IPR_SAMPLERATETRACKER 0x01000000
97#define IPR_FXDSP 0x00800000
98#define IPR_FORCEINT 0x00400000
99#define IPR_PCIERROR 0x00200000
100#define IPR_VOLINCR 0x00100000
101#define IPR_VOLDECR 0x00080000
102#define IPR_MUTE 0x00040000
103#define IPR_MICBUFFULL 0x00020000
104#define IPR_MICBUFHALFFULL 0x00010000
105#define IPR_ADCBUFFULL 0x00008000
106#define IPR_ADCBUFHALFFULL 0x00004000
107#define IPR_EFXBUFFULL 0x00002000
108#define IPR_EFXBUFHALFFULL 0x00001000
109#define IPR_GPSPDIFSTATUSCHANGE 0x00000800
110#define IPR_CDROMSTATUSCHANGE 0x00000400
111#define IPR_INTERVALTIMER 0x00000200
112#define IPR_MIDITRANSBUFEMPTY 0x00000100
113#define IPR_MIDIRECVBUFEMPTY 0x00000080
114#define IPR_CHANNELLOOP 0x00000040
115#define IPR_CHANNELNUMBERMASK 0x0000003f
116
117
118
119
120
121#define INTE 0x0c
122#define INTE_VIRTUALSB_MASK 0xc0000000
123#define INTE_VIRTUALSB_220 0x00000000
124#define INTE_VIRTUALSB_240 0x40000000
125#define INTE_VIRTUALSB_260 0x80000000
126#define INTE_VIRTUALSB_280 0xc0000000
127#define INTE_VIRTUALMPU_MASK 0x30000000
128#define INTE_VIRTUALMPU_300 0x00000000
129#define INTE_VIRTUALMPU_310 0x10000000
130#define INTE_VIRTUALMPU_320 0x20000000
131#define INTE_VIRTUALMPU_330 0x30000000
132#define INTE_MASTERDMAENABLE 0x08000000
133#define INTE_SLAVEDMAENABLE 0x04000000
134#define INTE_MASTERPICENABLE 0x02000000
135#define INTE_SLAVEPICENABLE 0x01000000
136#define INTE_VSBENABLE 0x00800000
137#define INTE_ADLIBENABLE 0x00400000
138#define INTE_MPUENABLE 0x00200000
139#define INTE_FORCEINT 0x00100000
140
141#define INTE_MRHANDENABLE 0x00080000
142
143
144
145
146
147
148#define INTE_A_MIDITXENABLE2 0x00020000
149#define INTE_A_MIDIRXENABLE2 0x00010000
150
151
152#define INTE_SAMPLERATETRACKER 0x00002000
153
154#define INTE_FXDSPENABLE 0x00001000
155#define INTE_PCIERRORENABLE 0x00000800
156#define INTE_VOLINCRENABLE 0x00000400
157#define INTE_VOLDECRENABLE 0x00000200
158#define INTE_MUTEENABLE 0x00000100
159#define INTE_MICBUFENABLE 0x00000080
160#define INTE_ADCBUFENABLE 0x00000040
161#define INTE_EFXBUFENABLE 0x00000020
162#define INTE_GPSPDIFENABLE 0x00000010
163#define INTE_CDSPDIFENABLE 0x00000008
164#define INTE_INTERVALTIMERENB 0x00000004
165#define INTE_MIDITXENABLE 0x00000002
166#define INTE_MIDIRXENABLE 0x00000001
167
168#define WC 0x10
169#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0
170#define WC_SAMPLECOUNTER 0x14060010
171#define WC_CURRENTCHANNEL 0x0000003F
172
173
174
175#define HCFG 0x14
176
177
178
179
180#define HCFG_LEGACYFUNC_MASK 0xe0000000
181#define HCFG_LEGACYFUNC_MPU 0x00000000
182#define HCFG_LEGACYFUNC_SB 0x40000000
183#define HCFG_LEGACYFUNC_AD 0x60000000
184#define HCFG_LEGACYFUNC_MPIC 0x80000000
185#define HCFG_LEGACYFUNC_MDMA 0xa0000000
186#define HCFG_LEGACYFUNC_SPCI 0xc0000000
187#define HCFG_LEGACYFUNC_SDMA 0xe0000000
188#define HCFG_IOCAPTUREADDR 0x1f000000
189#define HCFG_LEGACYWRITE 0x00800000
190#define HCFG_LEGACYWORD 0x00400000
191#define HCFG_LEGACYINT 0x00200000
192
193
194#define HCFG_PUSH_BUTTON_ENABLE 0x00100000
195#define HCFG_BAUD_RATE 0x00080000
196#define HCFG_EXPANDED_MEM 0x00040000
197#define HCFG_CODECFORMAT_MASK 0x00030000
198
199
200#define HCFG_CODECFORMAT_AC97_1 0x00000000
201#define HCFG_CODECFORMAT_AC97_2 0x00010000
202#define HCFG_AUTOMUTE_ASYNC 0x00008000
203
204
205
206#define HCFG_AUTOMUTE_SPDIF 0x00004000
207
208
209#define HCFG_EMU32_SLAVE 0x00002000
210#define HCFG_SLOW_RAMP 0x00001000
211
212#define HCFG_PHASE_TRACK_MASK 0x00000700
213
214
215#define HCFG_I2S_ASRC_ENABLE 0x00000070
216
217
218
219
220
221
222
223#define HCFG_CODECFORMAT_AC97 0x00000000
224#define HCFG_CODECFORMAT_I2S 0x00010000
225#define HCFG_GPINPUT0 0x00004000
226#define HCFG_GPINPUT1 0x00002000
227#define HCFG_GPOUTPUT_MASK 0x00001c00
228#define HCFG_GPOUT0 0x00001000
229#define HCFG_GPOUT1 0x00000800
230#define HCFG_GPOUT2 0x00000400
231#define HCFG_JOYENABLE 0x00000200
232#define HCFG_PHASETRACKENABLE 0x00000100
233
234
235#define HCFG_AC3ENABLE_MASK 0x000000e0
236#define HCFG_AC3ENABLE_ZVIDEO 0x00000080
237#define HCFG_AC3ENABLE_CDSPDIF 0x00000040
238#define HCFG_AC3ENABLE_GPSPDIF 0x00000020
239#define HCFG_AUTOMUTE 0x00000010
240
241
242
243#define HCFG_LOCKSOUNDCACHE 0x00000008
244
245#define HCFG_LOCKTANKCACHE_MASK 0x00000004
246
247#define HCFG_LOCKTANKCACHE 0x01020014
248#define HCFG_MUTEBUTTONENABLE 0x00000002
249
250
251
252
253
254#define HCFG_AUDIOENABLE 0x00000001
255
256
257
258
259
260#define MUDATA 0x18
261
262#define MUCMD 0x19
263#define MUCMD_RESET 0xff
264#define MUCMD_ENTERUARTMODE 0x3f
265
266
267#define MUSTAT MUCMD
268#define MUSTAT_IRDYN 0x80
269#define MUSTAT_ORDYN 0x40
270
271#define A_IOCFG 0x18
272#define A_GPINPUT_MASK 0xff00
273#define A_GPOUTPUT_MASK 0x00ff
274
275
276#define A_IOCFG_GPOUT0 0x0044
277#define A_IOCFG_DISABLE_ANALOG 0x0040
278#define A_IOCFG_ENABLE_DIGITAL 0x0004
279#define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080
280#define A_IOCFG_UNKNOWN_20 0x0020
281#define A_IOCFG_DISABLE_AC97_FRONT 0x0080
282#define A_IOCFG_GPOUT1 0x0002
283#define A_IOCFG_GPOUT2 0x0001
284#define A_IOCFG_MULTIPURPOSE_JACK 0x2000
285
286#define A_IOCFG_DIGITAL_JACK 0x1000
287#define A_IOCFG_FRONT_JACK 0x4000
288#define A_IOCFG_REAR_JACK 0x8000
289#define A_IOCFG_PHONES_JACK 0x0100
290
291
292
293
294
295
296
297#define TIMER 0x1a
298
299
300
301#define TIMER_RATE_MASK 0x000003ff
302
303#define TIMER_RATE 0x0a00001a
304
305#define AC97DATA 0x1c
306
307#define AC97ADDRESS 0x1e
308#define AC97ADDRESS_READY 0x80
309#define AC97ADDRESS_ADDRESS 0x7f
310
311
312#define PTR2 0x20
313#define DATA2 0x24
314#define IPR2 0x28
315#define IPR2_PLAYBACK_CH_0_LOOP 0x00001000
316#define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100
317#define IPR2_CAPTURE_CH_0_LOOP 0x00100000
318#define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000
319
320
321
322#define INTE2 0x2c
323#define INTE2_PLAYBACK_CH_0_LOOP 0x00001000
324#define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100
325#define INTE2_PLAYBACK_CH_1_LOOP 0x00002000
326#define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200
327#define INTE2_PLAYBACK_CH_2_LOOP 0x00004000
328#define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400
329#define INTE2_PLAYBACK_CH_3_LOOP 0x00008000
330#define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800
331#define INTE2_CAPTURE_CH_0_LOOP 0x00100000
332#define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000
333#define HCFG2 0x34
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349#define IPR3 0x38
350#define INTE3 0x3c
351
352
353
354
355#define JOYSTICK1 0x00
356#define JOYSTICK2 0x01
357#define JOYSTICK3 0x02
358#define JOYSTICK4 0x03
359#define JOYSTICK5 0x04
360#define JOYSTICK6 0x05
361#define JOYSTICK7 0x06
362#define JOYSTICK8 0x07
363
364
365
366#define JOYSTICK_BUTTONS 0x0f
367#define JOYSTICK_COMPARATOR 0xf0
368
369
370
371
372
373
374#define CPF 0x00
375#define CPF_CURRENTPITCH_MASK 0xffff0000
376#define CPF_CURRENTPITCH 0x10100000
377#define CPF_STEREO_MASK 0x00008000
378#define CPF_STOP_MASK 0x00004000
379#define CPF_FRACADDRESS_MASK 0x00003fff
380
381#define PTRX 0x01
382#define PTRX_PITCHTARGET_MASK 0xffff0000
383#define PTRX_PITCHTARGET 0x10100001
384#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00
385#define PTRX_FXSENDAMOUNT_A 0x08080001
386#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff
387#define PTRX_FXSENDAMOUNT_B 0x08000001
388
389#define CVCF 0x02
390#define CVCF_CURRENTVOL_MASK 0xffff0000
391#define CVCF_CURRENTVOL 0x10100002
392#define CVCF_CURRENTFILTER_MASK 0x0000ffff
393#define CVCF_CURRENTFILTER 0x10000002
394
395#define VTFT 0x03
396#define VTFT_VOLUMETARGET_MASK 0xffff0000
397#define VTFT_VOLUMETARGET 0x10100003
398#define VTFT_FILTERTARGET_MASK 0x0000ffff
399#define VTFT_FILTERTARGET 0x10000003
400
401#define Z1 0x05
402
403#define Z2 0x04
404
405#define PSST 0x06
406#define PSST_FXSENDAMOUNT_C_MASK 0xff000000
407
408#define PSST_FXSENDAMOUNT_C 0x08180006
409
410#define PSST_LOOPSTARTADDR_MASK 0x00ffffff
411#define PSST_LOOPSTARTADDR 0x18000006
412
413#define DSL 0x07
414#define DSL_FXSENDAMOUNT_D_MASK 0xff000000
415
416#define DSL_FXSENDAMOUNT_D 0x08180007
417
418#define DSL_LOOPENDADDR_MASK 0x00ffffff
419#define DSL_LOOPENDADDR 0x18000007
420
421#define CCCA 0x08
422#define CCCA_RESONANCE 0xf0000000
423#define CCCA_INTERPROMMASK 0x0e000000
424
425
426
427
428
429#define CCCA_INTERPROM_0 0x00000000
430#define CCCA_INTERPROM_1 0x02000000
431#define CCCA_INTERPROM_2 0x04000000
432#define CCCA_INTERPROM_3 0x06000000
433#define CCCA_INTERPROM_4 0x08000000
434#define CCCA_INTERPROM_5 0x0a000000
435#define CCCA_INTERPROM_6 0x0c000000
436#define CCCA_INTERPROM_7 0x0e000000
437#define CCCA_8BITSELECT 0x01000000
438#define CCCA_CURRADDR_MASK 0x00ffffff
439#define CCCA_CURRADDR 0x18000008
440
441
442#undef CCR
443#define CCR 0x09
444#define CCR_CACHEINVALIDSIZE 0x07190009
445#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000
446#define CCR_CACHELOOPFLAG 0x01000000
447#define CCR_INTERLEAVEDSAMPLES 0x00800000
448#define CCR_WORDSIZEDSAMPLES 0x00400000
449#define CCR_READADDRESS 0x06100009
450#define CCR_READADDRESS_MASK 0x003f0000
451#define CCR_LOOPINVALSIZE 0x0000fe00
452
453#define CCR_LOOPFLAG 0x00000100
454#define CCR_CACHELOOPADDRHI 0x000000ff
455
456#define CLP 0x0a
457
458#define CLP_CACHELOOPADDR 0x0000ffff
459
460#define FXRT 0x0b
461
462
463#define FXRT_CHANNELA 0x000f0000
464#define FXRT_CHANNELB 0x00f00000
465#define FXRT_CHANNELC 0x0f000000
466#define FXRT_CHANNELD 0xf0000000
467
468#define A_HR 0x0b
469#define MAPA 0x0c
470
471#define MAPB 0x0d
472
473#define MAP_PTE_MASK 0xffffe000
474#define MAP_PTI_MASK 0x00001fff
475
476
477
478#define ENVVOL 0x10
479#define ENVVOL_MASK 0x0000ffff
480
481
482#define ATKHLDV 0x11
483#define ATKHLDV_PHASE0 0x00008000
484#define ATKHLDV_HOLDTIME_MASK 0x00007f00
485#define ATKHLDV_ATTACKTIME_MASK 0x0000007f
486
487
488#define DCYSUSV 0x12
489#define DCYSUSV_PHASE1_MASK 0x00008000
490#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00
491#define DCYSUSV_CHANNELENABLE_MASK 0x00000080
492
493
494#define DCYSUSV_DECAYTIME_MASK 0x0000007f
495
496
497#define LFOVAL1 0x13
498#define LFOVAL_MASK 0x0000ffff
499
500
501#define ENVVAL 0x14
502#define ENVVAL_MASK 0x0000ffff
503
504
505#define ATKHLDM 0x15
506#define ATKHLDM_PHASE0 0x00008000
507#define ATKHLDM_HOLDTIME 0x00007f00
508#define ATKHLDM_ATTACKTIME 0x0000007f
509
510
511#define DCYSUSM 0x16
512#define DCYSUSM_PHASE1_MASK 0x00008000
513#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00
514#define DCYSUSM_DECAYTIME_MASK 0x0000007f
515
516
517#define LFOVAL2 0x17
518#define LFOVAL2_MASK 0x0000ffff
519
520
521#define IP 0x18
522#define IP_MASK 0x0000ffff
523
524#define IP_UNITY 0x0000e000
525
526#define IFATN 0x19
527#define IFATN_FILTERCUTOFF_MASK 0x0000ff00
528
529
530#define IFATN_FILTERCUTOFF 0x08080019
531#define IFATN_ATTENUATION_MASK 0x000000ff
532#define IFATN_ATTENUATION 0x08000019
533
534
535#define PEFE 0x1a
536#define PEFE_PITCHAMOUNT_MASK 0x0000ff00
537
538#define PEFE_PITCHAMOUNT 0x0808001a
539#define PEFE_FILTERAMOUNT_MASK 0x000000ff
540
541#define PEFE_FILTERAMOUNT 0x0800001a
542#define FMMOD 0x1b
543#define FMMOD_MODVIBRATO 0x0000ff00
544
545#define FMMOD_MOFILTER 0x000000ff
546
547
548
549#define TREMFRQ 0x1c
550#define TREMFRQ_DEPTH 0x0000ff00
551
552
553#define TREMFRQ_FREQUENCY 0x000000ff
554
555#define FM2FRQ2 0x1d
556#define FM2FRQ2_DEPTH 0x0000ff00
557
558#define FM2FRQ2_FREQUENCY 0x000000ff
559
560
561#define TEMPENV 0x1e
562#define TEMPENV_MASK 0x0000ffff
563
564
565
566
567
568#define CD0 0x20
569#define CD1 0x21
570#define CD2 0x22
571#define CD3 0x23
572#define CD4 0x24
573#define CD5 0x25
574#define CD6 0x26
575#define CD7 0x27
576#define CD8 0x28
577#define CD9 0x29
578#define CDA 0x2a
579#define CDB 0x2b
580#define CDC 0x2c
581#define CDD 0x2d
582#define CDE 0x2e
583#define CDF 0x2f
584
585
586
587#define PTB 0x40
588#define PTB_MASK 0xfffff000
589
590#define TCB 0x41
591#define TCB_MASK 0xfffff000
592
593#define ADCCR 0x42
594#define ADCCR_RCHANENABLE 0x00000010
595#define ADCCR_LCHANENABLE 0x00000008
596
597
598#define A_ADCCR_RCHANENABLE 0x00000020
599#define A_ADCCR_LCHANENABLE 0x00000010
600
601#define A_ADCCR_SAMPLERATE_MASK 0x0000000F
602#define ADCCR_SAMPLERATE_MASK 0x00000007
603#define ADCCR_SAMPLERATE_48 0x00000000
604#define ADCCR_SAMPLERATE_44 0x00000001
605#define ADCCR_SAMPLERATE_32 0x00000002
606#define ADCCR_SAMPLERATE_24 0x00000003
607#define ADCCR_SAMPLERATE_22 0x00000004
608#define ADCCR_SAMPLERATE_16 0x00000005
609#define ADCCR_SAMPLERATE_11 0x00000006
610#define ADCCR_SAMPLERATE_8 0x00000007
611#define A_ADCCR_SAMPLERATE_12 0x00000006
612#define A_ADCCR_SAMPLERATE_11 0x00000007
613#define A_ADCCR_SAMPLERATE_8 0x00000008
614
615#define FXWC 0x43
616
617
618
619
620
621
622#define FXWC_DEFAULTROUTE_C (1<<0)
623#define FXWC_DEFAULTROUTE_B (1<<1)
624#define FXWC_DEFAULTROUTE_A (1<<12)
625#define FXWC_DEFAULTROUTE_D (1<<13)
626#define FXWC_ADCLEFT (1<<18)
627#define FXWC_CDROMSPDIFLEFT (1<<18)
628#define FXWC_ADCRIGHT (1<<19)
629#define FXWC_CDROMSPDIFRIGHT (1<<19)
630#define FXWC_MIC (1<<20)
631#define FXWC_ZOOMLEFT (1<<20)
632#define FXWC_ZOOMRIGHT (1<<21)
633#define FXWC_SPDIFLEFT (1<<22)
634#define FXWC_SPDIFRIGHT (1<<23)
635
636#define A_TBLSZ 0x43
637
638#define TCBS 0x44
639#define TCBS_MASK 0x00000007
640#define TCBS_BUFFSIZE_16K 0x00000000
641#define TCBS_BUFFSIZE_32K 0x00000001
642#define TCBS_BUFFSIZE_64K 0x00000002
643#define TCBS_BUFFSIZE_128K 0x00000003
644#define TCBS_BUFFSIZE_256K 0x00000004
645#define TCBS_BUFFSIZE_512K 0x00000005
646#define TCBS_BUFFSIZE_1024K 0x00000006
647#define TCBS_BUFFSIZE_2048K 0x00000007
648
649#define MICBA 0x45
650#define MICBA_MASK 0xfffff000
651
652#define ADCBA 0x46
653#define ADCBA_MASK 0xfffff000
654
655#define FXBA 0x47
656#define FXBA_MASK 0xfffff000
657
658#define A_HWM 0x48
659
660#define MICBS 0x49
661
662#define ADCBS 0x4a
663
664#define FXBS 0x4b
665
666
667
668
669#define ADCBS_BUFSIZE_NONE 0x00000000
670#define ADCBS_BUFSIZE_384 0x00000001
671#define ADCBS_BUFSIZE_448 0x00000002
672#define ADCBS_BUFSIZE_512 0x00000003
673#define ADCBS_BUFSIZE_640 0x00000004
674#define ADCBS_BUFSIZE_768 0x00000005
675#define ADCBS_BUFSIZE_896 0x00000006
676#define ADCBS_BUFSIZE_1024 0x00000007
677#define ADCBS_BUFSIZE_1280 0x00000008
678#define ADCBS_BUFSIZE_1536 0x00000009
679#define ADCBS_BUFSIZE_1792 0x0000000a
680#define ADCBS_BUFSIZE_2048 0x0000000b
681#define ADCBS_BUFSIZE_2560 0x0000000c
682#define ADCBS_BUFSIZE_3072 0x0000000d
683#define ADCBS_BUFSIZE_3584 0x0000000e
684#define ADCBS_BUFSIZE_4096 0x0000000f
685#define ADCBS_BUFSIZE_5120 0x00000010
686#define ADCBS_BUFSIZE_6144 0x00000011
687#define ADCBS_BUFSIZE_7168 0x00000012
688#define ADCBS_BUFSIZE_8192 0x00000013
689#define ADCBS_BUFSIZE_10240 0x00000014
690#define ADCBS_BUFSIZE_12288 0x00000015
691#define ADCBS_BUFSIZE_14366 0x00000016
692#define ADCBS_BUFSIZE_16384 0x00000017
693#define ADCBS_BUFSIZE_20480 0x00000018
694#define ADCBS_BUFSIZE_24576 0x00000019
695#define ADCBS_BUFSIZE_28672 0x0000001a
696#define ADCBS_BUFSIZE_32768 0x0000001b
697#define ADCBS_BUFSIZE_40960 0x0000001c
698#define ADCBS_BUFSIZE_49152 0x0000001d
699#define ADCBS_BUFSIZE_57344 0x0000001e
700#define ADCBS_BUFSIZE_65536 0x0000001f
701
702
703#define A_CSBA 0x4c
704
705
706#define A_CSDC 0x4d
707
708
709#define A_CSFE 0x4e
710
711
712#define A_CSHG 0x4f
713
714
715#define CDCS 0x50
716
717#define GPSCS 0x51
718
719#define DBG 0x52
720
721
722#define A_SPSC 0x52
723
724#define REG53 0x53
725
726#define A_DBG 0x53
727#define A_DBG_SINGLE_STEP 0x00020000
728#define A_DBG_ZC 0x40000000
729#define A_DBG_STEP_ADDR 0x000003ff
730#define A_DBG_SATURATION_OCCURED 0x20000000
731#define A_DBG_SATURATION_ADDR 0x0ffc0000
732
733
734#define SPCS0 0x54
735
736#define SPCS1 0x55
737
738#define SPCS2 0x56
739
740#define SPCS_CLKACCYMASK 0x30000000
741#define SPCS_CLKACCY_1000PPM 0x00000000
742#define SPCS_CLKACCY_50PPM 0x10000000
743#define SPCS_CLKACCY_VARIABLE 0x20000000
744#define SPCS_SAMPLERATEMASK 0x0f000000
745#define SPCS_SAMPLERATE_44 0x00000000
746#define SPCS_SAMPLERATE_48 0x02000000
747#define SPCS_SAMPLERATE_32 0x03000000
748#define SPCS_CHANNELNUMMASK 0x00f00000
749#define SPCS_CHANNELNUM_UNSPEC 0x00000000
750#define SPCS_CHANNELNUM_LEFT 0x00100000
751#define SPCS_CHANNELNUM_RIGHT 0x00200000
752#define SPCS_SOURCENUMMASK 0x000f0000
753#define SPCS_SOURCENUM_UNSPEC 0x00000000
754#define SPCS_GENERATIONSTATUS 0x00008000
755#define SPCS_CATEGORYCODEMASK 0x00007f00
756#define SPCS_MODEMASK 0x000000c0
757#define SPCS_EMPHASISMASK 0x00000038
758#define SPCS_EMPHASIS_NONE 0x00000000
759#define SPCS_EMPHASIS_50_15 0x00000008
760#define SPCS_COPYRIGHT 0x00000004
761#define SPCS_NOTAUDIODATA 0x00000002
762#define SPCS_PROFESSIONAL 0x00000001
763
764
765
766
767#define CLIEL 0x58
768
769#define CLIEH 0x59
770
771#define CLIPL 0x5a
772
773#define CLIPH 0x5b
774
775#define SOLEL 0x5c
776
777#define SOLEH 0x5d
778
779#define SPBYPASS 0x5e
780#define SPBYPASS_SPDIF0_MASK 0x00000003
781#define SPBYPASS_SPDIF1_MASK 0x0000000c
782
783#define SPBYPASS_FORMAT 0x00000f00
784
785#define AC97SLOT 0x5f
786#define AC97SLOT_REAR_RIGHT 0x01
787#define AC97SLOT_REAR_LEFT 0x02
788#define AC97SLOT_CNTR 0x10
789#define AC97SLOT_LFE 0x20
790
791
792#define A_PCB 0x5f
793
794
795#define CDSRCS 0x60
796
797#define GPSRCS 0x61
798
799#define ZVSRCS 0x62
800
801
802
803
804#define SRCS_SPDIFVALID 0x04000000
805#define SRCS_SPDIFLOCKED 0x02000000
806#define SRCS_RATELOCKED 0x01000000
807#define SRCS_ESTSAMPLERATE 0x0007ffff
808
809
810#define SRCS_SPDIFRATE_44 0x0003acd9
811#define SRCS_SPDIFRATE_48 0x00040000
812#define SRCS_SPDIFRATE_96 0x00080000
813
814#define MICIDX 0x63
815#define MICIDX_MASK 0x0000ffff
816#define MICIDX_IDX 0x10000063
817
818#define ADCIDX 0x64
819#define ADCIDX_MASK 0x0000ffff
820#define ADCIDX_IDX 0x10000064
821
822#define A_ADCIDX 0x63
823#define A_ADCIDX_IDX 0x10000063
824
825#define A_MICIDX 0x64
826#define A_MICIDX_IDX 0x10000064
827
828#define FXIDX 0x65
829#define FXIDX_MASK 0x0000ffff
830#define FXIDX_IDX 0x10000065
831
832
833#define HLIEL 0x66
834
835#define HLIEH 0x67
836
837#define HLIPL 0x68
838
839#define HLIPH 0x69
840
841
842#define A_SPRI 0x6a
843
844#define A_SPRA 0x6b
845
846#define A_SPRC 0x6c
847
848#define A_DICE 0x6d
849
850#define A_TTB 0x6e
851
852#define A_TDOF 0x6f
853
854
855#define A_MUDATA1 0x70
856#define A_MUCMD1 0x71
857#define A_MUSTAT1 A_MUCMD1
858
859
860#define A_MUDATA2 0x72
861#define A_MUCMD2 0x73
862#define A_MUSTAT2 A_MUCMD2
863
864
865
866
867#define A_FXWC1 0x74
868#define A_FXWC2 0x75
869
870
871#define A_SPDIF_SAMPLERATE 0x76
872#define A_SAMPLE_RATE 0x76
873#define A_SAMPLE_RATE_NOT_USED 0x0ffc111e
874#define A_SAMPLE_RATE_UNKNOWN 0xf0030001
875#define A_SPDIF_RATE_MASK 0x000000e0
876#define A_SPDIF_48000 0x00000000
877#define A_SPDIF_192000 0x00000020
878#define A_SPDIF_96000 0x00000040
879#define A_SPDIF_44100 0x00000080
880
881#define A_I2S_CAPTURE_RATE_MASK 0x00000e00
882#define A_I2S_CAPTURE_48000 0x00000000
883#define A_I2S_CAPTURE_192000 0x00000200
884#define A_I2S_CAPTURE_96000 0x00000400
885#define A_I2S_CAPTURE_44100 0x00000800
886
887#define A_PCM_RATE_MASK 0x0000e000
888#define A_PCM_48000 0x00000000
889#define A_PCM_192000 0x00002000
890#define A_PCM_96000 0x00004000
891#define A_PCM_44100 0x00008000
892
893
894#define A_SRT3 0x77
895
896
897#define A_SRT4 0x78
898
899
900#define A_SRT5 0x79
901
902
903
904#define A_TTDA 0x7a
905
906#define A_TTDD 0x7b
907
908#define A_FXRT2 0x7c
909#define A_FXRT_CHANNELE 0x0000003f
910#define A_FXRT_CHANNELF 0x00003f00
911#define A_FXRT_CHANNELG 0x003f0000
912#define A_FXRT_CHANNELH 0x3f000000
913
914#define A_SENDAMOUNTS 0x7d
915#define A_FXSENDAMOUNT_E_MASK 0xFF000000
916#define A_FXSENDAMOUNT_F_MASK 0x00FF0000
917#define A_FXSENDAMOUNT_G_MASK 0x0000FF00
918#define A_FXSENDAMOUNT_H_MASK 0x000000FF
919
920
921
922#define A_FXRT1 0x7e
923#define A_FXRT_CHANNELA 0x0000003f
924#define A_FXRT_CHANNELB 0x00003f00
925#define A_FXRT_CHANNELC 0x003f0000
926#define A_FXRT_CHANNELD 0x3f000000
927
928
929
930#define FXGPREGBASE 0x100
931#define A_FXGPREGBASE 0x400
932
933#define A_TANKMEMCTLREGBASE 0x100
934#define A_TANKMEMCTLREG_MASK 0x1f
935
936
937
938
939#define TANKMEMDATAREGBASE 0x200
940#define TANKMEMDATAREG_MASK 0x000fffff
941
942
943#define TANKMEMADDRREGBASE 0x300
944#define TANKMEMADDRREG_ADDR_MASK 0x000fffff
945#define TANKMEMADDRREG_CLEAR 0x00800000
946#define TANKMEMADDRREG_ALIGN 0x00400000
947#define TANKMEMADDRREG_WRITE 0x00200000
948#define TANKMEMADDRREG_READ 0x00100000
949
950#define MICROCODEBASE 0x400
951
952
953
954#define LOWORD_OPX_MASK 0x000ffc00
955#define LOWORD_OPY_MASK 0x000003ff
956#define HIWORD_OPCODE_MASK 0x00f00000
957#define HIWORD_RESULT_MASK 0x000ffc00
958#define HIWORD_OPA_MASK 0x000003ff
959
960
961
962#define A_MICROCODEBASE 0x600
963#define A_LOWORD_OPY_MASK 0x000007ff
964#define A_LOWORD_OPX_MASK 0x007ff000
965#define A_HIWORD_OPCODE_MASK 0x0f000000
966#define A_HIWORD_RESULT_MASK 0x007ff000
967#define A_HIWORD_OPA_MASK 0x000007ff
968
969
970
971
972#define EMU_HANA_DESTHI 0x00
973#define EMU_HANA_DESTLO 0x01
974#define EMU_HANA_SRCHI 0x02
975#define EMU_HANA_SRCLO 0x03
976#define EMU_HANA_DOCK_PWR 0x04
977#define EMU_HANA_DOCK_PWR_ON 0x01
978#define EMU_HANA_WCLOCK 0x05
979
980
981#define EMU_HANA_WCLOCK_SRC_MASK 0x07
982#define EMU_HANA_WCLOCK_INT_48K 0x00
983#define EMU_HANA_WCLOCK_INT_44_1K 0x01
984#define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02
985#define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03
986#define EMU_HANA_WCLOCK_SYNC_BNCN 0x04
987#define EMU_HANA_WCLOCK_2ND_HANA 0x05
988#define EMU_HANA_WCLOCK_SRC_RESERVED 0x06
989#define EMU_HANA_WCLOCK_OFF 0x07
990#define EMU_HANA_WCLOCK_MULT_MASK 0x18
991#define EMU_HANA_WCLOCK_1X 0x00
992#define EMU_HANA_WCLOCK_2X 0x08
993#define EMU_HANA_WCLOCK_4X 0x10
994#define EMU_HANA_WCLOCK_MULT_RESERVED 0x18
995
996#define EMU_HANA_DEFCLOCK 0x06
997#define EMU_HANA_DEFCLOCK_48K 0x00
998#define EMU_HANA_DEFCLOCK_44_1K 0x01
999
1000#define EMU_HANA_UNMUTE 0x07
1001#define EMU_MUTE 0x00
1002#define EMU_UNMUTE 0x01
1003
1004#define EMU_HANA_FPGA_CONFIG 0x08
1005#define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01
1006#define EMU_HANA_FPGA_CONFIG_HANA 0x02
1007
1008#define EMU_HANA_IRQ_ENABLE 0x09
1009#define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1010#define EMU_HANA_IRQ_ADAT 0x02
1011#define EMU_HANA_IRQ_DOCK 0x04
1012#define EMU_HANA_IRQ_DOCK_LOST 0x08
1013
1014#define EMU_HANA_SPDIF_MODE 0x0a
1015#define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x00
1016#define EMU_HANA_SPDIF_MODE_TX_PRO 0x01
1017#define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02
1018#define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x00
1019#define EMU_HANA_SPDIF_MODE_RX_PRO 0x04
1020#define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08
1021#define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10
1022
1023#define EMU_HANA_OPTICAL_TYPE 0x0b
1024#define EMU_HANA_OPTICAL_IN_SPDIF 0x00
1025#define EMU_HANA_OPTICAL_IN_ADAT 0x01
1026#define EMU_HANA_OPTICAL_OUT_SPDIF 0x00
1027#define EMU_HANA_OPTICAL_OUT_ADAT 0x02
1028
1029#define EMU_HANA_MIDI_IN 0x0c
1030#define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00
1031#define EMU_HANA_MIDI_IN_FROM_DOCK 0x01
1032
1033#define EMU_HANA_DOCK_LEDS_1 0x0d
1034#define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01
1035#define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02
1036#define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04
1037#define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08
1038
1039#define EMU_HANA_DOCK_LEDS_2 0x0e
1040#define EMU_HANA_DOCK_LEDS_2_44K 0x01
1041#define EMU_HANA_DOCK_LEDS_2_48K 0x02
1042#define EMU_HANA_DOCK_LEDS_2_96K 0x04
1043#define EMU_HANA_DOCK_LEDS_2_192K 0x08
1044#define EMU_HANA_DOCK_LEDS_2_LOCK 0x10
1045#define EMU_HANA_DOCK_LEDS_2_EXT 0x20
1046
1047#define EMU_HANA_DOCK_LEDS_3 0x0f
1048#define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01
1049#define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02
1050#define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04
1051#define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08
1052#define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10
1053#define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20
1054
1055#define EMU_HANA_ADC_PADS 0x10
1056#define EMU_HANA_DOCK_ADC_PAD1 0x01
1057#define EMU_HANA_DOCK_ADC_PAD2 0x02
1058#define EMU_HANA_DOCK_ADC_PAD3 0x04
1059#define EMU_HANA_0202_ADC_PAD1 0x08
1060
1061#define EMU_HANA_DOCK_MISC 0x11
1062#define EMU_HANA_DOCK_DAC1_MUTE 0x01
1063#define EMU_HANA_DOCK_DAC2_MUTE 0x02
1064#define EMU_HANA_DOCK_DAC3_MUTE 0x04
1065#define EMU_HANA_DOCK_DAC4_MUTE 0x08
1066#define EMU_HANA_DOCK_PHONES_192_DAC1 0x00
1067#define EMU_HANA_DOCK_PHONES_192_DAC2 0x10
1068#define EMU_HANA_DOCK_PHONES_192_DAC3 0x20
1069#define EMU_HANA_DOCK_PHONES_192_DAC4 0x30
1070
1071#define EMU_HANA_MIDI_OUT 0x12
1072#define EMU_HANA_MIDI_OUT_0202 0x01
1073#define EMU_HANA_MIDI_OUT_DOCK1 0x02
1074#define EMU_HANA_MIDI_OUT_DOCK2 0x04
1075#define EMU_HANA_MIDI_OUT_SYNC2 0x08
1076#define EMU_HANA_MIDI_OUT_LOOP 0x10
1077
1078#define EMU_HANA_DAC_PADS 0x13
1079#define EMU_HANA_DOCK_DAC_PAD1 0x01
1080#define EMU_HANA_DOCK_DAC_PAD2 0x02
1081#define EMU_HANA_DOCK_DAC_PAD3 0x04
1082#define EMU_HANA_DOCK_DAC_PAD4 0x08
1083#define EMU_HANA_0202_DAC_PAD1 0x10
1084
1085
1086#define EMU_HANA_IRQ_STATUS 0x20
1087#if 0
1088#define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1089#define EMU_HANA_IRQ_ADAT 0x02
1090#define EMU_HANA_IRQ_DOCK 0x04
1091#define EMU_HANA_IRQ_DOCK_LOST 0x08
1092#endif
1093
1094#define EMU_HANA_OPTION_CARDS 0x21
1095#define EMU_HANA_OPTION_HAMOA 0x01
1096#define EMU_HANA_OPTION_SYNC 0x02
1097#define EMU_HANA_OPTION_DOCK_ONLINE 0x04
1098#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08
1099
1100#define EMU_HANA_ID 0x22
1101
1102#define EMU_HANA_MAJOR_REV 0x23
1103#define EMU_HANA_MINOR_REV 0x24
1104
1105#define EMU_DOCK_MAJOR_REV 0x25
1106#define EMU_DOCK_MINOR_REV 0x26
1107
1108#define EMU_DOCK_BOARD_ID 0x27
1109#define EMU_DOCK_BOARD_ID0 0x00
1110#define EMU_DOCK_BOARD_ID1 0x03
1111
1112#define EMU_HANA_WC_SPDIF_HI 0x28
1113#define EMU_HANA_WC_SPDIF_LO 0x29
1114
1115#define EMU_HANA_WC_ADAT_HI 0x2a
1116#define EMU_HANA_WC_ADAT_LO 0x2b
1117
1118#define EMU_HANA_WC_BNC_LO 0x2c
1119#define EMU_HANA_WC_BNC_HI 0x2d
1120
1121#define EMU_HANA2_WC_SPDIF_HI 0x2e
1122#define EMU_HANA2_WC_SPDIF_LO 0x2f
1123
1124
1125
1126
1127
1128
1129
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1230
1231#define EMU_DST_ALICE2_EMU32_0 0x000f
1232#define EMU_DST_ALICE2_EMU32_1 0x0000
1233#define EMU_DST_ALICE2_EMU32_2 0x0001
1234#define EMU_DST_ALICE2_EMU32_3 0x0002
1235#define EMU_DST_ALICE2_EMU32_4 0x0003
1236#define EMU_DST_ALICE2_EMU32_5 0x0004
1237#define EMU_DST_ALICE2_EMU32_6 0x0005
1238#define EMU_DST_ALICE2_EMU32_7 0x0006
1239#define EMU_DST_ALICE2_EMU32_8 0x0007
1240#define EMU_DST_ALICE2_EMU32_9 0x0008
1241#define EMU_DST_ALICE2_EMU32_A 0x0009
1242#define EMU_DST_ALICE2_EMU32_B 0x000a
1243#define EMU_DST_ALICE2_EMU32_C 0x000b
1244#define EMU_DST_ALICE2_EMU32_D 0x000c
1245#define EMU_DST_ALICE2_EMU32_E 0x000d
1246#define EMU_DST_ALICE2_EMU32_F 0x000e
1247#define EMU_DST_DOCK_DAC1_LEFT1 0x0100
1248#define EMU_DST_DOCK_DAC1_LEFT2 0x0101
1249#define EMU_DST_DOCK_DAC1_LEFT3 0x0102
1250#define EMU_DST_DOCK_DAC1_LEFT4 0x0103
1251#define EMU_DST_DOCK_DAC1_RIGHT1 0x0104
1252#define EMU_DST_DOCK_DAC1_RIGHT2 0x0105
1253#define EMU_DST_DOCK_DAC1_RIGHT3 0x0106
1254#define EMU_DST_DOCK_DAC1_RIGHT4 0x0107
1255#define EMU_DST_DOCK_DAC2_LEFT1 0x0108
1256#define EMU_DST_DOCK_DAC2_LEFT2 0x0109
1257#define EMU_DST_DOCK_DAC2_LEFT3 0x010a
1258#define EMU_DST_DOCK_DAC2_LEFT4 0x010b
1259#define EMU_DST_DOCK_DAC2_RIGHT1 0x010c
1260#define EMU_DST_DOCK_DAC2_RIGHT2 0x010d
1261#define EMU_DST_DOCK_DAC2_RIGHT3 0x010e
1262#define EMU_DST_DOCK_DAC2_RIGHT4 0x010f
1263#define EMU_DST_DOCK_DAC3_LEFT1 0x0110
1264#define EMU_DST_DOCK_DAC3_LEFT2 0x0111
1265#define EMU_DST_DOCK_DAC3_LEFT3 0x0112
1266#define EMU_DST_DOCK_DAC3_LEFT4 0x0113
1267#define EMU_DST_DOCK_PHONES_LEFT1 0x0112
1268#define EMU_DST_DOCK_PHONES_LEFT2 0x0113
1269#define EMU_DST_DOCK_DAC3_RIGHT1 0x0114
1270#define EMU_DST_DOCK_DAC3_RIGHT2 0x0115
1271#define EMU_DST_DOCK_DAC3_RIGHT3 0x0116
1272#define EMU_DST_DOCK_DAC3_RIGHT4 0x0117
1273#define EMU_DST_DOCK_PHONES_RIGHT1 0x0116
1274#define EMU_DST_DOCK_PHONES_RIGHT2 0x0117
1275#define EMU_DST_DOCK_DAC4_LEFT1 0x0118
1276#define EMU_DST_DOCK_DAC4_LEFT2 0x0119
1277#define EMU_DST_DOCK_DAC4_LEFT3 0x011a
1278#define EMU_DST_DOCK_DAC4_LEFT4 0x011b
1279#define EMU_DST_DOCK_SPDIF_LEFT1 0x011a
1280#define EMU_DST_DOCK_SPDIF_LEFT2 0x011b
1281#define EMU_DST_DOCK_DAC4_RIGHT1 0x011c
1282#define EMU_DST_DOCK_DAC4_RIGHT2 0x011d
1283#define EMU_DST_DOCK_DAC4_RIGHT3 0x011e
1284#define EMU_DST_DOCK_DAC4_RIGHT4 0x011f
1285#define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e
1286#define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f
1287#define EMU_DST_HANA_SPDIF_LEFT1 0x0200
1288#define EMU_DST_HANA_SPDIF_LEFT2 0x0202
1289#define EMU_DST_HANA_SPDIF_RIGHT1 0x0201
1290#define EMU_DST_HANA_SPDIF_RIGHT2 0x0203
1291#define EMU_DST_HAMOA_DAC_LEFT1 0x0300
1292#define EMU_DST_HAMOA_DAC_LEFT2 0x0302
1293#define EMU_DST_HAMOA_DAC_LEFT3 0x0304
1294#define EMU_DST_HAMOA_DAC_LEFT4 0x0306
1295#define EMU_DST_HAMOA_DAC_RIGHT1 0x0301
1296#define EMU_DST_HAMOA_DAC_RIGHT2 0x0303
1297#define EMU_DST_HAMOA_DAC_RIGHT3 0x0305
1298#define EMU_DST_HAMOA_DAC_RIGHT4 0x0307
1299#define EMU_DST_HANA_ADAT 0x0400
1300#define EMU_DST_ALICE_I2S0_LEFT 0x0500
1301#define EMU_DST_ALICE_I2S0_RIGHT 0x0501
1302#define EMU_DST_ALICE_I2S1_LEFT 0x0600
1303#define EMU_DST_ALICE_I2S1_RIGHT 0x0601
1304#define EMU_DST_ALICE_I2S2_LEFT 0x0700
1305#define EMU_DST_ALICE_I2S2_RIGHT 0x0701
1306
1307
1308
1309#define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112
1310
1311#define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113
1312
1313#define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116
1314
1315#define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117
1316
1317#define EMU_DST_MDOCK_ADAT 0x0118
1318
1319
1320#define EMU_DST_MANA_DAC_LEFT 0x0300
1321
1322#define EMU_DST_MANA_DAC_RIGHT 0x0301
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1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429#define EMU_SRC_SILENCE 0x0000
1430#define EMU_SRC_DOCK_MIC_A1 0x0100
1431#define EMU_SRC_DOCK_MIC_A2 0x0101
1432#define EMU_SRC_DOCK_MIC_A3 0x0102
1433#define EMU_SRC_DOCK_MIC_A4 0x0103
1434#define EMU_SRC_DOCK_MIC_B1 0x0104
1435#define EMU_SRC_DOCK_MIC_B2 0x0105
1436#define EMU_SRC_DOCK_MIC_B3 0x0106
1437#define EMU_SRC_DOCK_MIC_B4 0x0107
1438#define EMU_SRC_DOCK_ADC1_LEFT1 0x0108
1439#define EMU_SRC_DOCK_ADC1_LEFT2 0x0109
1440#define EMU_SRC_DOCK_ADC1_LEFT3 0x010a
1441#define EMU_SRC_DOCK_ADC1_LEFT4 0x010b
1442#define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c
1443#define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d
1444#define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e
1445#define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f
1446#define EMU_SRC_DOCK_ADC2_LEFT1 0x0110
1447#define EMU_SRC_DOCK_ADC2_LEFT2 0x0111
1448#define EMU_SRC_DOCK_ADC2_LEFT3 0x0112
1449#define EMU_SRC_DOCK_ADC2_LEFT4 0x0113
1450#define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114
1451#define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115
1452#define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116
1453#define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117
1454#define EMU_SRC_DOCK_ADC3_LEFT1 0x0118
1455#define EMU_SRC_DOCK_ADC3_LEFT2 0x0119
1456#define EMU_SRC_DOCK_ADC3_LEFT3 0x011a
1457#define EMU_SRC_DOCK_ADC3_LEFT4 0x011b
1458#define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c
1459#define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d
1460#define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e
1461#define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f
1462#define EMU_SRC_HAMOA_ADC_LEFT1 0x0200
1463#define EMU_SRC_HAMOA_ADC_LEFT2 0x0202
1464#define EMU_SRC_HAMOA_ADC_LEFT3 0x0204
1465#define EMU_SRC_HAMOA_ADC_LEFT4 0x0206
1466#define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201
1467#define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203
1468#define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205
1469#define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207
1470#define EMU_SRC_ALICE_EMU32A 0x0300
1471#define EMU_SRC_ALICE_EMU32B 0x0310
1472#define EMU_SRC_HANA_ADAT 0x0400
1473#define EMU_SRC_HANA_SPDIF_LEFT1 0x0500
1474#define EMU_SRC_HANA_SPDIF_LEFT2 0x0502
1475#define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501
1476#define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503
1477
1478
1479
1480#define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112
1481
1482#define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113
1483
1484#define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116
1485
1486#define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117
1487
1488#define EMU_SRC_MDOCK_ADAT 0x0118
1489
1490
1491
1492
1493
1494enum {
1495 EMU10K1_EFX,
1496 EMU10K1_PCM,
1497 EMU10K1_SYNTH,
1498 EMU10K1_MIDI
1499};
1500
1501struct snd_emu10k1;
1502
1503struct snd_emu10k1_voice {
1504 struct snd_emu10k1 *emu;
1505 int number;
1506 unsigned int use: 1,
1507 pcm: 1,
1508 efx: 1,
1509 synth: 1,
1510 midi: 1;
1511 void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1512
1513 struct snd_emu10k1_pcm *epcm;
1514};
1515
1516enum {
1517 PLAYBACK_EMUVOICE,
1518 PLAYBACK_EFX,
1519 CAPTURE_AC97ADC,
1520 CAPTURE_AC97MIC,
1521 CAPTURE_EFX
1522};
1523
1524struct snd_emu10k1_pcm {
1525 struct snd_emu10k1 *emu;
1526 int type;
1527 struct snd_pcm_substream *substream;
1528 struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK];
1529 struct snd_emu10k1_voice *extra;
1530 unsigned short running;
1531 unsigned short first_ptr;
1532 struct snd_util_memblk *memblk;
1533 unsigned int start_addr;
1534 unsigned int ccca_start_addr;
1535 unsigned int capture_ipr;
1536 unsigned int capture_inte;
1537 unsigned int capture_ba_reg;
1538 unsigned int capture_bs_reg;
1539 unsigned int capture_idx_reg;
1540 unsigned int capture_cr_val;
1541 unsigned int capture_cr_val2;
1542 unsigned int capture_bs_val;
1543 unsigned int capture_bufsize;
1544};
1545
1546struct snd_emu10k1_pcm_mixer {
1547
1548 unsigned char send_routing[3][8];
1549 unsigned char send_volume[3][8];
1550 unsigned short attn[3];
1551 struct snd_emu10k1_pcm *epcm;
1552};
1553
1554#define snd_emu10k1_compose_send_routing(route) \
1555((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
1556
1557#define snd_emu10k1_compose_audigy_fxrt1(route) \
1558((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))
1559
1560#define snd_emu10k1_compose_audigy_fxrt2(route) \
1561((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))
1562
1563struct snd_emu10k1_memblk {
1564 struct snd_util_memblk mem;
1565
1566 int first_page, last_page, pages, mapped_page;
1567 unsigned int map_locked;
1568 struct list_head mapped_link;
1569 struct list_head mapped_order_link;
1570};
1571
1572#define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
1573
1574#define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
1575
1576struct snd_emu10k1_fx8010_ctl {
1577 struct list_head list;
1578 unsigned int vcount;
1579 unsigned int count;
1580 unsigned short gpr[32];
1581 unsigned int value[32];
1582 unsigned int min;
1583 unsigned int max;
1584 unsigned int translation;
1585 struct snd_kcontrol *kcontrol;
1586};
1587
1588typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data);
1589
1590struct snd_emu10k1_fx8010_irq {
1591 struct snd_emu10k1_fx8010_irq *next;
1592 snd_fx8010_irq_handler_t *handler;
1593 unsigned short gpr_running;
1594 void *private_data;
1595};
1596
1597struct snd_emu10k1_fx8010_pcm {
1598 unsigned int valid: 1,
1599 opened: 1,
1600 active: 1;
1601 unsigned int channels;
1602 unsigned int tram_start;
1603 unsigned int buffer_size;
1604 unsigned short gpr_size;
1605 unsigned short gpr_ptr;
1606 unsigned short gpr_count;
1607 unsigned short gpr_tmpcount;
1608 unsigned short gpr_trigger;
1609 unsigned short gpr_running;
1610 unsigned char etram[32];
1611 struct snd_pcm_indirect pcm_rec;
1612 unsigned int tram_pos;
1613 unsigned int tram_shift;
1614 struct snd_emu10k1_fx8010_irq *irq;
1615};
1616
1617struct snd_emu10k1_fx8010 {
1618 unsigned short fxbus_mask;
1619 unsigned short extin_mask;
1620 unsigned short extout_mask;
1621 unsigned short pad1;
1622 unsigned int itram_size;
1623 struct snd_dma_buffer etram_pages;
1624 unsigned int dbg;
1625 unsigned char name[128];
1626 int gpr_size;
1627 int gpr_count;
1628 struct list_head gpr_ctl;
1629 struct mutex lock;
1630 struct snd_emu10k1_fx8010_pcm pcm[8];
1631 spinlock_t irq_lock;
1632 struct snd_emu10k1_fx8010_irq *irq_handlers;
1633};
1634
1635struct snd_emu10k1_midi {
1636 struct snd_emu10k1 *emu;
1637 struct snd_rawmidi *rmidi;
1638 struct snd_rawmidi_substream *substream_input;
1639 struct snd_rawmidi_substream *substream_output;
1640 unsigned int midi_mode;
1641 spinlock_t input_lock;
1642 spinlock_t output_lock;
1643 spinlock_t open_lock;
1644 int tx_enable, rx_enable;
1645 int port;
1646 int ipr_tx, ipr_rx;
1647 void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1648};
1649
1650enum {
1651 EMU_MODEL_SB,
1652 EMU_MODEL_EMU1010,
1653 EMU_MODEL_EMU1010B,
1654 EMU_MODEL_EMU1616,
1655 EMU_MODEL_EMU0404,
1656};
1657
1658struct snd_emu_chip_details {
1659 u32 vendor;
1660 u32 device;
1661 u32 subsystem;
1662 unsigned char revision;
1663 unsigned char emu10k1_chip;
1664 unsigned char emu10k2_chip;
1665 unsigned char ca0102_chip;
1666 unsigned char ca0108_chip;
1667 unsigned char ca_cardbus_chip;
1668 unsigned char ca0151_chip;
1669 unsigned char spk71;
1670 unsigned char sblive51;
1671 unsigned char spdif_bug;
1672 unsigned char ac97_chip;
1673 unsigned char ecard;
1674 unsigned char emu_model;
1675 unsigned char spi_dac;
1676 unsigned char i2c_adc;
1677 unsigned char adc_1361t;
1678 unsigned char invert_shared_spdif;
1679 const char *driver;
1680 const char *name;
1681 const char *id;
1682};
1683
1684struct snd_emu1010 {
1685 unsigned int output_source[64];
1686 unsigned int input_source[64];
1687 unsigned int adc_pads;
1688 unsigned int dac_pads;
1689 unsigned int internal_clock;
1690 unsigned int optical_in;
1691 unsigned int optical_out;
1692 struct task_struct *firmware_thread;
1693};
1694
1695struct snd_emu10k1 {
1696 int irq;
1697
1698 unsigned long port;
1699 unsigned int tos_link: 1,
1700 rear_ac97: 1,
1701 enable_ir: 1;
1702 unsigned int support_tlv :1;
1703
1704 const struct snd_emu_chip_details *card_capabilities;
1705 unsigned int audigy;
1706 unsigned int revision;
1707 unsigned int serial;
1708 unsigned short model;
1709 unsigned int card_type;
1710 unsigned int ecard_ctrl;
1711 unsigned long dma_mask;
1712 unsigned int delay_pcm_irq;
1713 int max_cache_pages;
1714 struct snd_dma_buffer silent_page;
1715 struct snd_dma_buffer ptb_pages;
1716 struct snd_dma_device p16v_dma_dev;
1717 struct snd_dma_buffer p16v_buffer;
1718
1719 struct snd_util_memhdr *memhdr;
1720 struct snd_emu10k1_memblk *reserved_page;
1721
1722 struct list_head mapped_link_head;
1723 struct list_head mapped_order_link_head;
1724 void **page_ptr_table;
1725 unsigned long *page_addr_table;
1726 spinlock_t memblk_lock;
1727
1728 unsigned int spdif_bits[3];
1729 unsigned int i2c_capture_source;
1730 u8 i2c_capture_volume[4][2];
1731
1732 struct snd_emu10k1_fx8010 fx8010;
1733 int gpr_base;
1734
1735 struct snd_ac97 *ac97;
1736
1737 struct pci_dev *pci;
1738 struct snd_card *card;
1739 struct snd_pcm *pcm;
1740 struct snd_pcm *pcm_mic;
1741 struct snd_pcm *pcm_efx;
1742 struct snd_pcm *pcm_multi;
1743 struct snd_pcm *pcm_p16v;
1744
1745 spinlock_t synth_lock;
1746 void *synth;
1747 int (*get_synth_voice)(struct snd_emu10k1 *emu);
1748
1749 spinlock_t reg_lock;
1750 spinlock_t emu_lock;
1751 spinlock_t voice_lock;
1752 spinlock_t spi_lock;
1753 spinlock_t i2c_lock;
1754
1755 struct snd_emu10k1_voice voices[NUM_G];
1756 struct snd_emu10k1_voice p16v_voices[4];
1757 struct snd_emu10k1_voice p16v_capture_voice;
1758 int p16v_device_offset;
1759 u32 p16v_capture_source;
1760 u32 p16v_capture_channel;
1761 struct snd_emu1010 emu1010;
1762 struct snd_emu10k1_pcm_mixer pcm_mixer[32];
1763 struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK];
1764 struct snd_kcontrol *ctl_send_routing;
1765 struct snd_kcontrol *ctl_send_volume;
1766 struct snd_kcontrol *ctl_attn;
1767 struct snd_kcontrol *ctl_efx_send_routing;
1768 struct snd_kcontrol *ctl_efx_send_volume;
1769 struct snd_kcontrol *ctl_efx_attn;
1770
1771 void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1772 void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1773 void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1774 void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1775 void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1776 void (*dsp_interrupt)(struct snd_emu10k1 *emu);
1777
1778 struct snd_pcm_substream *pcm_capture_substream;
1779 struct snd_pcm_substream *pcm_capture_mic_substream;
1780 struct snd_pcm_substream *pcm_capture_efx_substream;
1781 struct snd_pcm_substream *pcm_playback_efx_substream;
1782
1783 struct snd_timer *timer;
1784
1785 struct snd_emu10k1_midi midi;
1786 struct snd_emu10k1_midi midi2;
1787
1788 unsigned int efx_voices_mask[2];
1789 unsigned int next_free_voice;
1790
1791#ifdef CONFIG_PM
1792 unsigned int *saved_ptr;
1793 unsigned int *saved_gpr;
1794 unsigned int *tram_val_saved;
1795 unsigned int *tram_addr_saved;
1796 unsigned int *saved_icode;
1797 unsigned int *p16v_saved;
1798 unsigned int saved_a_iocfg, saved_hcfg;
1799#endif
1800
1801};
1802
1803int snd_emu10k1_create(struct snd_card *card,
1804 struct pci_dev *pci,
1805 unsigned short extin_mask,
1806 unsigned short extout_mask,
1807 long max_cache_bytes,
1808 int enable_ir,
1809 uint subsystem,
1810 struct snd_emu10k1 ** remu);
1811
1812int snd_emu10k1_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1813int snd_emu10k1_pcm_mic(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1814int snd_emu10k1_pcm_efx(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1815int snd_p16v_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1816int snd_p16v_free(struct snd_emu10k1 * emu);
1817int snd_p16v_mixer(struct snd_emu10k1 * emu);
1818int snd_emu10k1_pcm_multi(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1819int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1820int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device);
1821int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device);
1822int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device, struct snd_hwdep ** rhwdep);
1823
1824irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id);
1825
1826void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice);
1827int snd_emu10k1_init_efx(struct snd_emu10k1 *emu);
1828void snd_emu10k1_free_efx(struct snd_emu10k1 *emu);
1829int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size);
1830int snd_emu10k1_done(struct snd_emu10k1 * emu);
1831
1832
1833unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1834void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1835unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1836void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1837int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data);
1838int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value);
1839int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value);
1840int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value);
1841int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, u32 dst, u32 src);
1842unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc);
1843void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb);
1844void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);
1845void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1846void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1847void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1848void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1849void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1850void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1851void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1852void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1853void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait);
1854static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1855unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
1856void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data);
1857unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
1858
1859#ifdef CONFIG_PM
1860void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu);
1861void snd_emu10k1_resume_init(struct snd_emu10k1 *emu);
1862void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu);
1863int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu);
1864void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu);
1865void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu);
1866void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu);
1867int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu);
1868void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu);
1869void snd_p16v_suspend(struct snd_emu10k1 *emu);
1870void snd_p16v_resume(struct snd_emu10k1 *emu);
1871#endif
1872
1873
1874struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream);
1875int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1876struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size);
1877int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1878int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size);
1879int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size);
1880int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk);
1881
1882
1883int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice);
1884int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1885
1886
1887int snd_emu10k1_midi(struct snd_emu10k1 * emu);
1888int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu);
1889
1890
1891int snd_emu10k1_proc_init(struct snd_emu10k1 * emu);
1892
1893
1894int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
1895 snd_fx8010_irq_handler_t *handler,
1896 unsigned char gpr_running,
1897 void *private_data,
1898 struct snd_emu10k1_fx8010_irq **r_irq);
1899int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
1900 struct snd_emu10k1_fx8010_irq *irq);
1901
1902#endif
1903
1904
1905
1906
1907
1908#define EMU10K1_CARD_CREATIVE 0x00000000
1909#define EMU10K1_CARD_EMUAPS 0x00000001
1910
1911#define EMU10K1_FX8010_PCM_COUNT 8
1912
1913
1914#define iMAC0 0x00
1915#define iMAC1 0x01
1916#define iMAC2 0x02
1917#define iMAC3 0x03
1918#define iMACINT0 0x04
1919#define iMACINT1 0x05
1920#define iACC3 0x06
1921#define iMACMV 0x07
1922#define iANDXOR 0x08
1923#define iTSTNEG 0x09
1924#define iLIMITGE 0x0a
1925#define iLIMITLT 0x0b
1926#define iLOG 0x0c
1927#define iEXP 0x0d
1928#define iINTERP 0x0e
1929#define iSKIP 0x0f
1930
1931
1932#define FXBUS(x) (0x00 + (x))
1933#define EXTIN(x) (0x10 + (x))
1934#define EXTOUT(x) (0x20 + (x))
1935#define FXBUS2(x) (0x30 + (x))
1936
1937
1938#define C_00000000 0x40
1939#define C_00000001 0x41
1940#define C_00000002 0x42
1941#define C_00000003 0x43
1942#define C_00000004 0x44
1943#define C_00000008 0x45
1944#define C_00000010 0x46
1945#define C_00000020 0x47
1946#define C_00000100 0x48
1947#define C_00010000 0x49
1948#define C_00080000 0x4a
1949#define C_10000000 0x4b
1950#define C_20000000 0x4c
1951#define C_40000000 0x4d
1952#define C_80000000 0x4e
1953#define C_7fffffff 0x4f
1954#define C_ffffffff 0x50
1955#define C_fffffffe 0x51
1956#define C_c0000000 0x52
1957#define C_4f1bbcdc 0x53
1958#define C_5a7ef9db 0x54
1959#define C_00100000 0x55
1960#define GPR_ACCU 0x56
1961#define GPR_COND 0x57
1962#define GPR_NOISE0 0x58
1963#define GPR_NOISE1 0x59
1964#define GPR_IRQ 0x5a
1965#define GPR_DBAC 0x5b
1966#define GPR(x) (FXGPREGBASE + (x))
1967#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
1968#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x))
1969#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
1970#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x))
1971
1972#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
1973#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x))
1974#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
1975#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x))
1976#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x))
1977#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x))
1978
1979#define A_FXBUS(x) (0x00 + (x))
1980#define A_EXTIN(x) (0x40 + (x))
1981#define A_P16VIN(x) (0x50 + (x))
1982#define A_EXTOUT(x) (0x60 + (x))
1983#define A_FXBUS2(x) (0x80 + (x))
1984#define A_EMU32OUTH(x) (0xa0 + (x))
1985#define A_EMU32OUTL(x) (0xb0 + (x))
1986#define A3_EMU32IN(x) (0x160 + (x))
1987#define A3_EMU32OUT(x) (0x1E0 + (x))
1988#define A_GPR(x) (A_FXGPREGBASE + (x))
1989
1990
1991#define CC_REG_NORMALIZED C_00000001
1992#define CC_REG_BORROW C_00000002
1993#define CC_REG_MINUS C_00000004
1994#define CC_REG_ZERO C_00000008
1995#define CC_REG_SATURATE C_00000010
1996#define CC_REG_NONZERO C_00000100
1997
1998
1999#define FXBUS_PCM_LEFT 0x00
2000#define FXBUS_PCM_RIGHT 0x01
2001#define FXBUS_PCM_LEFT_REAR 0x02
2002#define FXBUS_PCM_RIGHT_REAR 0x03
2003#define FXBUS_MIDI_LEFT 0x04
2004#define FXBUS_MIDI_RIGHT 0x05
2005#define FXBUS_PCM_CENTER 0x06
2006#define FXBUS_PCM_LFE 0x07
2007#define FXBUS_PCM_LEFT_FRONT 0x08
2008#define FXBUS_PCM_RIGHT_FRONT 0x09
2009#define FXBUS_MIDI_REVERB 0x0c
2010#define FXBUS_MIDI_CHORUS 0x0d
2011#define FXBUS_PCM_LEFT_SIDE 0x0e
2012#define FXBUS_PCM_RIGHT_SIDE 0x0f
2013#define FXBUS_PT_LEFT 0x14
2014#define FXBUS_PT_RIGHT 0x15
2015
2016
2017#define EXTIN_AC97_L 0x00
2018#define EXTIN_AC97_R 0x01
2019#define EXTIN_SPDIF_CD_L 0x02
2020#define EXTIN_SPDIF_CD_R 0x03
2021#define EXTIN_ZOOM_L 0x04
2022#define EXTIN_ZOOM_R 0x05
2023#define EXTIN_TOSLINK_L 0x06
2024#define EXTIN_TOSLINK_R 0x07
2025#define EXTIN_LINE1_L 0x08
2026#define EXTIN_LINE1_R 0x09
2027#define EXTIN_COAX_SPDIF_L 0x0a
2028#define EXTIN_COAX_SPDIF_R 0x0b
2029#define EXTIN_LINE2_L 0x0c
2030#define EXTIN_LINE2_R 0x0d
2031
2032
2033#define EXTOUT_AC97_L 0x00
2034#define EXTOUT_AC97_R 0x01
2035#define EXTOUT_TOSLINK_L 0x02
2036#define EXTOUT_TOSLINK_R 0x03
2037#define EXTOUT_AC97_CENTER 0x04
2038#define EXTOUT_AC97_LFE 0x05
2039#define EXTOUT_HEADPHONE_L 0x06
2040#define EXTOUT_HEADPHONE_R 0x07
2041#define EXTOUT_REAR_L 0x08
2042#define EXTOUT_REAR_R 0x09
2043#define EXTOUT_ADC_CAP_L 0x0a
2044#define EXTOUT_ADC_CAP_R 0x0b
2045#define EXTOUT_MIC_CAP 0x0c
2046#define EXTOUT_AC97_REAR_L 0x0d
2047#define EXTOUT_AC97_REAR_R 0x0e
2048#define EXTOUT_ACENTER 0x11
2049#define EXTOUT_ALFE 0x12
2050
2051
2052#define A_EXTIN_AC97_L 0x00
2053#define A_EXTIN_AC97_R 0x01
2054#define A_EXTIN_SPDIF_CD_L 0x02
2055#define A_EXTIN_SPDIF_CD_R 0x03
2056#define A_EXTIN_OPT_SPDIF_L 0x04
2057#define A_EXTIN_OPT_SPDIF_R 0x05
2058#define A_EXTIN_LINE2_L 0x08
2059#define A_EXTIN_LINE2_R 0x09
2060#define A_EXTIN_ADC_L 0x0a
2061#define A_EXTIN_ADC_R 0x0b
2062#define A_EXTIN_AUX2_L 0x0c
2063#define A_EXTIN_AUX2_R 0x0d
2064
2065
2066#define A_EXTOUT_FRONT_L 0x00
2067#define A_EXTOUT_FRONT_R 0x01
2068#define A_EXTOUT_CENTER 0x02
2069#define A_EXTOUT_LFE 0x03
2070#define A_EXTOUT_HEADPHONE_L 0x04
2071#define A_EXTOUT_HEADPHONE_R 0x05
2072#define A_EXTOUT_REAR_L 0x06
2073#define A_EXTOUT_REAR_R 0x07
2074#define A_EXTOUT_AFRONT_L 0x08
2075#define A_EXTOUT_AFRONT_R 0x09
2076#define A_EXTOUT_ACENTER 0x0a
2077#define A_EXTOUT_ALFE 0x0b
2078#define A_EXTOUT_ASIDE_L 0x0c
2079#define A_EXTOUT_ASIDE_R 0x0d
2080#define A_EXTOUT_AREAR_L 0x0e
2081#define A_EXTOUT_AREAR_R 0x0f
2082#define A_EXTOUT_AC97_L 0x10
2083#define A_EXTOUT_AC97_R 0x11
2084#define A_EXTOUT_ADC_CAP_L 0x16
2085#define A_EXTOUT_ADC_CAP_R 0x17
2086#define A_EXTOUT_MIC_CAP 0x18
2087
2088
2089#define A_C_00000000 0xc0
2090#define A_C_00000001 0xc1
2091#define A_C_00000002 0xc2
2092#define A_C_00000003 0xc3
2093#define A_C_00000004 0xc4
2094#define A_C_00000008 0xc5
2095#define A_C_00000010 0xc6
2096#define A_C_00000020 0xc7
2097#define A_C_00000100 0xc8
2098#define A_C_00010000 0xc9
2099#define A_C_00000800 0xca
2100#define A_C_10000000 0xcb
2101#define A_C_20000000 0xcc
2102#define A_C_40000000 0xcd
2103#define A_C_80000000 0xce
2104#define A_C_7fffffff 0xcf
2105#define A_C_ffffffff 0xd0
2106#define A_C_fffffffe 0xd1
2107#define A_C_c0000000 0xd2
2108#define A_C_4f1bbcdc 0xd3
2109#define A_C_5a7ef9db 0xd4
2110#define A_C_00100000 0xd5
2111#define A_GPR_ACCU 0xd6
2112#define A_GPR_COND 0xd7
2113#define A_GPR_NOISE0 0xd8
2114#define A_GPR_NOISE1 0xd9
2115#define A_GPR_IRQ 0xda
2116#define A_GPR_DBAC 0xdb
2117#define A_GPR_DBACE 0xde
2118
2119
2120#define EMU10K1_DBG_ZC 0x80000000
2121#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000
2122#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000
2123#define EMU10K1_DBG_SINGLE_STEP 0x00008000
2124#define EMU10K1_DBG_STEP 0x00004000
2125#define EMU10K1_DBG_CONDITION_CODE 0x00003e00
2126#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff
2127
2128
2129#ifndef __KERNEL__
2130#define TANKMEMADDRREG_ADDR_MASK 0x000fffff
2131#define TANKMEMADDRREG_CLEAR 0x00800000
2132#define TANKMEMADDRREG_ALIGN 0x00400000
2133#define TANKMEMADDRREG_WRITE 0x00200000
2134#define TANKMEMADDRREG_READ 0x00100000
2135#endif
2136
2137struct snd_emu10k1_fx8010_info {
2138 unsigned int internal_tram_size;
2139 unsigned int external_tram_size;
2140 char fxbus_names[16][32];
2141 char extin_names[16][32];
2142 char extout_names[32][32];
2143 unsigned int gpr_controls;
2144};
2145
2146#define EMU10K1_GPR_TRANSLATION_NONE 0
2147#define EMU10K1_GPR_TRANSLATION_TABLE100 1
2148#define EMU10K1_GPR_TRANSLATION_BASS 2
2149#define EMU10K1_GPR_TRANSLATION_TREBLE 3
2150#define EMU10K1_GPR_TRANSLATION_ONOFF 4
2151
2152struct snd_emu10k1_fx8010_control_gpr {
2153 struct snd_ctl_elem_id id;
2154 unsigned int vcount;
2155 unsigned int count;
2156 unsigned short gpr[32];
2157 unsigned int value[32];
2158 unsigned int min;
2159 unsigned int max;
2160 unsigned int translation;
2161 const unsigned int *tlv;
2162};
2163
2164
2165struct snd_emu10k1_fx8010_control_old_gpr {
2166 struct snd_ctl_elem_id id;
2167 unsigned int vcount;
2168 unsigned int count;
2169 unsigned short gpr[32];
2170 unsigned int value[32];
2171 unsigned int min;
2172 unsigned int max;
2173 unsigned int translation;
2174};
2175
2176struct snd_emu10k1_fx8010_code {
2177 char name[128];
2178
2179 DECLARE_BITMAP(gpr_valid, 0x200);
2180 __u32 __user *gpr_map;
2181
2182 unsigned int gpr_add_control_count;
2183 struct snd_emu10k1_fx8010_control_gpr __user *gpr_add_controls;
2184
2185 unsigned int gpr_del_control_count;
2186 struct snd_ctl_elem_id __user *gpr_del_controls;
2187
2188 unsigned int gpr_list_control_count;
2189 unsigned int gpr_list_control_total;
2190 struct snd_emu10k1_fx8010_control_gpr __user *gpr_list_controls;
2191
2192 DECLARE_BITMAP(tram_valid, 0x100);
2193 __u32 __user *tram_data_map;
2194 __u32 __user *tram_addr_map;
2195
2196 DECLARE_BITMAP(code_valid, 1024);
2197 __u32 __user *code;
2198};
2199
2200struct snd_emu10k1_fx8010_tram {
2201 unsigned int address;
2202 unsigned int size;
2203 unsigned int *samples;
2204
2205};
2206
2207struct snd_emu10k1_fx8010_pcm_rec {
2208 unsigned int substream;
2209 unsigned int res1;
2210 unsigned int channels;
2211 unsigned int tram_start;
2212 unsigned int buffer_size;
2213 unsigned short gpr_size;
2214 unsigned short gpr_ptr;
2215 unsigned short gpr_count;
2216 unsigned short gpr_tmpcount;
2217 unsigned short gpr_trigger;
2218 unsigned short gpr_running;
2219 unsigned char pad;
2220 unsigned char etram[32];
2221 unsigned int res2;
2222};
2223
2224#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
2225
2226#define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
2227#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
2228#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
2229#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
2230#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
2231#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
2232#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
2233#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
2234#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int)
2235#define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
2236#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
2237#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
2238#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
2239#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
2240
2241
2242typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t;
2243typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t;
2244typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t;
2245typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t;
2246typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t;
2247
2248#endif
2249