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176#include <asm/io.h>
177#include <linux/init.h>
178#include <linux/bug.h>
179#include <linux/pci.h>
180#include <linux/delay.h>
181#include <linux/slab.h>
182#include <linux/gameport.h>
183#include <linux/moduleparam.h>
184#include <linux/dma-mapping.h>
185#include <sound/core.h>
186#include <sound/control.h>
187#include <sound/pcm.h>
188#include <sound/rawmidi.h>
189#include <sound/mpu401.h>
190#include <sound/opl3.h>
191#include <sound/initval.h>
192#include "azt3328.h"
193
194MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
195MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
196MODULE_LICENSE("GPL");
197MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
198
199#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
200#define SUPPORT_GAMEPORT 1
201#endif
202
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225#define DEBUG_MISC 0
226#define DEBUG_CALLS 0
227#define DEBUG_MIXER 0
228#define DEBUG_CODEC 0
229#define DEBUG_TIMER 0
230#define DEBUG_GAME 0
231#define DEBUG_PM 0
232#define MIXER_TESTING 0
233
234#if DEBUG_MISC
235#define snd_azf3328_dbgmisc(format, args...) printk(KERN_DEBUG format, ##args)
236#else
237#define snd_azf3328_dbgmisc(format, args...)
238#endif
239
240#if DEBUG_CALLS
241#define snd_azf3328_dbgcalls(format, args...) printk(format, ##args)
242#define snd_azf3328_dbgcallenter() printk(KERN_DEBUG "--> %s\n", __func__)
243#define snd_azf3328_dbgcallleave() printk(KERN_DEBUG "<-- %s\n", __func__)
244#else
245#define snd_azf3328_dbgcalls(format, args...)
246#define snd_azf3328_dbgcallenter()
247#define snd_azf3328_dbgcallleave()
248#endif
249
250#if DEBUG_MIXER
251#define snd_azf3328_dbgmixer(format, args...) printk(KERN_DEBUG format, ##args)
252#else
253#define snd_azf3328_dbgmixer(format, args...)
254#endif
255
256#if DEBUG_CODEC
257#define snd_azf3328_dbgcodec(format, args...) printk(KERN_DEBUG format, ##args)
258#else
259#define snd_azf3328_dbgcodec(format, args...)
260#endif
261
262#if DEBUG_MISC
263#define snd_azf3328_dbgtimer(format, args...) printk(KERN_DEBUG format, ##args)
264#else
265#define snd_azf3328_dbgtimer(format, args...)
266#endif
267
268#if DEBUG_GAME
269#define snd_azf3328_dbggame(format, args...) printk(KERN_DEBUG format, ##args)
270#else
271#define snd_azf3328_dbggame(format, args...)
272#endif
273
274#if DEBUG_PM
275#define snd_azf3328_dbgpm(format, args...) printk(KERN_DEBUG format, ##args)
276#else
277#define snd_azf3328_dbgpm(format, args...)
278#endif
279
280static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
281module_param_array(index, int, NULL, 0444);
282MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
283
284static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
285module_param_array(id, charp, NULL, 0444);
286MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
287
288static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
289module_param_array(enable, bool, NULL, 0444);
290MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
291
292static int seqtimer_scaling = 128;
293module_param(seqtimer_scaling, int, 0444);
294MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
295
296enum snd_azf3328_codec_type {
297
298 AZF_CODEC_PLAYBACK = 0,
299 AZF_CODEC_CAPTURE = 1,
300 AZF_CODEC_I2S_OUT = 2,
301};
302
303struct snd_azf3328_codec_data {
304 unsigned long io_base;
305 unsigned int dma_base;
306 spinlock_t *lock;
307 struct snd_pcm_substream *substream;
308 bool running;
309 enum snd_azf3328_codec_type type;
310 const char *name;
311};
312
313struct snd_azf3328 {
314
315
316 unsigned long ctrl_io;
317 unsigned long game_io;
318 unsigned long mpu_io;
319 unsigned long opl3_io;
320 unsigned long mixer_io;
321
322 spinlock_t reg_lock;
323
324 struct snd_timer *timer;
325
326 struct snd_pcm *pcm[3];
327
328
329 struct snd_azf3328_codec_data codecs[3];
330
331 struct snd_card *card;
332 struct snd_rawmidi *rmidi;
333
334#ifdef SUPPORT_GAMEPORT
335 struct gameport *gameport;
336 u16 axes[4];
337#endif
338
339 struct pci_dev *pci;
340 int irq;
341
342
343
344
345
346 u16 shadow_reg_ctrl_6AH;
347
348#ifdef CONFIG_PM
349
350
351 u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4];
352 u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4];
353 u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4];
354 u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4];
355 u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4];
356#endif
357};
358
359static DEFINE_PCI_DEVICE_TABLE(snd_azf3328_ids) = {
360 { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
361 { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
362 { 0, }
363};
364
365MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
366
367
368static int
369snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set)
370{
371
372
373
374 u8 prev = inb(reg), new;
375
376 new = (do_set) ? (prev|mask) : (prev & ~mask);
377
378
379 outb(new, reg);
380 if (new != prev)
381 return 1;
382
383 return 0;
384}
385
386static inline void
387snd_azf3328_codec_outb(const struct snd_azf3328_codec_data *codec,
388 unsigned reg,
389 u8 value
390)
391{
392 outb(value, codec->io_base + reg);
393}
394
395static inline u8
396snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg)
397{
398 return inb(codec->io_base + reg);
399}
400
401static inline void
402snd_azf3328_codec_outw(const struct snd_azf3328_codec_data *codec,
403 unsigned reg,
404 u16 value
405)
406{
407 outw(value, codec->io_base + reg);
408}
409
410static inline u16
411snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg)
412{
413 return inw(codec->io_base + reg);
414}
415
416static inline void
417snd_azf3328_codec_outl(const struct snd_azf3328_codec_data *codec,
418 unsigned reg,
419 u32 value
420)
421{
422 outl(value, codec->io_base + reg);
423}
424
425static inline void
426snd_azf3328_codec_outl_multi(const struct snd_azf3328_codec_data *codec,
427 unsigned reg, const void *buffer, int count
428)
429{
430 unsigned long addr = codec->io_base + reg;
431 if (count) {
432 const u32 *buf = buffer;
433 do {
434 outl(*buf++, addr);
435 addr += 4;
436 } while (--count);
437 }
438}
439
440static inline u32
441snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg)
442{
443 return inl(codec->io_base + reg);
444}
445
446static inline void
447snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
448{
449 outb(value, chip->ctrl_io + reg);
450}
451
452static inline u8
453snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg)
454{
455 return inb(chip->ctrl_io + reg);
456}
457
458static inline void
459snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
460{
461 outw(value, chip->ctrl_io + reg);
462}
463
464static inline void
465snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value)
466{
467 outl(value, chip->ctrl_io + reg);
468}
469
470static inline void
471snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
472{
473 outb(value, chip->game_io + reg);
474}
475
476static inline void
477snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
478{
479 outw(value, chip->game_io + reg);
480}
481
482static inline u8
483snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg)
484{
485 return inb(chip->game_io + reg);
486}
487
488static inline u16
489snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg)
490{
491 return inw(chip->game_io + reg);
492}
493
494static inline void
495snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
496{
497 outw(value, chip->mixer_io + reg);
498}
499
500static inline u16
501snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg)
502{
503 return inw(chip->mixer_io + reg);
504}
505
506#define AZF_MUTE_BIT 0x80
507
508static bool
509snd_azf3328_mixer_set_mute(const struct snd_azf3328 *chip,
510 unsigned reg, bool do_mute
511)
512{
513 unsigned long portbase = chip->mixer_io + reg + 1;
514 bool updated;
515
516
517
518 updated = snd_azf3328_io_reg_setb(portbase, AZF_MUTE_BIT, do_mute);
519
520
521 return (do_mute) ? !updated : updated;
522}
523
524static void
525snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip,
526 unsigned reg,
527 unsigned char dst_vol_left,
528 unsigned char dst_vol_right,
529 int chan_sel, int delay
530)
531{
532 unsigned long portbase = chip->mixer_io + reg;
533 unsigned char curr_vol_left = 0, curr_vol_right = 0;
534 int left_change = 0, right_change = 0;
535
536 snd_azf3328_dbgcallenter();
537
538 if (chan_sel & SET_CHAN_LEFT) {
539 curr_vol_left = inb(portbase + 1);
540
541
542 if (curr_vol_left & AZF_MUTE_BIT)
543 dst_vol_left |= AZF_MUTE_BIT;
544 else
545 dst_vol_left &= ~AZF_MUTE_BIT;
546
547 left_change = (curr_vol_left > dst_vol_left) ? -1 : 1;
548 }
549
550 if (chan_sel & SET_CHAN_RIGHT) {
551 curr_vol_right = inb(portbase + 0);
552
553 right_change = (curr_vol_right > dst_vol_right) ? -1 : 1;
554 }
555
556 do {
557 if (left_change) {
558 if (curr_vol_left != dst_vol_left) {
559 curr_vol_left += left_change;
560 outb(curr_vol_left, portbase + 1);
561 } else
562 left_change = 0;
563 }
564 if (right_change) {
565 if (curr_vol_right != dst_vol_right) {
566 curr_vol_right += right_change;
567
568
569
570
571 outb(curr_vol_right, portbase + 0);
572 } else
573 right_change = 0;
574 }
575 if (delay)
576 mdelay(delay);
577 } while ((left_change) || (right_change));
578 snd_azf3328_dbgcallleave();
579}
580
581
582
583
584struct azf3328_mixer_reg {
585 unsigned reg;
586 unsigned int lchan_shift, rchan_shift;
587 unsigned int mask;
588 unsigned int invert: 1;
589 unsigned int stereo: 1;
590 unsigned int enum_c: 4;
591};
592
593#define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
594 ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
595 (mask << 16) | \
596 (invert << 24) | \
597 (stereo << 25) | \
598 (enum_c << 26))
599
600static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
601{
602 r->reg = val & 0xff;
603 r->lchan_shift = (val >> 8) & 0x0f;
604 r->rchan_shift = (val >> 12) & 0x0f;
605 r->mask = (val >> 16) & 0xff;
606 r->invert = (val >> 24) & 1;
607 r->stereo = (val >> 25) & 1;
608 r->enum_c = (val >> 26) & 0x0f;
609}
610
611
612
613
614
615#define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
616{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
617 .info = snd_azf3328_info_mixer, \
618 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
619 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
620}
621
622#define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
623{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
624 .info = snd_azf3328_info_mixer, \
625 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
626 .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
627}
628
629#define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
630{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
631 .info = snd_azf3328_info_mixer, \
632 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
633 .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
634}
635
636#define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
637{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
638 .info = snd_azf3328_info_mixer, \
639 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
640 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
641}
642
643#define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
644{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
645 .info = snd_azf3328_info_mixer_enum, \
646 .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
647 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
648}
649
650static int
651snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
652 struct snd_ctl_elem_info *uinfo)
653{
654 struct azf3328_mixer_reg reg;
655
656 snd_azf3328_dbgcallenter();
657 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
658 uinfo->type = reg.mask == 1 ?
659 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
660 uinfo->count = reg.stereo + 1;
661 uinfo->value.integer.min = 0;
662 uinfo->value.integer.max = reg.mask;
663 snd_azf3328_dbgcallleave();
664 return 0;
665}
666
667static int
668snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
669 struct snd_ctl_elem_value *ucontrol)
670{
671 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
672 struct azf3328_mixer_reg reg;
673 u16 oreg, val;
674
675 snd_azf3328_dbgcallenter();
676 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
677
678 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
679 val = (oreg >> reg.lchan_shift) & reg.mask;
680 if (reg.invert)
681 val = reg.mask - val;
682 ucontrol->value.integer.value[0] = val;
683 if (reg.stereo) {
684 val = (oreg >> reg.rchan_shift) & reg.mask;
685 if (reg.invert)
686 val = reg.mask - val;
687 ucontrol->value.integer.value[1] = val;
688 }
689 snd_azf3328_dbgmixer("get: %02x is %04x -> vol %02lx|%02lx "
690 "(shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
691 reg.reg, oreg,
692 ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
693 reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
694 snd_azf3328_dbgcallleave();
695 return 0;
696}
697
698static int
699snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
700 struct snd_ctl_elem_value *ucontrol)
701{
702 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
703 struct azf3328_mixer_reg reg;
704 u16 oreg, nreg, val;
705
706 snd_azf3328_dbgcallenter();
707 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
708 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
709 val = ucontrol->value.integer.value[0] & reg.mask;
710 if (reg.invert)
711 val = reg.mask - val;
712 nreg = oreg & ~(reg.mask << reg.lchan_shift);
713 nreg |= (val << reg.lchan_shift);
714 if (reg.stereo) {
715 val = ucontrol->value.integer.value[1] & reg.mask;
716 if (reg.invert)
717 val = reg.mask - val;
718 nreg &= ~(reg.mask << reg.rchan_shift);
719 nreg |= (val << reg.rchan_shift);
720 }
721 if (reg.mask >= 0x07)
722 snd_azf3328_mixer_write_volume_gradually(
723 chip, reg.reg, nreg >> 8, nreg & 0xff,
724
725 SET_CHAN_LEFT|SET_CHAN_RIGHT,
726 0);
727 else
728 snd_azf3328_mixer_outw(chip, reg.reg, nreg);
729
730 snd_azf3328_dbgmixer("put: %02x to %02lx|%02lx, "
731 "oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
732 reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
733 oreg, reg.lchan_shift, reg.rchan_shift,
734 nreg, snd_azf3328_mixer_inw(chip, reg.reg));
735 snd_azf3328_dbgcallleave();
736 return (nreg != oreg);
737}
738
739static int
740snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
741 struct snd_ctl_elem_info *uinfo)
742{
743 static const char * const texts1[] = {
744 "Mic1", "Mic2"
745 };
746 static const char * const texts2[] = {
747 "Mix", "Mic"
748 };
749 static const char * const texts3[] = {
750 "Mic", "CD", "Video", "Aux",
751 "Line", "Mix", "Mix Mono", "Phone"
752 };
753 static const char * const texts4[] = {
754 "pre 3D", "post 3D"
755 };
756 struct azf3328_mixer_reg reg;
757 const char * const *p = NULL;
758
759 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
760 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
761 uinfo->count = (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1;
762 uinfo->value.enumerated.items = reg.enum_c;
763 if (uinfo->value.enumerated.item > reg.enum_c - 1U)
764 uinfo->value.enumerated.item = reg.enum_c - 1U;
765 if (reg.reg == IDX_MIXER_ADVCTL2) {
766 switch(reg.lchan_shift) {
767 case 8:
768 p = texts1;
769 break;
770 case 9:
771 p = texts2;
772 break;
773 case 15:
774 p = texts4;
775 break;
776 }
777 } else
778 if (reg.reg == IDX_MIXER_REC_SELECT)
779 p = texts3;
780
781 strcpy(uinfo->value.enumerated.name, p[uinfo->value.enumerated.item]);
782 return 0;
783}
784
785static int
786snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
787 struct snd_ctl_elem_value *ucontrol)
788{
789 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
790 struct azf3328_mixer_reg reg;
791 unsigned short val;
792
793 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
794 val = snd_azf3328_mixer_inw(chip, reg.reg);
795 if (reg.reg == IDX_MIXER_REC_SELECT) {
796 ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
797 ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
798 } else
799 ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
800
801 snd_azf3328_dbgmixer("get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
802 reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
803 reg.lchan_shift, reg.enum_c);
804 return 0;
805}
806
807static int
808snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
809 struct snd_ctl_elem_value *ucontrol)
810{
811 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
812 struct azf3328_mixer_reg reg;
813 u16 oreg, nreg, val;
814
815 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
816 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
817 val = oreg;
818 if (reg.reg == IDX_MIXER_REC_SELECT) {
819 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
820 ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
821 return -EINVAL;
822 val = (ucontrol->value.enumerated.item[0] << 8) |
823 (ucontrol->value.enumerated.item[1] << 0);
824 } else {
825 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
826 return -EINVAL;
827 val &= ~((reg.enum_c - 1) << reg.lchan_shift);
828 val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
829 }
830 snd_azf3328_mixer_outw(chip, reg.reg, val);
831 nreg = val;
832
833 snd_azf3328_dbgmixer("put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
834 return (nreg != oreg);
835}
836
837static struct snd_kcontrol_new snd_azf3328_mixer_controls[] __devinitdata = {
838 AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
839 AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
840 AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
841 AZF3328_MIXER_VOL_STEREO("PCM Playback Volume",
842 IDX_MIXER_WAVEOUT, 0x1f, 1),
843 AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch",
844 IDX_MIXER_ADVCTL2, 7, 1),
845 AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
846 AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
847 AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
848 AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
849 AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
850 AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
851 AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
852 AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
853 AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
854 AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
855 AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
856 AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
857 AZF3328_MIXER_SWITCH("Beep Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
858 AZF3328_MIXER_VOL_SPECIAL("Beep Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
859 AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
860 AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
861 AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
862 AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
863 AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
864 AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
865 AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
866 AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
867 AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8),
868 AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9),
869 AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15),
870 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
871 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
872 AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
873 AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0),
874 AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0),
875#if MIXER_TESTING
876 AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
877 AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
878 AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
879 AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
880 AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
881 AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
882 AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
883 AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
884 AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
885 AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
886 AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
887 AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
888 AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
889 AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
890 AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
891 AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
892#endif
893};
894
895static u16 __devinitdata snd_azf3328_init_values[][2] = {
896 { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f },
897 { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f },
898 { IDX_MIXER_BASSTREBLE, 0x0000 },
899 { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f },
900 { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f },
901 { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f },
902 { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f },
903 { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f },
904 { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f },
905 { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f },
906 { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f },
907 { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f },
908 { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 },
909};
910
911static int __devinit
912snd_azf3328_mixer_new(struct snd_azf3328 *chip)
913{
914 struct snd_card *card;
915 const struct snd_kcontrol_new *sw;
916 unsigned int idx;
917 int err;
918
919 snd_azf3328_dbgcallenter();
920 if (snd_BUG_ON(!chip || !chip->card))
921 return -EINVAL;
922
923 card = chip->card;
924
925
926 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
927
928
929 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) {
930 snd_azf3328_mixer_outw(chip,
931 snd_azf3328_init_values[idx][0],
932 snd_azf3328_init_values[idx][1]);
933 }
934
935
936 sw = snd_azf3328_mixer_controls;
937 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls);
938 ++idx, ++sw) {
939 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
940 return err;
941 }
942 snd_component_add(card, "AZF3328 mixer");
943 strcpy(card->mixername, "AZF3328 mixer");
944
945 snd_azf3328_dbgcallleave();
946 return 0;
947}
948
949static int
950snd_azf3328_hw_params(struct snd_pcm_substream *substream,
951 struct snd_pcm_hw_params *hw_params)
952{
953 int res;
954 snd_azf3328_dbgcallenter();
955 res = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
956 snd_azf3328_dbgcallleave();
957 return res;
958}
959
960static int
961snd_azf3328_hw_free(struct snd_pcm_substream *substream)
962{
963 snd_azf3328_dbgcallenter();
964 snd_pcm_lib_free_pages(substream);
965 snd_azf3328_dbgcallleave();
966 return 0;
967}
968
969static void
970snd_azf3328_codec_setfmt(struct snd_azf3328_codec_data *codec,
971 enum azf_freq_t bitrate,
972 unsigned int format_width,
973 unsigned int channels
974)
975{
976 unsigned long flags;
977 u16 val = 0xff00;
978 u8 freq = 0;
979
980 snd_azf3328_dbgcallenter();
981 switch (bitrate) {
982 case AZF_FREQ_4000: freq = SOUNDFORMAT_FREQ_SUSPECTED_4000; break;
983 case AZF_FREQ_4800: freq = SOUNDFORMAT_FREQ_SUSPECTED_4800; break;
984 case AZF_FREQ_5512:
985
986 freq = SOUNDFORMAT_FREQ_5510; break;
987 case AZF_FREQ_6620: freq = SOUNDFORMAT_FREQ_6620; break;
988 case AZF_FREQ_8000: freq = SOUNDFORMAT_FREQ_8000; break;
989 case AZF_FREQ_9600: freq = SOUNDFORMAT_FREQ_9600; break;
990 case AZF_FREQ_11025: freq = SOUNDFORMAT_FREQ_11025; break;
991 case AZF_FREQ_13240: freq = SOUNDFORMAT_FREQ_SUSPECTED_13240; break;
992 case AZF_FREQ_16000: freq = SOUNDFORMAT_FREQ_16000; break;
993 case AZF_FREQ_22050: freq = SOUNDFORMAT_FREQ_22050; break;
994 case AZF_FREQ_32000: freq = SOUNDFORMAT_FREQ_32000; break;
995 default:
996 snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
997
998 case AZF_FREQ_44100: freq = SOUNDFORMAT_FREQ_44100; break;
999 case AZF_FREQ_48000: freq = SOUNDFORMAT_FREQ_48000; break;
1000 case AZF_FREQ_66200: freq = SOUNDFORMAT_FREQ_SUSPECTED_66200; break;
1001 }
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012 val |= freq;
1013
1014 if (channels == 2)
1015 val |= SOUNDFORMAT_FLAG_2CHANNELS;
1016
1017 if (format_width == 16)
1018 val |= SOUNDFORMAT_FLAG_16BIT;
1019
1020 spin_lock_irqsave(codec->lock, flags);
1021
1022
1023 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, val);
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033 if (codec->type != AZF_CODEC_CAPTURE)
1034 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1035 snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS) |
1036 DMA_RUN_SOMETHING1 |
1037 DMA_RUN_SOMETHING2 |
1038 SOMETHING_ALMOST_ALWAYS_SET |
1039 DMA_EPILOGUE_SOMETHING |
1040 DMA_SOMETHING_ELSE
1041 );
1042
1043 spin_unlock_irqrestore(codec->lock, flags);
1044 snd_azf3328_dbgcallleave();
1045}
1046
1047static inline void
1048snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328_codec_data *codec
1049)
1050{
1051
1052
1053
1054
1055 snd_azf3328_codec_setfmt(codec, AZF_FREQ_4000, 8, 1);
1056}
1057
1058static void
1059snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip,
1060 unsigned bitmask,
1061 bool enable
1062)
1063{
1064 bool do_mask = !enable;
1065 if (do_mask)
1066 chip->shadow_reg_ctrl_6AH |= bitmask;
1067 else
1068 chip->shadow_reg_ctrl_6AH &= ~bitmask;
1069 snd_azf3328_dbgcodec("6AH_update mask 0x%04x do_mask %d: val 0x%04x\n",
1070 bitmask, do_mask, chip->shadow_reg_ctrl_6AH);
1071 snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH);
1072}
1073
1074static inline void
1075snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable)
1076{
1077 snd_azf3328_dbgcodec("codec_enable %d\n", enable);
1078
1079
1080 snd_azf3328_ctrl_reg_6AH_update(
1081 chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable
1082 );
1083}
1084
1085static void
1086snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip,
1087 enum snd_azf3328_codec_type codec_type,
1088 bool enable
1089)
1090{
1091 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
1092 bool need_change = (codec->running != enable);
1093
1094 snd_azf3328_dbgcodec(
1095 "codec_activity: %s codec, enable %d, need_change %d\n",
1096 codec->name, enable, need_change
1097 );
1098 if (need_change) {
1099 static const struct {
1100 enum snd_azf3328_codec_type other1;
1101 enum snd_azf3328_codec_type other2;
1102 } peer_codecs[3] =
1103 { { AZF_CODEC_CAPTURE, AZF_CODEC_I2S_OUT },
1104 { AZF_CODEC_PLAYBACK, AZF_CODEC_I2S_OUT },
1105 { AZF_CODEC_PLAYBACK, AZF_CODEC_CAPTURE } };
1106 bool call_function;
1107
1108 if (enable)
1109
1110
1111 call_function = 1;
1112 else {
1113
1114
1115
1116
1117 call_function =
1118 ((!chip->codecs[peer_codecs[codec_type].other1]
1119 .running)
1120 && (!chip->codecs[peer_codecs[codec_type].other2]
1121 .running));
1122 }
1123 if (call_function)
1124 snd_azf3328_ctrl_enable_codecs(chip, enable);
1125
1126
1127
1128 if (!enable)
1129 snd_azf3328_codec_setfmt_lowpower(codec);
1130 codec->running = enable;
1131 }
1132}
1133
1134static void
1135snd_azf3328_codec_setdmaa(struct snd_azf3328_codec_data *codec,
1136 unsigned long addr,
1137 unsigned int period_bytes,
1138 unsigned int buffer_bytes
1139)
1140{
1141 snd_azf3328_dbgcallenter();
1142 WARN_ONCE(period_bytes & 1, "odd period length!?\n");
1143 WARN_ONCE(buffer_bytes != 2 * period_bytes,
1144 "missed our input expectations! %u vs. %u\n",
1145 buffer_bytes, period_bytes);
1146 if (!codec->running) {
1147
1148
1149 unsigned long flags;
1150
1151
1152 u32 area_length;
1153 struct codec_setup_io {
1154 u32 dma_start_1;
1155 u32 dma_start_2;
1156 u32 dma_lengths;
1157 } __attribute__((packed)) setup_io;
1158
1159 area_length = buffer_bytes/2;
1160
1161 setup_io.dma_start_1 = addr;
1162 setup_io.dma_start_2 = addr+area_length;
1163
1164 snd_azf3328_dbgcodec(
1165 "setdma: buffers %08x[%u] / %08x[%u], %u, %u\n",
1166 setup_io.dma_start_1, area_length,
1167 setup_io.dma_start_2, area_length,
1168 period_bytes, buffer_bytes);
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179 setup_io.dma_lengths = (area_length << 16) | (area_length);
1180
1181 spin_lock_irqsave(codec->lock, flags);
1182 snd_azf3328_codec_outl_multi(
1183 codec, IDX_IO_CODEC_DMA_START_1, &setup_io, 3
1184 );
1185 spin_unlock_irqrestore(codec->lock, flags);
1186 }
1187 snd_azf3328_dbgcallleave();
1188}
1189
1190static int
1191snd_azf3328_pcm_prepare(struct snd_pcm_substream *substream)
1192{
1193 struct snd_pcm_runtime *runtime = substream->runtime;
1194 struct snd_azf3328_codec_data *codec = runtime->private_data;
1195#if 0
1196 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1197 unsigned int count = snd_pcm_lib_period_bytes(substream);
1198#endif
1199
1200 snd_azf3328_dbgcallenter();
1201
1202 codec->dma_base = runtime->dma_addr;
1203
1204#if 0
1205 snd_azf3328_codec_setfmt(codec,
1206 runtime->rate,
1207 snd_pcm_format_width(runtime->format),
1208 runtime->channels);
1209 snd_azf3328_codec_setdmaa(codec,
1210 runtime->dma_addr, count, size);
1211#endif
1212 snd_azf3328_dbgcallleave();
1213 return 0;
1214}
1215
1216static int
1217snd_azf3328_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1218{
1219 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1220 struct snd_pcm_runtime *runtime = substream->runtime;
1221 struct snd_azf3328_codec_data *codec = runtime->private_data;
1222 int result = 0;
1223 u16 flags1;
1224 bool previously_muted = 0;
1225 bool is_main_mixer_playback_codec = (AZF_CODEC_PLAYBACK == codec->type);
1226
1227 snd_azf3328_dbgcalls("snd_azf3328_pcm_trigger cmd %d\n", cmd);
1228
1229 switch (cmd) {
1230 case SNDRV_PCM_TRIGGER_START:
1231 snd_azf3328_dbgcodec("START %s\n", codec->name);
1232
1233 if (is_main_mixer_playback_codec) {
1234
1235 previously_muted =
1236 snd_azf3328_mixer_set_mute(
1237 chip, IDX_MIXER_WAVEOUT, 1
1238 );
1239 }
1240
1241 snd_azf3328_codec_setfmt(codec,
1242 runtime->rate,
1243 snd_pcm_format_width(runtime->format),
1244 runtime->channels);
1245
1246 spin_lock(codec->lock);
1247
1248 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
1249
1250
1251 flags1 &= ~DMA_RESUME;
1252 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1253
1254
1255 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_IRQTYPE, 0xffff);
1256 spin_unlock(codec->lock);
1257
1258 snd_azf3328_codec_setdmaa(codec, runtime->dma_addr,
1259 snd_pcm_lib_period_bytes(substream),
1260 snd_pcm_lib_buffer_bytes(substream)
1261 );
1262
1263 spin_lock(codec->lock);
1264#ifdef WIN9X
1265
1266 flags1 |= DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2;
1267 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1268
1269
1270
1271 flags1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
1272 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1273#else
1274 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1275 0x0000);
1276 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1277 DMA_RUN_SOMETHING1);
1278 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1279 DMA_RUN_SOMETHING1 |
1280 DMA_RUN_SOMETHING2);
1281 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1282 DMA_RESUME |
1283 SOMETHING_ALMOST_ALWAYS_SET |
1284 DMA_EPILOGUE_SOMETHING |
1285 DMA_SOMETHING_ELSE);
1286#endif
1287 spin_unlock(codec->lock);
1288 snd_azf3328_ctrl_codec_activity(chip, codec->type, 1);
1289
1290 if (is_main_mixer_playback_codec) {
1291
1292 if (!previously_muted)
1293 snd_azf3328_mixer_set_mute(
1294 chip, IDX_MIXER_WAVEOUT, 0
1295 );
1296 }
1297
1298 snd_azf3328_dbgcodec("STARTED %s\n", codec->name);
1299 break;
1300 case SNDRV_PCM_TRIGGER_RESUME:
1301 snd_azf3328_dbgcodec("RESUME %s\n", codec->name);
1302
1303 spin_lock(codec->lock);
1304 if (codec->running)
1305 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1306 snd_azf3328_codec_inw(
1307 codec, IDX_IO_CODEC_DMA_FLAGS
1308 ) | DMA_RESUME
1309 );
1310 spin_unlock(codec->lock);
1311 break;
1312 case SNDRV_PCM_TRIGGER_STOP:
1313 snd_azf3328_dbgcodec("STOP %s\n", codec->name);
1314
1315 if (is_main_mixer_playback_codec) {
1316
1317 previously_muted =
1318 snd_azf3328_mixer_set_mute(
1319 chip, IDX_MIXER_WAVEOUT, 1
1320 );
1321 }
1322
1323 spin_lock(codec->lock);
1324
1325 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
1326
1327
1328 flags1 &= ~DMA_RESUME;
1329 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1330
1331
1332
1333 flags1 |= DMA_RUN_SOMETHING1;
1334 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1335
1336 flags1 &= ~DMA_RUN_SOMETHING1;
1337 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1338 spin_unlock(codec->lock);
1339 snd_azf3328_ctrl_codec_activity(chip, codec->type, 0);
1340
1341 if (is_main_mixer_playback_codec) {
1342
1343 if (!previously_muted)
1344 snd_azf3328_mixer_set_mute(
1345 chip, IDX_MIXER_WAVEOUT, 0
1346 );
1347 }
1348
1349 snd_azf3328_dbgcodec("STOPPED %s\n", codec->name);
1350 break;
1351 case SNDRV_PCM_TRIGGER_SUSPEND:
1352 snd_azf3328_dbgcodec("SUSPEND %s\n", codec->name);
1353
1354 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1355 snd_azf3328_codec_inw(
1356 codec, IDX_IO_CODEC_DMA_FLAGS
1357 ) & ~DMA_RESUME
1358 );
1359 break;
1360 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1361 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
1362 break;
1363 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1364 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
1365 break;
1366 default:
1367 snd_printk(KERN_ERR "FIXME: unknown trigger mode!\n");
1368 return -EINVAL;
1369 }
1370
1371 snd_azf3328_dbgcallleave();
1372 return result;
1373}
1374
1375static snd_pcm_uframes_t
1376snd_azf3328_pcm_pointer(struct snd_pcm_substream *substream
1377)
1378{
1379 const struct snd_azf3328_codec_data *codec =
1380 substream->runtime->private_data;
1381 unsigned long result;
1382 snd_pcm_uframes_t frmres;
1383
1384 result = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_CURRPOS);
1385
1386
1387#ifdef QUERY_HARDWARE
1388 result -= snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_START_1);
1389#else
1390 result -= codec->dma_base;
1391#endif
1392 frmres = bytes_to_frames( substream->runtime, result);
1393 snd_azf3328_dbgcodec("%08li %s @ 0x%8lx, frames %8ld\n",
1394 jiffies, codec->name, result, frmres);
1395 return frmres;
1396}
1397
1398
1399
1400#ifdef SUPPORT_GAMEPORT
1401static inline void
1402snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip,
1403 bool enable
1404)
1405{
1406 snd_azf3328_io_reg_setb(
1407 chip->game_io+IDX_GAME_HWCONFIG,
1408 GAME_HWCFG_IRQ_ENABLE,
1409 enable
1410 );
1411}
1412
1413static inline void
1414snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip,
1415 bool enable
1416)
1417{
1418 snd_azf3328_io_reg_setb(
1419 chip->game_io+IDX_GAME_HWCONFIG,
1420 GAME_HWCFG_LEGACY_ADDRESS_ENABLE,
1421 enable
1422 );
1423}
1424
1425static void
1426snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip,
1427 unsigned int freq_cfg
1428)
1429{
1430 snd_azf3328_io_reg_setb(
1431 chip->game_io+IDX_GAME_HWCONFIG,
1432 0x02,
1433 (freq_cfg & 1) != 0
1434 );
1435 snd_azf3328_io_reg_setb(
1436 chip->game_io+IDX_GAME_HWCONFIG,
1437 0x04,
1438 (freq_cfg & 2) != 0
1439 );
1440}
1441
1442static inline void
1443snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable)
1444{
1445 snd_azf3328_ctrl_reg_6AH_update(
1446 chip, IO_6A_SOMETHING2_GAMEPORT, enable
1447 );
1448}
1449
1450static inline void
1451snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1452{
1453
1454
1455
1456
1457 snd_azf3328_dbggame("gameport irq\n");
1458
1459
1460 snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE);
1461}
1462
1463static int
1464snd_azf3328_gameport_open(struct gameport *gameport, int mode)
1465{
1466 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1467 int res;
1468
1469 snd_azf3328_dbggame("gameport_open, mode %d\n", mode);
1470 switch (mode) {
1471 case GAMEPORT_MODE_COOKED:
1472 case GAMEPORT_MODE_RAW:
1473 res = 0;
1474 break;
1475 default:
1476 res = -1;
1477 break;
1478 }
1479
1480 snd_azf3328_gameport_set_counter_frequency(chip,
1481 GAME_HWCFG_ADC_COUNTER_FREQ_STD);
1482 snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0));
1483
1484 return res;
1485}
1486
1487static void
1488snd_azf3328_gameport_close(struct gameport *gameport)
1489{
1490 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1491
1492 snd_azf3328_dbggame("gameport_close\n");
1493 snd_azf3328_gameport_set_counter_frequency(chip,
1494 GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
1495 snd_azf3328_gameport_axis_circuit_enable(chip, 0);
1496}
1497
1498static int
1499snd_azf3328_gameport_cooked_read(struct gameport *gameport,
1500 int *axes,
1501 int *buttons
1502)
1503{
1504 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1505 int i;
1506 u8 val;
1507 unsigned long flags;
1508
1509 if (snd_BUG_ON(!chip))
1510 return 0;
1511
1512 spin_lock_irqsave(&chip->reg_lock, flags);
1513 val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE);
1514 *buttons = (~(val) >> 4) & 0xf;
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526 val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG);
1527 if (val & GAME_AXES_SAMPLING_READY) {
1528 for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) {
1529
1530 val = (i << 4) | 0x0f;
1531 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
1532
1533 chip->axes[i] = snd_azf3328_game_inw(
1534 chip, IDX_GAME_AXIS_VALUE
1535 );
1536 }
1537 }
1538
1539
1540
1541
1542
1543
1544
1545 val = 0x03;
1546 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
1547
1548 snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff);
1549 spin_unlock_irqrestore(&chip->reg_lock, flags);
1550
1551 for (i = 0; i < ARRAY_SIZE(chip->axes); i++) {
1552 axes[i] = chip->axes[i];
1553 if (axes[i] == 0xffff)
1554 axes[i] = -1;
1555 }
1556
1557 snd_azf3328_dbggame("cooked_read: axes %d %d %d %d buttons %d\n",
1558 axes[0], axes[1], axes[2], axes[3], *buttons
1559 );
1560
1561 return 0;
1562}
1563
1564static int __devinit
1565snd_azf3328_gameport(struct snd_azf3328 *chip, int dev)
1566{
1567 struct gameport *gp;
1568
1569 chip->gameport = gp = gameport_allocate_port();
1570 if (!gp) {
1571 printk(KERN_ERR "azt3328: cannot alloc memory for gameport\n");
1572 return -ENOMEM;
1573 }
1574
1575 gameport_set_name(gp, "AZF3328 Gameport");
1576 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1577 gameport_set_dev_parent(gp, &chip->pci->dev);
1578 gp->io = chip->game_io;
1579 gameport_set_port_data(gp, chip);
1580
1581 gp->open = snd_azf3328_gameport_open;
1582 gp->close = snd_azf3328_gameport_close;
1583 gp->fuzz = 16;
1584 gp->cooked_read = snd_azf3328_gameport_cooked_read;
1585
1586
1587 snd_azf3328_gameport_legacy_address_enable(chip, 0);
1588
1589 snd_azf3328_gameport_set_counter_frequency(chip,
1590 GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
1591 snd_azf3328_gameport_axis_circuit_enable(chip, 0);
1592
1593 gameport_register_port(chip->gameport);
1594
1595 return 0;
1596}
1597
1598static void
1599snd_azf3328_gameport_free(struct snd_azf3328 *chip)
1600{
1601 if (chip->gameport) {
1602 gameport_unregister_port(chip->gameport);
1603 chip->gameport = NULL;
1604 }
1605 snd_azf3328_gameport_irq_enable(chip, 0);
1606}
1607#else
1608static inline int
1609snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
1610static inline void
1611snd_azf3328_gameport_free(struct snd_azf3328 *chip) { }
1612static inline void
1613snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1614{
1615 printk(KERN_WARNING "huh, game port IRQ occurred!?\n");
1616}
1617#endif
1618
1619
1620
1621static inline void
1622snd_azf3328_irq_log_unknown_type(u8 which)
1623{
1624 snd_azf3328_dbgcodec(
1625 "azt3328: unknown IRQ type (%x) occurred, please report!\n",
1626 which
1627 );
1628}
1629
1630static inline void
1631snd_azf3328_pcm_interrupt(const struct snd_azf3328_codec_data *first_codec,
1632 u8 status
1633)
1634{
1635 u8 which;
1636 enum snd_azf3328_codec_type codec_type;
1637 const struct snd_azf3328_codec_data *codec = first_codec;
1638
1639 for (codec_type = AZF_CODEC_PLAYBACK;
1640 codec_type <= AZF_CODEC_I2S_OUT;
1641 ++codec_type, ++codec) {
1642
1643
1644 if (!(status & (1 << codec_type)))
1645 continue;
1646
1647 spin_lock(codec->lock);
1648 which = snd_azf3328_codec_inb(codec, IDX_IO_CODEC_IRQTYPE);
1649
1650 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, which);
1651 spin_unlock(codec->lock);
1652
1653 if (codec->substream) {
1654 snd_pcm_period_elapsed(codec->substream);
1655 snd_azf3328_dbgcodec("%s period done (#%x), @ %x\n",
1656 codec->name,
1657 which,
1658 snd_azf3328_codec_inl(
1659 codec, IDX_IO_CODEC_DMA_CURRPOS
1660 )
1661 );
1662 } else
1663 printk(KERN_WARNING "azt3328: irq handler problem!\n");
1664 if (which & IRQ_SOMETHING)
1665 snd_azf3328_irq_log_unknown_type(which);
1666 }
1667}
1668
1669static irqreturn_t
1670snd_azf3328_interrupt(int irq, void *dev_id)
1671{
1672 struct snd_azf3328 *chip = dev_id;
1673 u8 status;
1674#if DEBUG_CODEC
1675 static unsigned long irq_count;
1676#endif
1677
1678 status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS);
1679
1680
1681 if (!(status &
1682 (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT
1683 |IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER)
1684 ))
1685 return IRQ_NONE;
1686
1687 snd_azf3328_dbgcodec(
1688 "irq_count %ld! IDX_IO_IRQSTATUS %04x\n",
1689 irq_count++ ,
1690 status
1691 );
1692
1693 if (status & IRQ_TIMER) {
1694
1695
1696
1697
1698 if (chip->timer)
1699 snd_timer_interrupt(chip->timer, chip->timer->sticks);
1700
1701 spin_lock(&chip->reg_lock);
1702 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
1703 spin_unlock(&chip->reg_lock);
1704 snd_azf3328_dbgcodec("azt3328: timer IRQ\n");
1705 }
1706
1707 if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT))
1708 snd_azf3328_pcm_interrupt(chip->codecs, status);
1709
1710 if (status & IRQ_GAMEPORT)
1711 snd_azf3328_gameport_interrupt(chip);
1712
1713
1714
1715 if (status & IRQ_MPU401) {
1716 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1717
1718
1719
1720 snd_azf3328_dbgcodec("azt3328: MPU401 IRQ\n");
1721 }
1722 return IRQ_HANDLED;
1723}
1724
1725
1726
1727
1728
1729
1730
1731static const struct snd_pcm_hardware snd_azf3328_hardware =
1732{
1733
1734 .info = SNDRV_PCM_INFO_MMAP |
1735 SNDRV_PCM_INFO_INTERLEAVED |
1736 SNDRV_PCM_INFO_MMAP_VALID,
1737 .formats = SNDRV_PCM_FMTBIT_S8 |
1738 SNDRV_PCM_FMTBIT_U8 |
1739 SNDRV_PCM_FMTBIT_S16_LE |
1740 SNDRV_PCM_FMTBIT_U16_LE,
1741 .rates = SNDRV_PCM_RATE_5512 |
1742 SNDRV_PCM_RATE_8000_48000 |
1743 SNDRV_PCM_RATE_KNOT,
1744 .rate_min = AZF_FREQ_4000,
1745 .rate_max = AZF_FREQ_66200,
1746 .channels_min = 1,
1747 .channels_max = 2,
1748 .buffer_bytes_max = (64*1024),
1749 .period_bytes_min = 1024,
1750 .period_bytes_max = (32*1024),
1751
1752
1753
1754
1755 .periods_min = 2,
1756 .periods_max = 2,
1757
1758
1759
1760 .fifo_size = 0,
1761};
1762
1763
1764static unsigned int snd_azf3328_fixed_rates[] = {
1765 AZF_FREQ_4000,
1766 AZF_FREQ_4800,
1767 AZF_FREQ_5512,
1768 AZF_FREQ_6620,
1769 AZF_FREQ_8000,
1770 AZF_FREQ_9600,
1771 AZF_FREQ_11025,
1772 AZF_FREQ_13240,
1773 AZF_FREQ_16000,
1774 AZF_FREQ_22050,
1775 AZF_FREQ_32000,
1776 AZF_FREQ_44100,
1777 AZF_FREQ_48000,
1778 AZF_FREQ_66200
1779};
1780
1781static struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
1782 .count = ARRAY_SIZE(snd_azf3328_fixed_rates),
1783 .list = snd_azf3328_fixed_rates,
1784 .mask = 0,
1785};
1786
1787
1788
1789static int
1790snd_azf3328_pcm_open(struct snd_pcm_substream *substream,
1791 enum snd_azf3328_codec_type codec_type
1792)
1793{
1794 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1795 struct snd_pcm_runtime *runtime = substream->runtime;
1796 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
1797
1798 snd_azf3328_dbgcallenter();
1799 codec->substream = substream;
1800
1801
1802 runtime->hw = snd_azf3328_hardware;
1803
1804 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1805 &snd_azf3328_hw_constraints_rates);
1806 runtime->private_data = codec;
1807 snd_azf3328_dbgcallleave();
1808 return 0;
1809}
1810
1811static int
1812snd_azf3328_pcm_playback_open(struct snd_pcm_substream *substream)
1813{
1814 return snd_azf3328_pcm_open(substream, AZF_CODEC_PLAYBACK);
1815}
1816
1817static int
1818snd_azf3328_pcm_capture_open(struct snd_pcm_substream *substream)
1819{
1820 return snd_azf3328_pcm_open(substream, AZF_CODEC_CAPTURE);
1821}
1822
1823static int
1824snd_azf3328_pcm_i2s_out_open(struct snd_pcm_substream *substream)
1825{
1826 return snd_azf3328_pcm_open(substream, AZF_CODEC_I2S_OUT);
1827}
1828
1829static int
1830snd_azf3328_pcm_close(struct snd_pcm_substream *substream
1831)
1832{
1833 struct snd_azf3328_codec_data *codec =
1834 substream->runtime->private_data;
1835
1836 snd_azf3328_dbgcallenter();
1837 codec->substream = NULL;
1838 snd_azf3328_dbgcallleave();
1839 return 0;
1840}
1841
1842
1843
1844static struct snd_pcm_ops snd_azf3328_playback_ops = {
1845 .open = snd_azf3328_pcm_playback_open,
1846 .close = snd_azf3328_pcm_close,
1847 .ioctl = snd_pcm_lib_ioctl,
1848 .hw_params = snd_azf3328_hw_params,
1849 .hw_free = snd_azf3328_hw_free,
1850 .prepare = snd_azf3328_pcm_prepare,
1851 .trigger = snd_azf3328_pcm_trigger,
1852 .pointer = snd_azf3328_pcm_pointer
1853};
1854
1855static struct snd_pcm_ops snd_azf3328_capture_ops = {
1856 .open = snd_azf3328_pcm_capture_open,
1857 .close = snd_azf3328_pcm_close,
1858 .ioctl = snd_pcm_lib_ioctl,
1859 .hw_params = snd_azf3328_hw_params,
1860 .hw_free = snd_azf3328_hw_free,
1861 .prepare = snd_azf3328_pcm_prepare,
1862 .trigger = snd_azf3328_pcm_trigger,
1863 .pointer = snd_azf3328_pcm_pointer
1864};
1865
1866static struct snd_pcm_ops snd_azf3328_i2s_out_ops = {
1867 .open = snd_azf3328_pcm_i2s_out_open,
1868 .close = snd_azf3328_pcm_close,
1869 .ioctl = snd_pcm_lib_ioctl,
1870 .hw_params = snd_azf3328_hw_params,
1871 .hw_free = snd_azf3328_hw_free,
1872 .prepare = snd_azf3328_pcm_prepare,
1873 .trigger = snd_azf3328_pcm_trigger,
1874 .pointer = snd_azf3328_pcm_pointer
1875};
1876
1877static int __devinit
1878snd_azf3328_pcm(struct snd_azf3328 *chip)
1879{
1880enum { AZF_PCMDEV_STD, AZF_PCMDEV_I2S_OUT, NUM_AZF_PCMDEVS };
1881
1882 struct snd_pcm *pcm;
1883 int err;
1884
1885 snd_azf3328_dbgcallenter();
1886
1887 err = snd_pcm_new(chip->card, "AZF3328 DSP", AZF_PCMDEV_STD,
1888 1, 1, &pcm);
1889 if (err < 0)
1890 return err;
1891 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1892 &snd_azf3328_playback_ops);
1893 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1894 &snd_azf3328_capture_ops);
1895
1896 pcm->private_data = chip;
1897 pcm->info_flags = 0;
1898 strcpy(pcm->name, chip->card->shortname);
1899
1900 chip->pcm[AZF_CODEC_PLAYBACK] = pcm;
1901 chip->pcm[AZF_CODEC_CAPTURE] = pcm;
1902
1903 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1904 snd_dma_pci_data(chip->pci),
1905 64*1024, 64*1024);
1906
1907 err = snd_pcm_new(chip->card, "AZF3328 I2S OUT", AZF_PCMDEV_I2S_OUT,
1908 1, 0, &pcm);
1909 if (err < 0)
1910 return err;
1911 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1912 &snd_azf3328_i2s_out_ops);
1913
1914 pcm->private_data = chip;
1915 pcm->info_flags = 0;
1916 strcpy(pcm->name, chip->card->shortname);
1917 chip->pcm[AZF_CODEC_I2S_OUT] = pcm;
1918
1919 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1920 snd_dma_pci_data(chip->pci),
1921 64*1024, 64*1024);
1922
1923 snd_azf3328_dbgcallleave();
1924 return 0;
1925}
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939static int
1940snd_azf3328_timer_start(struct snd_timer *timer)
1941{
1942 struct snd_azf3328 *chip;
1943 unsigned long flags;
1944 unsigned int delay;
1945
1946 snd_azf3328_dbgcallenter();
1947 chip = snd_timer_chip(timer);
1948 delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
1949 if (delay < 49) {
1950
1951
1952
1953
1954 snd_azf3328_dbgtimer("delay was too low (%d)!\n", delay);
1955 delay = 49;
1956 }
1957 snd_azf3328_dbgtimer("setting timer countdown value %d\n", delay);
1958 delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE;
1959 spin_lock_irqsave(&chip->reg_lock, flags);
1960 snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, delay);
1961 spin_unlock_irqrestore(&chip->reg_lock, flags);
1962 snd_azf3328_dbgcallleave();
1963 return 0;
1964}
1965
1966static int
1967snd_azf3328_timer_stop(struct snd_timer *timer)
1968{
1969 struct snd_azf3328 *chip;
1970 unsigned long flags;
1971
1972 snd_azf3328_dbgcallenter();
1973 chip = snd_timer_chip(timer);
1974 spin_lock_irqsave(&chip->reg_lock, flags);
1975
1976
1977
1978
1979
1980
1981
1982 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x04);
1983 spin_unlock_irqrestore(&chip->reg_lock, flags);
1984 snd_azf3328_dbgcallleave();
1985 return 0;
1986}
1987
1988
1989static int
1990snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
1991 unsigned long *num, unsigned long *den)
1992{
1993 snd_azf3328_dbgcallenter();
1994 *num = 1;
1995 *den = 1024000 / seqtimer_scaling;
1996 snd_azf3328_dbgcallleave();
1997 return 0;
1998}
1999
2000static struct snd_timer_hardware snd_azf3328_timer_hw = {
2001 .flags = SNDRV_TIMER_HW_AUTO,
2002 .resolution = 977,
2003 .ticks = 1024000,
2004 .start = snd_azf3328_timer_start,
2005 .stop = snd_azf3328_timer_stop,
2006 .precise_resolution = snd_azf3328_timer_precise_resolution,
2007};
2008
2009static int __devinit
2010snd_azf3328_timer(struct snd_azf3328 *chip, int device)
2011{
2012 struct snd_timer *timer = NULL;
2013 struct snd_timer_id tid;
2014 int err;
2015
2016 snd_azf3328_dbgcallenter();
2017 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
2018 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
2019 tid.card = chip->card->number;
2020 tid.device = device;
2021 tid.subdevice = 0;
2022
2023 snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
2024 snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
2025
2026 err = snd_timer_new(chip->card, "AZF3328", &tid, &timer);
2027 if (err < 0)
2028 goto out;
2029
2030 strcpy(timer->name, "AZF3328 timer");
2031 timer->private_data = chip;
2032 timer->hw = snd_azf3328_timer_hw;
2033
2034 chip->timer = timer;
2035
2036 snd_azf3328_timer_stop(timer);
2037
2038 err = 0;
2039
2040out:
2041 snd_azf3328_dbgcallleave();
2042 return err;
2043}
2044
2045
2046
2047static int
2048snd_azf3328_free(struct snd_azf3328 *chip)
2049{
2050 if (chip->irq < 0)
2051 goto __end_hw;
2052
2053
2054
2055
2056 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
2057 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
2058
2059 snd_azf3328_timer_stop(chip->timer);
2060 snd_azf3328_gameport_free(chip);
2061
2062 if (chip->irq >= 0)
2063 synchronize_irq(chip->irq);
2064__end_hw:
2065 if (chip->irq >= 0)
2066 free_irq(chip->irq, chip);
2067 pci_release_regions(chip->pci);
2068 pci_disable_device(chip->pci);
2069
2070 kfree(chip);
2071 return 0;
2072}
2073
2074static int
2075snd_azf3328_dev_free(struct snd_device *device)
2076{
2077 struct snd_azf3328 *chip = device->device_data;
2078 return snd_azf3328_free(chip);
2079}
2080
2081#if 0
2082
2083static void
2084snd_azf3328_test_bit(unsigned unsigned reg, int bit)
2085{
2086 unsigned char val, valoff, valon;
2087
2088 val = inb(reg);
2089
2090 outb(val & ~(1 << bit), reg);
2091 valoff = inb(reg);
2092
2093 outb(val|(1 << bit), reg);
2094 valon = inb(reg);
2095
2096 outb(val, reg);
2097
2098 printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n",
2099 reg, bit, val, valoff, valon
2100 );
2101}
2102#endif
2103
2104static inline void
2105snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
2106{
2107#if DEBUG_MISC
2108 u16 tmp;
2109
2110 snd_azf3328_dbgmisc(
2111 "ctrl_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, "
2112 "opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n",
2113 chip->ctrl_io, chip->game_io, chip->mpu_io,
2114 chip->opl3_io, chip->mixer_io, chip->irq
2115 );
2116
2117 snd_azf3328_dbgmisc("game %02x %02x %02x %02x %02x %02x\n",
2118 snd_azf3328_game_inb(chip, 0),
2119 snd_azf3328_game_inb(chip, 1),
2120 snd_azf3328_game_inb(chip, 2),
2121 snd_azf3328_game_inb(chip, 3),
2122 snd_azf3328_game_inb(chip, 4),
2123 snd_azf3328_game_inb(chip, 5)
2124 );
2125
2126 for (tmp = 0; tmp < 0x07; tmp += 1)
2127 snd_azf3328_dbgmisc("mpu_io 0x%04x\n", inb(chip->mpu_io + tmp));
2128
2129 for (tmp = 0; tmp <= 0x07; tmp += 1)
2130 snd_azf3328_dbgmisc("0x%02x: game200 0x%04x, game208 0x%04x\n",
2131 tmp, inb(0x200 + tmp), inb(0x208 + tmp));
2132
2133 for (tmp = 0; tmp <= 0x01; tmp += 1)
2134 snd_azf3328_dbgmisc(
2135 "0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, "
2136 "mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n",
2137 tmp,
2138 inb(0x300 + tmp),
2139 inb(0x310 + tmp),
2140 inb(0x320 + tmp),
2141 inb(0x330 + tmp),
2142 inb(0x388 + tmp),
2143 inb(0x38c + tmp)
2144 );
2145
2146 for (tmp = 0; tmp < AZF_IO_SIZE_CTRL; tmp += 2)
2147 snd_azf3328_dbgmisc("ctrl 0x%02x: 0x%04x\n",
2148 tmp, snd_azf3328_ctrl_inw(chip, tmp)
2149 );
2150
2151 for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2)
2152 snd_azf3328_dbgmisc("mixer 0x%02x: 0x%04x\n",
2153 tmp, snd_azf3328_mixer_inw(chip, tmp)
2154 );
2155#endif
2156}
2157
2158static int __devinit
2159snd_azf3328_create(struct snd_card *card,
2160 struct pci_dev *pci,
2161 unsigned long device_type,
2162 struct snd_azf3328 **rchip)
2163{
2164 struct snd_azf3328 *chip;
2165 int err;
2166 static struct snd_device_ops ops = {
2167 .dev_free = snd_azf3328_dev_free,
2168 };
2169 u8 dma_init;
2170 enum snd_azf3328_codec_type codec_type;
2171 struct snd_azf3328_codec_data *codec_setup;
2172
2173 *rchip = NULL;
2174
2175 err = pci_enable_device(pci);
2176 if (err < 0)
2177 return err;
2178
2179 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2180 if (chip == NULL) {
2181 err = -ENOMEM;
2182 goto out_err;
2183 }
2184 spin_lock_init(&chip->reg_lock);
2185 chip->card = card;
2186 chip->pci = pci;
2187 chip->irq = -1;
2188
2189
2190 if (pci_set_dma_mask(pci, DMA_BIT_MASK(24)) < 0 ||
2191 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(24)) < 0) {
2192 snd_printk(KERN_ERR "architecture does not support "
2193 "24bit PCI busmaster DMA\n"
2194 );
2195 err = -ENXIO;
2196 goto out_err;
2197 }
2198
2199 err = pci_request_regions(pci, "Aztech AZF3328");
2200 if (err < 0)
2201 goto out_err;
2202
2203 chip->ctrl_io = pci_resource_start(pci, 0);
2204 chip->game_io = pci_resource_start(pci, 1);
2205 chip->mpu_io = pci_resource_start(pci, 2);
2206 chip->opl3_io = pci_resource_start(pci, 3);
2207 chip->mixer_io = pci_resource_start(pci, 4);
2208
2209 codec_setup = &chip->codecs[AZF_CODEC_PLAYBACK];
2210 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK;
2211 codec_setup->lock = &chip->reg_lock;
2212 codec_setup->type = AZF_CODEC_PLAYBACK;
2213 codec_setup->name = "PLAYBACK";
2214
2215 codec_setup = &chip->codecs[AZF_CODEC_CAPTURE];
2216 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE;
2217 codec_setup->lock = &chip->reg_lock;
2218 codec_setup->type = AZF_CODEC_CAPTURE;
2219 codec_setup->name = "CAPTURE";
2220
2221 codec_setup = &chip->codecs[AZF_CODEC_I2S_OUT];
2222 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT;
2223 codec_setup->lock = &chip->reg_lock;
2224 codec_setup->type = AZF_CODEC_I2S_OUT;
2225 codec_setup->name = "I2S_OUT";
2226
2227 if (request_irq(pci->irq, snd_azf3328_interrupt,
2228 IRQF_SHARED, card->shortname, chip)) {
2229 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2230 err = -EBUSY;
2231 goto out_err;
2232 }
2233 chip->irq = pci->irq;
2234 pci_set_master(pci);
2235 synchronize_irq(chip->irq);
2236
2237 snd_azf3328_debug_show_ports(chip);
2238
2239 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2240 if (err < 0)
2241 goto out_err;
2242
2243
2244 err = snd_azf3328_mixer_new(chip);
2245 if (err < 0)
2246 goto out_err;
2247
2248
2249
2250 dma_init = DMA_RUN_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
2251
2252 for (codec_type = AZF_CODEC_PLAYBACK;
2253 codec_type <= AZF_CODEC_I2S_OUT; ++codec_type) {
2254 struct snd_azf3328_codec_data *codec =
2255 &chip->codecs[codec_type];
2256
2257
2258
2259 codec->running = 1;
2260 snd_azf3328_ctrl_codec_activity(chip, codec_type, 0);
2261
2262 spin_lock_irq(codec->lock);
2263 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_DMA_FLAGS,
2264 dma_init);
2265 spin_unlock_irq(codec->lock);
2266 }
2267
2268 snd_card_set_dev(card, &pci->dev);
2269
2270 *rchip = chip;
2271
2272 err = 0;
2273 goto out;
2274
2275out_err:
2276 if (chip)
2277 snd_azf3328_free(chip);
2278 pci_disable_device(pci);
2279
2280out:
2281 return err;
2282}
2283
2284static int __devinit
2285snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2286{
2287 static int dev;
2288 struct snd_card *card;
2289 struct snd_azf3328 *chip;
2290 struct snd_opl3 *opl3;
2291 int err;
2292
2293 snd_azf3328_dbgcallenter();
2294 if (dev >= SNDRV_CARDS)
2295 return -ENODEV;
2296 if (!enable[dev]) {
2297 dev++;
2298 return -ENOENT;
2299 }
2300
2301 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2302 if (err < 0)
2303 return err;
2304
2305 strcpy(card->driver, "AZF3328");
2306 strcpy(card->shortname, "Aztech AZF3328 (PCI168)");
2307
2308 err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip);
2309 if (err < 0)
2310 goto out_err;
2311
2312 card->private_data = chip;
2313
2314
2315
2316 err = snd_mpu401_uart_new(
2317 card, 0,
2318 MPU401_HW_AZT2320, chip->mpu_io, MPU401_INFO_INTEGRATED,
2319 pci->irq, 0, &chip->rmidi
2320 );
2321 if (err < 0) {
2322 snd_printk(KERN_ERR "azf3328: no MPU-401 device at 0x%lx?\n",
2323 chip->mpu_io
2324 );
2325 goto out_err;
2326 }
2327
2328 err = snd_azf3328_timer(chip, 0);
2329 if (err < 0)
2330 goto out_err;
2331
2332 err = snd_azf3328_pcm(chip);
2333 if (err < 0)
2334 goto out_err;
2335
2336 if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2,
2337 OPL3_HW_AUTO, 1, &opl3) < 0) {
2338 snd_printk(KERN_ERR "azf3328: no OPL3 device at 0x%lx-0x%lx?\n",
2339 chip->opl3_io, chip->opl3_io+2
2340 );
2341 } else {
2342
2343 err = snd_opl3_timer_new(opl3, 1, 2);
2344 if (err < 0)
2345 goto out_err;
2346 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
2347 if (err < 0)
2348 goto out_err;
2349 }
2350
2351 opl3->private_data = chip;
2352
2353 sprintf(card->longname, "%s at 0x%lx, irq %i",
2354 card->shortname, chip->ctrl_io, chip->irq);
2355
2356 err = snd_card_register(card);
2357 if (err < 0)
2358 goto out_err;
2359
2360#ifdef MODULE
2361 printk(KERN_INFO
2362"azt3328: Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n"
2363"azt3328: Hardware was completely undocumented, unfortunately.\n"
2364"azt3328: Feel free to contact andi AT lisas.de for bug reports etc.!\n"
2365"azt3328: User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
2366 1024000 / seqtimer_scaling, seqtimer_scaling);
2367#endif
2368
2369 snd_azf3328_gameport(chip, dev);
2370
2371 pci_set_drvdata(pci, card);
2372 dev++;
2373
2374 err = 0;
2375 goto out;
2376
2377out_err:
2378 snd_printk(KERN_ERR "azf3328: something failed, exiting\n");
2379 snd_card_free(card);
2380
2381out:
2382 snd_azf3328_dbgcallleave();
2383 return err;
2384}
2385
2386static void __devexit
2387snd_azf3328_remove(struct pci_dev *pci)
2388{
2389 snd_azf3328_dbgcallenter();
2390 snd_card_free(pci_get_drvdata(pci));
2391 pci_set_drvdata(pci, NULL);
2392 snd_azf3328_dbgcallleave();
2393}
2394
2395#ifdef CONFIG_PM
2396static inline void
2397snd_azf3328_suspend_regs(unsigned long io_addr, unsigned count, u32 *saved_regs)
2398{
2399 unsigned reg;
2400
2401 for (reg = 0; reg < count; ++reg) {
2402 *saved_regs = inl(io_addr);
2403 snd_azf3328_dbgpm("suspend: io 0x%04lx: 0x%08x\n",
2404 io_addr, *saved_regs);
2405 ++saved_regs;
2406 io_addr += sizeof(*saved_regs);
2407 }
2408}
2409
2410static int
2411snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state)
2412{
2413 struct snd_card *card = pci_get_drvdata(pci);
2414 struct snd_azf3328 *chip = card->private_data;
2415 u16 *saved_regs_ctrl_u16;
2416
2417 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2418
2419
2420 snd_pcm_suspend_all(chip->pcm[AZF_CODEC_PLAYBACK]);
2421 snd_pcm_suspend_all(chip->pcm[AZF_CODEC_I2S_OUT]);
2422
2423 snd_azf3328_suspend_regs(chip->mixer_io,
2424 ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer);
2425
2426
2427 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
2428 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
2429
2430 snd_azf3328_suspend_regs(chip->ctrl_io,
2431 ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl);
2432
2433
2434 saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl;
2435 saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH;
2436
2437 snd_azf3328_suspend_regs(chip->game_io,
2438 ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game);
2439 snd_azf3328_suspend_regs(chip->mpu_io,
2440 ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu);
2441 snd_azf3328_suspend_regs(chip->opl3_io,
2442 ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3);
2443
2444 pci_disable_device(pci);
2445 pci_save_state(pci);
2446 pci_set_power_state(pci, pci_choose_state(pci, state));
2447 return 0;
2448}
2449
2450static inline void
2451snd_azf3328_resume_regs(const u32 *saved_regs,
2452 unsigned long io_addr,
2453 unsigned count
2454)
2455{
2456 unsigned reg;
2457
2458 for (reg = 0; reg < count; ++reg) {
2459 outl(*saved_regs, io_addr);
2460 snd_azf3328_dbgpm("resume: io 0x%04lx: 0x%08x --> 0x%08x\n",
2461 io_addr, *saved_regs, inl(io_addr));
2462 ++saved_regs;
2463 io_addr += sizeof(*saved_regs);
2464 }
2465}
2466
2467static int
2468snd_azf3328_resume(struct pci_dev *pci)
2469{
2470 struct snd_card *card = pci_get_drvdata(pci);
2471 const struct snd_azf3328 *chip = card->private_data;
2472
2473 pci_set_power_state(pci, PCI_D0);
2474 pci_restore_state(pci);
2475 if (pci_enable_device(pci) < 0) {
2476 printk(KERN_ERR "azt3328: pci_enable_device failed, "
2477 "disabling device\n");
2478 snd_card_disconnect(card);
2479 return -EIO;
2480 }
2481 pci_set_master(pci);
2482
2483 snd_azf3328_resume_regs(chip->saved_regs_game, chip->game_io,
2484 ARRAY_SIZE(chip->saved_regs_game));
2485 snd_azf3328_resume_regs(chip->saved_regs_mpu, chip->mpu_io,
2486 ARRAY_SIZE(chip->saved_regs_mpu));
2487 snd_azf3328_resume_regs(chip->saved_regs_opl3, chip->opl3_io,
2488 ARRAY_SIZE(chip->saved_regs_opl3));
2489
2490 snd_azf3328_resume_regs(chip->saved_regs_mixer, chip->mixer_io,
2491 ARRAY_SIZE(chip->saved_regs_mixer));
2492
2493
2494
2495
2496
2497 outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2);
2498
2499 snd_azf3328_resume_regs(chip->saved_regs_ctrl, chip->ctrl_io,
2500 ARRAY_SIZE(chip->saved_regs_ctrl));
2501
2502 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2503 return 0;
2504}
2505#endif
2506
2507
2508static struct pci_driver driver = {
2509 .name = "AZF3328",
2510 .id_table = snd_azf3328_ids,
2511 .probe = snd_azf3328_probe,
2512 .remove = __devexit_p(snd_azf3328_remove),
2513#ifdef CONFIG_PM
2514 .suspend = snd_azf3328_suspend,
2515 .resume = snd_azf3328_resume,
2516#endif
2517};
2518
2519static int __init
2520alsa_card_azf3328_init(void)
2521{
2522 int err;
2523 snd_azf3328_dbgcallenter();
2524 err = pci_register_driver(&driver);
2525 snd_azf3328_dbgcallleave();
2526 return err;
2527}
2528
2529static void __exit
2530alsa_card_azf3328_exit(void)
2531{
2532 snd_azf3328_dbgcallenter();
2533 pci_unregister_driver(&driver);
2534 snd_azf3328_dbgcallleave();
2535}
2536
2537module_init(alsa_card_azf3328_init)
2538module_exit(alsa_card_azf3328_exit)
2539