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17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/init.h>
20#include <linux/completion.h>
21#include <linux/delay.h>
22#include <linux/pm.h>
23#include <linux/i2c.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26#include <sound/core.h>
27#include <sound/jack.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/tlv.h>
31#include <sound/soc.h>
32#include <sound/initval.h>
33#include <sound/wm8903.h>
34#include <trace/events/asoc.h>
35
36#include "wm8903.h"
37
38
39static u16 wm8903_reg_defaults[] = {
40 0x8903,
41 0x0000,
42 0x0000,
43 0x0000,
44 0x0018,
45 0x0000,
46 0x0000,
47 0x0000,
48 0x0001,
49 0x0000,
50 0x0001,
51 0x0000,
52 0x0000,
53 0x0000,
54 0x0000,
55 0x0000,
56 0x0000,
57 0x0000,
58 0x0000,
59 0x0000,
60 0x0400,
61 0x0D07,
62 0x0000,
63 0x0000,
64 0x0050,
65 0x0242,
66 0x0008,
67 0x0022,
68 0x0000,
69 0x0000,
70 0x00C0,
71 0x00C0,
72 0x0000,
73 0x0000,
74 0x0000,
75 0x0000,
76 0x00C0,
77 0x00C0,
78 0x0000,
79 0x0073,
80 0x09BF,
81 0x3241,
82 0x0020,
83 0x0000,
84 0x0085,
85 0x0085,
86 0x0044,
87 0x0044,
88 0x0000,
89 0x0000,
90 0x0008,
91 0x0004,
92 0x0000,
93 0x0000,
94 0x0000,
95 0x0000,
96 0x0000,
97 0x002D,
98 0x002D,
99 0x0039,
100 0x0039,
101 0x0100,
102 0x0139,
103 0x0139,
104 0x0000,
105 0x0000,
106 0x0000,
107 0x0010,
108 0x0100,
109 0x00A4,
110 0x0807,
111 0x0000,
112 0x0000,
113 0x0000,
114 0x0000,
115 0x0000,
116 0x0000,
117 0x0000,
118 0x0000,
119 0x000E,
120 0x0000,
121 0x0000,
122 0x0000,
123 0x0000,
124 0x0000,
125 0x0000,
126 0x0000,
127 0x0006,
128 0x0000,
129 0x0000,
130 0x0000,
131 0x0060,
132 0x0000,
133 0x0000,
134 0x0000,
135 0x0060,
136 0x0000,
137 0x0000,
138 0x0000,
139 0x1F25,
140 0x2B19,
141 0x01C0,
142 0x01EF,
143 0x2B00,
144 0x0000,
145 0x01C0,
146 0x1C10,
147 0x0000,
148 0x0000,
149 0x0000,
150 0x0000,
151 0x0000,
152 0x0000,
153 0x0000,
154 0x0000,
155 0x0000,
156 0x00A8,
157 0x00A8,
158 0x00A8,
159 0x0220,
160 0x01A0,
161 0x0000,
162 0xFFFF,
163 0x0000,
164 0x0000,
165 0x0003,
166 0x0000,
167 0x0000,
168 0x0005,
169 0x0000,
170 0x0000,
171 0x0000,
172 0x0000,
173 0x0000,
174 0x0000,
175 0x03FF,
176 0x0007,
177 0x0040,
178 0x0000,
179 0x0000,
180 0x0000,
181 0x0000,
182 0x0000,
183 0x0000,
184 0x0000,
185 0x0000,
186 0x0000,
187 0x0000,
188 0x4000,
189 0x6810,
190 0x0004,
191 0x0000,
192 0x0000,
193 0x0000,
194 0x0000,
195 0x0000,
196 0x0000,
197 0x0000,
198 0x0000,
199 0x0000,
200 0x0000,
201 0x0000,
202 0x0000,
203 0x0000,
204 0x0028,
205 0x0004,
206 0x0000,
207 0x0060,
208 0x0000,
209 0x0000,
210 0x0000,
211 0x0000,
212 0x0000,
213};
214
215struct wm8903_priv {
216
217 int sysclk;
218 int irq;
219
220 int fs;
221 int deemph;
222
223
224 int class_w_users;
225
226 struct completion wseq;
227
228 struct snd_soc_jack *mic_jack;
229 int mic_det;
230 int mic_short;
231 int mic_last_report;
232 int mic_delay;
233};
234
235static int wm8903_volatile_register(unsigned int reg)
236{
237 switch (reg) {
238 case WM8903_SW_RESET_AND_ID:
239 case WM8903_REVISION_NUMBER:
240 case WM8903_INTERRUPT_STATUS_1:
241 case WM8903_WRITE_SEQUENCER_4:
242 return 1;
243
244 default:
245 return 0;
246 }
247}
248
249static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
250{
251 u16 reg[5];
252 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
253
254 BUG_ON(start > 48);
255
256
257 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
258 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
259 reg[0] | WM8903_WSEQ_ENA);
260
261 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
262
263 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
264 start | WM8903_WSEQ_START);
265
266
267
268
269 do {
270 wait_for_completion_timeout(&wm8903->wseq,
271 msecs_to_jiffies(10));
272
273 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
274 } while (reg[4] & WM8903_WSEQ_BUSY);
275
276 dev_dbg(codec->dev, "Sequence complete\n");
277
278
279 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
280
281 return 0;
282}
283
284static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
285{
286 int i;
287
288
289 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
290 cache[i] = codec->hw_read(codec, i);
291}
292
293static void wm8903_reset(struct snd_soc_codec *codec)
294{
295 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
296 memcpy(codec->reg_cache, wm8903_reg_defaults,
297 sizeof(wm8903_reg_defaults));
298}
299
300#define WM8903_OUTPUT_SHORT 0x8
301#define WM8903_OUTPUT_OUT 0x4
302#define WM8903_OUTPUT_INT 0x2
303#define WM8903_OUTPUT_IN 0x1
304
305static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
306 struct snd_kcontrol *kcontrol, int event)
307{
308 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
309 mdelay(4);
310
311 return 0;
312}
313
314
315
316
317
318
319static int wm8903_output_event(struct snd_soc_dapm_widget *w,
320 struct snd_kcontrol *kcontrol, int event)
321{
322 struct snd_soc_codec *codec = w->codec;
323 u16 val;
324 u16 reg;
325 u16 dcs_reg;
326 u16 dcs_bit;
327 int shift;
328
329 switch (w->reg) {
330 case WM8903_POWER_MANAGEMENT_2:
331 reg = WM8903_ANALOGUE_HP_0;
332 dcs_bit = 0 + w->shift;
333 break;
334 case WM8903_POWER_MANAGEMENT_3:
335 reg = WM8903_ANALOGUE_LINEOUT_0;
336 dcs_bit = 2 + w->shift;
337 break;
338 default:
339 BUG();
340 return -EINVAL;
341 }
342
343 switch (w->shift) {
344 case 0:
345 shift = 0;
346 break;
347 case 1:
348 shift = 4;
349 break;
350 default:
351 BUG();
352 return -EINVAL;
353 }
354
355 if (event & SND_SOC_DAPM_PRE_PMU) {
356 val = snd_soc_read(codec, reg);
357
358
359 val &= ~(WM8903_OUTPUT_SHORT << shift);
360 snd_soc_write(codec, reg, val);
361 }
362
363 if (event & SND_SOC_DAPM_POST_PMU) {
364 val = snd_soc_read(codec, reg);
365
366 val |= (WM8903_OUTPUT_IN << shift);
367 snd_soc_write(codec, reg, val);
368
369 val |= (WM8903_OUTPUT_INT << shift);
370 snd_soc_write(codec, reg, val);
371
372
373 val |= (WM8903_OUTPUT_OUT << shift);
374 snd_soc_write(codec, reg, val);
375
376
377 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
378 dcs_reg |= dcs_bit;
379 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
380
381
382 val |= (WM8903_OUTPUT_SHORT << shift);
383 snd_soc_write(codec, reg, val);
384 }
385
386 if (event & SND_SOC_DAPM_PRE_PMD) {
387 val = snd_soc_read(codec, reg);
388
389
390 val &= ~(WM8903_OUTPUT_SHORT << shift);
391 snd_soc_write(codec, reg, val);
392
393
394 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
395 dcs_reg &= ~dcs_bit;
396 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
397
398
399 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
400 WM8903_OUTPUT_IN) << shift);
401 snd_soc_write(codec, reg, val);
402 }
403
404 return 0;
405}
406
407
408
409
410
411
412
413
414
415static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
416 struct snd_ctl_elem_value *ucontrol)
417{
418 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
419 struct snd_soc_codec *codec = widget->codec;
420 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
421 u16 reg;
422 int ret;
423
424 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
425
426
427 if (ucontrol->value.integer.value[0]) {
428 if (wm8903->class_w_users == 0) {
429 dev_dbg(codec->dev, "Disabling Class W\n");
430 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
431 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
432 }
433 wm8903->class_w_users++;
434 }
435
436
437 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
438
439
440 if (!ucontrol->value.integer.value[0]) {
441 if (wm8903->class_w_users == 1) {
442 dev_dbg(codec->dev, "Enabling Class W\n");
443 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
444 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
445 }
446 wm8903->class_w_users--;
447 }
448
449 dev_dbg(codec->dev, "Bypass use count now %d\n",
450 wm8903->class_w_users);
451
452 return ret;
453}
454
455#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
456{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
457 .info = snd_soc_info_volsw, \
458 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
459 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
460
461
462static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
463
464static int wm8903_set_deemph(struct snd_soc_codec *codec)
465{
466 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
467 int val, i, best;
468
469
470
471
472 if (wm8903->deemph) {
473 best = 1;
474 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
475 if (abs(wm8903_deemph[i] - wm8903->fs) <
476 abs(wm8903_deemph[best] - wm8903->fs))
477 best = i;
478 }
479
480 val = best << WM8903_DEEMPH_SHIFT;
481 } else {
482 best = 0;
483 val = 0;
484 }
485
486 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
487 best, wm8903_deemph[best]);
488
489 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
490 WM8903_DEEMPH_MASK, val);
491}
492
493static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
494 struct snd_ctl_elem_value *ucontrol)
495{
496 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
497 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
498
499 ucontrol->value.enumerated.item[0] = wm8903->deemph;
500
501 return 0;
502}
503
504static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
505 struct snd_ctl_elem_value *ucontrol)
506{
507 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
508 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
509 int deemph = ucontrol->value.enumerated.item[0];
510 int ret = 0;
511
512 if (deemph > 1)
513 return -EINVAL;
514
515 mutex_lock(&codec->mutex);
516 if (wm8903->deemph != deemph) {
517 wm8903->deemph = deemph;
518
519 wm8903_set_deemph(codec);
520
521 ret = 1;
522 }
523 mutex_unlock(&codec->mutex);
524
525 return ret;
526}
527
528
529static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
530
531static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
532static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
533
534static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
535static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
536static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
537static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
538static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
539
540static const char *hpf_mode_text[] = {
541 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
542};
543
544static const struct soc_enum hpf_mode =
545 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
546
547static const char *osr_text[] = {
548 "Low power", "High performance"
549};
550
551static const struct soc_enum adc_osr =
552 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
553
554static const struct soc_enum dac_osr =
555 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
556
557static const char *drc_slope_text[] = {
558 "1", "1/2", "1/4", "1/8", "1/16", "0"
559};
560
561static const struct soc_enum drc_slope_r0 =
562 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
563
564static const struct soc_enum drc_slope_r1 =
565 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
566
567static const char *drc_attack_text[] = {
568 "instantaneous",
569 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
570 "46.4ms", "92.8ms", "185.6ms"
571};
572
573static const struct soc_enum drc_attack =
574 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
575
576static const char *drc_decay_text[] = {
577 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
578 "23.87s", "47.56s"
579};
580
581static const struct soc_enum drc_decay =
582 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
583
584static const char *drc_ff_delay_text[] = {
585 "5 samples", "9 samples"
586};
587
588static const struct soc_enum drc_ff_delay =
589 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
590
591static const char *drc_qr_decay_text[] = {
592 "0.725ms", "1.45ms", "5.8ms"
593};
594
595static const struct soc_enum drc_qr_decay =
596 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
597
598static const char *drc_smoothing_text[] = {
599 "Low", "Medium", "High"
600};
601
602static const struct soc_enum drc_smoothing =
603 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
604
605static const char *soft_mute_text[] = {
606 "Fast (fs/2)", "Slow (fs/32)"
607};
608
609static const struct soc_enum soft_mute =
610 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
611
612static const char *mute_mode_text[] = {
613 "Hard", "Soft"
614};
615
616static const struct soc_enum mute_mode =
617 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
618
619static const char *companding_text[] = {
620 "ulaw", "alaw"
621};
622
623static const struct soc_enum dac_companding =
624 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
625
626static const struct soc_enum adc_companding =
627 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
628
629static const char *input_mode_text[] = {
630 "Single-Ended", "Differential Line", "Differential Mic"
631};
632
633static const struct soc_enum linput_mode_enum =
634 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
635
636static const struct soc_enum rinput_mode_enum =
637 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
638
639static const char *linput_mux_text[] = {
640 "IN1L", "IN2L", "IN3L"
641};
642
643static const struct soc_enum linput_enum =
644 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
645
646static const struct soc_enum linput_inv_enum =
647 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
648
649static const char *rinput_mux_text[] = {
650 "IN1R", "IN2R", "IN3R"
651};
652
653static const struct soc_enum rinput_enum =
654 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
655
656static const struct soc_enum rinput_inv_enum =
657 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
658
659
660static const char *sidetone_text[] = {
661 "None", "Left", "Right"
662};
663
664static const struct soc_enum lsidetone_enum =
665 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
666
667static const struct soc_enum rsidetone_enum =
668 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
669
670static const struct snd_kcontrol_new wm8903_snd_controls[] = {
671
672
673SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
674 7, 1, 1),
675SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
676 0, 31, 0),
677SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
678 6, 1, 0),
679
680SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
681 7, 1, 1),
682SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
683 0, 31, 0),
684SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
685 6, 1, 0),
686
687
688SOC_ENUM("ADC OSR", adc_osr),
689SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
690SOC_ENUM("HPF Mode", hpf_mode),
691SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
692SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
693SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
694SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
695 drc_tlv_thresh),
696SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
697SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
698SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
699SOC_ENUM("DRC Attack Rate", drc_attack),
700SOC_ENUM("DRC Decay Rate", drc_decay),
701SOC_ENUM("DRC FF Delay", drc_ff_delay),
702SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
703SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
704SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
705SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
706SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
707SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
708SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
709SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
710
711SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
712 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
713SOC_ENUM("ADC Companding Mode", adc_companding),
714SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
715
716SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
717 12, 0, digital_sidetone_tlv),
718
719
720SOC_ENUM("DAC OSR", dac_osr),
721SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
722 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
723SOC_ENUM("DAC Soft Mute Rate", soft_mute),
724SOC_ENUM("DAC Mute Mode", mute_mode),
725SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
726SOC_ENUM("DAC Companding Mode", dac_companding),
727SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
728SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
729 wm8903_get_deemph, wm8903_put_deemph),
730
731
732SOC_DOUBLE_R("Headphone Switch",
733 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
734 8, 1, 1),
735SOC_DOUBLE_R("Headphone ZC Switch",
736 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
737 6, 1, 0),
738SOC_DOUBLE_R_TLV("Headphone Volume",
739 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
740 0, 63, 0, out_tlv),
741
742
743SOC_DOUBLE_R("Line Out Switch",
744 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
745 8, 1, 1),
746SOC_DOUBLE_R("Line Out ZC Switch",
747 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
748 6, 1, 0),
749SOC_DOUBLE_R_TLV("Line Out Volume",
750 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
751 0, 63, 0, out_tlv),
752
753
754SOC_DOUBLE_R("Speaker Switch",
755 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
756SOC_DOUBLE_R("Speaker ZC Switch",
757 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
758SOC_DOUBLE_R_TLV("Speaker Volume",
759 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
760 0, 63, 0, out_tlv),
761};
762
763static const struct snd_kcontrol_new linput_mode_mux =
764 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
765
766static const struct snd_kcontrol_new rinput_mode_mux =
767 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
768
769static const struct snd_kcontrol_new linput_mux =
770 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
771
772static const struct snd_kcontrol_new linput_inv_mux =
773 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
774
775static const struct snd_kcontrol_new rinput_mux =
776 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
777
778static const struct snd_kcontrol_new rinput_inv_mux =
779 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
780
781static const struct snd_kcontrol_new lsidetone_mux =
782 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
783
784static const struct snd_kcontrol_new rsidetone_mux =
785 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
786
787static const struct snd_kcontrol_new left_output_mixer[] = {
788SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
789SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
790SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
791SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
792};
793
794static const struct snd_kcontrol_new right_output_mixer[] = {
795SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
796SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
797SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
798SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
799};
800
801static const struct snd_kcontrol_new left_speaker_mixer[] = {
802SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
803SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
804SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
805SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
806 0, 1, 0),
807};
808
809static const struct snd_kcontrol_new right_speaker_mixer[] = {
810SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
811SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
812SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
813 1, 1, 0),
814SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
815 0, 1, 0),
816};
817
818static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
819SND_SOC_DAPM_INPUT("IN1L"),
820SND_SOC_DAPM_INPUT("IN1R"),
821SND_SOC_DAPM_INPUT("IN2L"),
822SND_SOC_DAPM_INPUT("IN2R"),
823SND_SOC_DAPM_INPUT("IN3L"),
824SND_SOC_DAPM_INPUT("IN3R"),
825
826SND_SOC_DAPM_OUTPUT("HPOUTL"),
827SND_SOC_DAPM_OUTPUT("HPOUTR"),
828SND_SOC_DAPM_OUTPUT("LINEOUTL"),
829SND_SOC_DAPM_OUTPUT("LINEOUTR"),
830SND_SOC_DAPM_OUTPUT("LOP"),
831SND_SOC_DAPM_OUTPUT("LON"),
832SND_SOC_DAPM_OUTPUT("ROP"),
833SND_SOC_DAPM_OUTPUT("RON"),
834
835SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
836
837SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
838SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
839 &linput_inv_mux),
840SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
841
842SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
843SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
844 &rinput_inv_mux),
845SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
846
847SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
848SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
849
850SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
851SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
852
853SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
854SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
855
856SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
857SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
858
859SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
860 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
861SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
862 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
863
864SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
865 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
866SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
867 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
868
869SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
870 1, 0, NULL, 0, wm8903_output_event,
871 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
872 SND_SOC_DAPM_PRE_PMD),
873SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
874 0, 0, NULL, 0, wm8903_output_event,
875 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
876 SND_SOC_DAPM_PRE_PMD),
877
878SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
879 NULL, 0, wm8903_output_event,
880 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
881 SND_SOC_DAPM_PRE_PMD),
882SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
883 NULL, 0, wm8903_output_event,
884 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
885 SND_SOC_DAPM_PRE_PMD),
886
887SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
888 NULL, 0),
889SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
890 NULL, 0),
891
892SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
893 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
894SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
895};
896
897static const struct snd_soc_dapm_route intercon[] = {
898
899 { "Left Input Mux", "IN1L", "IN1L" },
900 { "Left Input Mux", "IN2L", "IN2L" },
901 { "Left Input Mux", "IN3L", "IN3L" },
902
903 { "Left Input Inverting Mux", "IN1L", "IN1L" },
904 { "Left Input Inverting Mux", "IN2L", "IN2L" },
905 { "Left Input Inverting Mux", "IN3L", "IN3L" },
906
907 { "Right Input Mux", "IN1R", "IN1R" },
908 { "Right Input Mux", "IN2R", "IN2R" },
909 { "Right Input Mux", "IN3R", "IN3R" },
910
911 { "Right Input Inverting Mux", "IN1R", "IN1R" },
912 { "Right Input Inverting Mux", "IN2R", "IN2R" },
913 { "Right Input Inverting Mux", "IN3R", "IN3R" },
914
915 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
916 { "Left Input Mode Mux", "Differential Line",
917 "Left Input Mux" },
918 { "Left Input Mode Mux", "Differential Line",
919 "Left Input Inverting Mux" },
920 { "Left Input Mode Mux", "Differential Mic",
921 "Left Input Mux" },
922 { "Left Input Mode Mux", "Differential Mic",
923 "Left Input Inverting Mux" },
924
925 { "Right Input Mode Mux", "Single-Ended",
926 "Right Input Inverting Mux" },
927 { "Right Input Mode Mux", "Differential Line",
928 "Right Input Mux" },
929 { "Right Input Mode Mux", "Differential Line",
930 "Right Input Inverting Mux" },
931 { "Right Input Mode Mux", "Differential Mic",
932 "Right Input Mux" },
933 { "Right Input Mode Mux", "Differential Mic",
934 "Right Input Inverting Mux" },
935
936 { "Left Input PGA", NULL, "Left Input Mode Mux" },
937 { "Right Input PGA", NULL, "Right Input Mode Mux" },
938
939 { "ADCL", NULL, "Left Input PGA" },
940 { "ADCL", NULL, "CLK_DSP" },
941 { "ADCR", NULL, "Right Input PGA" },
942 { "ADCR", NULL, "CLK_DSP" },
943
944 { "DACL Sidetone", "Left", "ADCL" },
945 { "DACL Sidetone", "Right", "ADCR" },
946 { "DACR Sidetone", "Left", "ADCL" },
947 { "DACR Sidetone", "Right", "ADCR" },
948
949 { "DACL", NULL, "DACL Sidetone" },
950 { "DACL", NULL, "CLK_DSP" },
951 { "DACR", NULL, "DACR Sidetone" },
952 { "DACR", NULL, "CLK_DSP" },
953
954 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
955 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
956 { "Left Output Mixer", "DACL Switch", "DACL" },
957 { "Left Output Mixer", "DACR Switch", "DACR" },
958
959 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
960 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
961 { "Right Output Mixer", "DACL Switch", "DACL" },
962 { "Right Output Mixer", "DACR Switch", "DACR" },
963
964 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
965 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
966 { "Left Speaker Mixer", "DACL Switch", "DACL" },
967 { "Left Speaker Mixer", "DACR Switch", "DACR" },
968
969 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
970 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
971 { "Right Speaker Mixer", "DACL Switch", "DACL" },
972 { "Right Speaker Mixer", "DACR Switch", "DACR" },
973
974 { "Left Line Output PGA", NULL, "Left Output Mixer" },
975 { "Right Line Output PGA", NULL, "Right Output Mixer" },
976
977 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
978 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
979
980 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
981 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
982
983 { "HPOUTL", NULL, "Left Headphone Output PGA" },
984 { "HPOUTR", NULL, "Right Headphone Output PGA" },
985
986 { "LINEOUTL", NULL, "Left Line Output PGA" },
987 { "LINEOUTR", NULL, "Right Line Output PGA" },
988
989 { "LOP", NULL, "Left Speaker PGA" },
990 { "LON", NULL, "Left Speaker PGA" },
991
992 { "ROP", NULL, "Right Speaker PGA" },
993 { "RON", NULL, "Right Speaker PGA" },
994
995 { "Left Headphone Output PGA", NULL, "Charge Pump" },
996 { "Right Headphone Output PGA", NULL, "Charge Pump" },
997 { "Left Line Output PGA", NULL, "Charge Pump" },
998 { "Right Line Output PGA", NULL, "Charge Pump" },
999};
1000
1001static int wm8903_add_widgets(struct snd_soc_codec *codec)
1002{
1003 struct snd_soc_dapm_context *dapm = &codec->dapm;
1004
1005 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
1006 ARRAY_SIZE(wm8903_dapm_widgets));
1007 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
1008
1009 return 0;
1010}
1011
1012static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1013 enum snd_soc_bias_level level)
1014{
1015 u16 reg;
1016
1017 switch (level) {
1018 case SND_SOC_BIAS_ON:
1019 case SND_SOC_BIAS_PREPARE:
1020 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
1021 reg &= ~(WM8903_VMID_RES_MASK);
1022 reg |= WM8903_VMID_RES_50K;
1023 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
1024 break;
1025
1026 case SND_SOC_BIAS_STANDBY:
1027 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1028 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
1029 WM8903_CLK_SYS_ENA);
1030
1031
1032 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1033 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1034 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
1035
1036 wm8903_run_sequence(codec, 0);
1037 wm8903_sync_reg_cache(codec, codec->reg_cache);
1038
1039
1040
1041
1042 dev_dbg(codec->dev, "Enabling Class W\n");
1043 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1044 WM8903_CP_DYN_FREQ |
1045 WM8903_CP_DYN_V,
1046 WM8903_CP_DYN_FREQ |
1047 WM8903_CP_DYN_V);
1048 }
1049
1050 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
1051 reg &= ~(WM8903_VMID_RES_MASK);
1052 reg |= WM8903_VMID_RES_250K;
1053 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
1054 break;
1055
1056 case SND_SOC_BIAS_OFF:
1057 wm8903_run_sequence(codec, 32);
1058 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
1059 reg &= ~WM8903_CLK_SYS_ENA;
1060 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
1061 break;
1062 }
1063
1064 codec->dapm.bias_level = level;
1065
1066 return 0;
1067}
1068
1069static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1070 int clk_id, unsigned int freq, int dir)
1071{
1072 struct snd_soc_codec *codec = codec_dai->codec;
1073 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1074
1075 wm8903->sysclk = freq;
1076
1077 return 0;
1078}
1079
1080static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1081 unsigned int fmt)
1082{
1083 struct snd_soc_codec *codec = codec_dai->codec;
1084 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1085
1086 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1087 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1088
1089 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1090 case SND_SOC_DAIFMT_CBS_CFS:
1091 break;
1092 case SND_SOC_DAIFMT_CBS_CFM:
1093 aif1 |= WM8903_LRCLK_DIR;
1094 break;
1095 case SND_SOC_DAIFMT_CBM_CFM:
1096 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1097 break;
1098 case SND_SOC_DAIFMT_CBM_CFS:
1099 aif1 |= WM8903_BCLK_DIR;
1100 break;
1101 default:
1102 return -EINVAL;
1103 }
1104
1105 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1106 case SND_SOC_DAIFMT_DSP_A:
1107 aif1 |= 0x3;
1108 break;
1109 case SND_SOC_DAIFMT_DSP_B:
1110 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1111 break;
1112 case SND_SOC_DAIFMT_I2S:
1113 aif1 |= 0x2;
1114 break;
1115 case SND_SOC_DAIFMT_RIGHT_J:
1116 aif1 |= 0x1;
1117 break;
1118 case SND_SOC_DAIFMT_LEFT_J:
1119 break;
1120 default:
1121 return -EINVAL;
1122 }
1123
1124
1125 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1126 case SND_SOC_DAIFMT_DSP_A:
1127 case SND_SOC_DAIFMT_DSP_B:
1128
1129 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1130 case SND_SOC_DAIFMT_NB_NF:
1131 break;
1132 case SND_SOC_DAIFMT_IB_NF:
1133 aif1 |= WM8903_AIF_BCLK_INV;
1134 break;
1135 default:
1136 return -EINVAL;
1137 }
1138 break;
1139 case SND_SOC_DAIFMT_I2S:
1140 case SND_SOC_DAIFMT_RIGHT_J:
1141 case SND_SOC_DAIFMT_LEFT_J:
1142 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1143 case SND_SOC_DAIFMT_NB_NF:
1144 break;
1145 case SND_SOC_DAIFMT_IB_IF:
1146 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1147 break;
1148 case SND_SOC_DAIFMT_IB_NF:
1149 aif1 |= WM8903_AIF_BCLK_INV;
1150 break;
1151 case SND_SOC_DAIFMT_NB_IF:
1152 aif1 |= WM8903_AIF_LRCLK_INV;
1153 break;
1154 default:
1155 return -EINVAL;
1156 }
1157 break;
1158 default:
1159 return -EINVAL;
1160 }
1161
1162 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1163
1164 return 0;
1165}
1166
1167static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1168{
1169 struct snd_soc_codec *codec = codec_dai->codec;
1170 u16 reg;
1171
1172 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1173
1174 if (mute)
1175 reg |= WM8903_DAC_MUTE;
1176 else
1177 reg &= ~WM8903_DAC_MUTE;
1178
1179 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
1180
1181 return 0;
1182}
1183
1184
1185
1186
1187static struct {
1188 int div;
1189 int rate;
1190 int mode;
1191 int mclk_div;
1192} clk_sys_ratios[] = {
1193 { 64, 0x0, 0x0, 1 },
1194 { 68, 0x0, 0x1, 1 },
1195 { 125, 0x0, 0x2, 1 },
1196 { 128, 0x1, 0x0, 1 },
1197 { 136, 0x1, 0x1, 1 },
1198 { 192, 0x2, 0x0, 1 },
1199 { 204, 0x2, 0x1, 1 },
1200
1201 { 64, 0x0, 0x0, 2 },
1202 { 68, 0x0, 0x1, 2 },
1203 { 125, 0x0, 0x2, 2 },
1204 { 128, 0x1, 0x0, 2 },
1205 { 136, 0x1, 0x1, 2 },
1206 { 192, 0x2, 0x0, 2 },
1207 { 204, 0x2, 0x1, 2 },
1208
1209 { 250, 0x2, 0x2, 1 },
1210 { 256, 0x3, 0x0, 1 },
1211 { 272, 0x3, 0x1, 1 },
1212 { 384, 0x4, 0x0, 1 },
1213 { 408, 0x4, 0x1, 1 },
1214 { 375, 0x4, 0x2, 1 },
1215 { 512, 0x5, 0x0, 1 },
1216 { 544, 0x5, 0x1, 1 },
1217 { 500, 0x5, 0x2, 1 },
1218 { 768, 0x6, 0x0, 1 },
1219 { 816, 0x6, 0x1, 1 },
1220 { 750, 0x6, 0x2, 1 },
1221 { 1024, 0x7, 0x0, 1 },
1222 { 1088, 0x7, 0x1, 1 },
1223 { 1000, 0x7, 0x2, 1 },
1224 { 1408, 0x8, 0x0, 1 },
1225 { 1496, 0x8, 0x1, 1 },
1226 { 1536, 0x9, 0x0, 1 },
1227 { 1632, 0x9, 0x1, 1 },
1228 { 1500, 0x9, 0x2, 1 },
1229
1230 { 250, 0x2, 0x2, 2 },
1231 { 256, 0x3, 0x0, 2 },
1232 { 272, 0x3, 0x1, 2 },
1233 { 384, 0x4, 0x0, 2 },
1234 { 408, 0x4, 0x1, 2 },
1235 { 375, 0x4, 0x2, 2 },
1236 { 512, 0x5, 0x0, 2 },
1237 { 544, 0x5, 0x1, 2 },
1238 { 500, 0x5, 0x2, 2 },
1239 { 768, 0x6, 0x0, 2 },
1240 { 816, 0x6, 0x1, 2 },
1241 { 750, 0x6, 0x2, 2 },
1242 { 1024, 0x7, 0x0, 2 },
1243 { 1088, 0x7, 0x1, 2 },
1244 { 1000, 0x7, 0x2, 2 },
1245 { 1408, 0x8, 0x0, 2 },
1246 { 1496, 0x8, 0x1, 2 },
1247 { 1536, 0x9, 0x0, 2 },
1248 { 1632, 0x9, 0x1, 2 },
1249 { 1500, 0x9, 0x2, 2 },
1250};
1251
1252
1253static struct {
1254 int ratio;
1255 int div;
1256} bclk_divs[] = {
1257 { 10, 0 },
1258 { 20, 2 },
1259 { 30, 3 },
1260 { 40, 4 },
1261 { 50, 5 },
1262 { 60, 7 },
1263 { 80, 8 },
1264 { 100, 9 },
1265 { 120, 11 },
1266 { 160, 12 },
1267 { 200, 13 },
1268 { 220, 14 },
1269 { 240, 15 },
1270 { 300, 17 },
1271 { 320, 18 },
1272 { 440, 19 },
1273 { 480, 20 },
1274};
1275
1276
1277static struct {
1278 int rate;
1279 int value;
1280} sample_rates[] = {
1281 { 8000, 0 },
1282 { 11025, 1 },
1283 { 12000, 2 },
1284 { 16000, 3 },
1285 { 22050, 4 },
1286 { 24000, 5 },
1287 { 32000, 6 },
1288 { 44100, 7 },
1289 { 48000, 8 },
1290 { 88200, 9 },
1291 { 96000, 10 },
1292 { 0, 0 },
1293};
1294
1295static int wm8903_hw_params(struct snd_pcm_substream *substream,
1296 struct snd_pcm_hw_params *params,
1297 struct snd_soc_dai *dai)
1298{
1299 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1300 struct snd_soc_codec *codec =rtd->codec;
1301 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1302 int fs = params_rate(params);
1303 int bclk;
1304 int bclk_div;
1305 int i;
1306 int dsp_config;
1307 int clk_config;
1308 int best_val;
1309 int cur_val;
1310 int clk_sys;
1311
1312 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1313 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1314 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1315 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1316 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1317 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1318
1319
1320 if (fs <= 24000)
1321 dac_digital1 |= WM8903_DAC_SB_FILT;
1322 else
1323 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1324
1325
1326 dsp_config = 0;
1327 best_val = abs(sample_rates[dsp_config].rate - fs);
1328 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1329 cur_val = abs(sample_rates[i].rate - fs);
1330 if (cur_val <= best_val) {
1331 dsp_config = i;
1332 best_val = cur_val;
1333 }
1334 }
1335
1336 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1337 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1338 clock1 |= sample_rates[dsp_config].value;
1339
1340 aif1 &= ~WM8903_AIF_WL_MASK;
1341 bclk = 2 * fs;
1342 switch (params_format(params)) {
1343 case SNDRV_PCM_FORMAT_S16_LE:
1344 bclk *= 16;
1345 break;
1346 case SNDRV_PCM_FORMAT_S20_3LE:
1347 bclk *= 20;
1348 aif1 |= 0x4;
1349 break;
1350 case SNDRV_PCM_FORMAT_S24_LE:
1351 bclk *= 24;
1352 aif1 |= 0x8;
1353 break;
1354 case SNDRV_PCM_FORMAT_S32_LE:
1355 bclk *= 32;
1356 aif1 |= 0xc;
1357 break;
1358 default:
1359 return -EINVAL;
1360 }
1361
1362 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1363 wm8903->sysclk, fs);
1364
1365
1366
1367
1368
1369 clk_config = 0;
1370 best_val = abs((wm8903->sysclk /
1371 (clk_sys_ratios[0].mclk_div *
1372 clk_sys_ratios[0].div)) - fs);
1373 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1374 cur_val = abs((wm8903->sysclk /
1375 (clk_sys_ratios[i].mclk_div *
1376 clk_sys_ratios[i].div)) - fs);
1377
1378 if (cur_val <= best_val) {
1379 clk_config = i;
1380 best_val = cur_val;
1381 }
1382 }
1383
1384 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1385 clock0 |= WM8903_MCLKDIV2;
1386 clk_sys = wm8903->sysclk / 2;
1387 } else {
1388 clock0 &= ~WM8903_MCLKDIV2;
1389 clk_sys = wm8903->sysclk;
1390 }
1391
1392 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1393 WM8903_CLK_SYS_MODE_MASK);
1394 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1395 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1396
1397 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1398 clk_sys_ratios[clk_config].rate,
1399 clk_sys_ratios[clk_config].mode,
1400 clk_sys_ratios[clk_config].div);
1401
1402 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1403
1404
1405
1406
1407
1408
1409 bclk_div = 0;
1410 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1411 i = 1;
1412 while (i < ARRAY_SIZE(bclk_divs)) {
1413 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1414 if (cur_val < 0)
1415 break;
1416 bclk_div = i;
1417 best_val = cur_val;
1418 i++;
1419 }
1420
1421 aif2 &= ~WM8903_BCLK_DIV_MASK;
1422 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1423
1424 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1425 bclk_divs[bclk_div].ratio / 10, bclk,
1426 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1427
1428 aif2 |= bclk_divs[bclk_div].div;
1429 aif3 |= bclk / fs;
1430
1431 wm8903->fs = params_rate(params);
1432 wm8903_set_deemph(codec);
1433
1434 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1435 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1436 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1437 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1438 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1439 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
1440
1441 return 0;
1442}
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1462 int det, int shrt)
1463{
1464 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1465 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
1466
1467 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1468 det, shrt);
1469
1470
1471 wm8903->mic_jack = jack;
1472 wm8903->mic_det = det;
1473 wm8903->mic_short = shrt;
1474
1475
1476 if (det)
1477 irq_mask &= ~WM8903_MICDET_EINT;
1478 if (shrt)
1479 irq_mask &= ~WM8903_MICSHRT_EINT;
1480
1481 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1482 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1483 irq_mask);
1484
1485 if (det || shrt) {
1486
1487
1488 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1489 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1490 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1491 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1492 } else {
1493 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1494 WM8903_MICDET_ENA, 0);
1495 }
1496
1497 return 0;
1498}
1499EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1500
1501static irqreturn_t wm8903_irq(int irq, void *data)
1502{
1503 struct snd_soc_codec *codec = data;
1504 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1505 int mic_report;
1506 int int_pol;
1507 int int_val = 0;
1508 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
1509
1510 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
1511
1512 if (int_val & WM8903_WSEQ_BUSY_EINT) {
1513 dev_dbg(codec->dev, "Write sequencer done\n");
1514 complete(&wm8903->wseq);
1515 }
1516
1517
1518
1519
1520
1521
1522
1523
1524 mic_report = wm8903->mic_last_report;
1525 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1526
1527#ifndef CONFIG_SND_SOC_WM8903_MODULE
1528 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1529 trace_snd_soc_jack_irq(dev_name(codec->dev));
1530#endif
1531
1532 if (int_val & WM8903_MICSHRT_EINT) {
1533 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1534
1535 mic_report ^= wm8903->mic_short;
1536 int_pol ^= WM8903_MICSHRT_INV;
1537 }
1538
1539 if (int_val & WM8903_MICDET_EINT) {
1540 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1541
1542 mic_report ^= wm8903->mic_det;
1543 int_pol ^= WM8903_MICDET_INV;
1544
1545 msleep(wm8903->mic_delay);
1546 }
1547
1548 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1549 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1550
1551 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1552 wm8903->mic_short | wm8903->mic_det);
1553
1554 wm8903->mic_last_report = mic_report;
1555
1556 return IRQ_HANDLED;
1557}
1558
1559#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1560 SNDRV_PCM_RATE_11025 | \
1561 SNDRV_PCM_RATE_16000 | \
1562 SNDRV_PCM_RATE_22050 | \
1563 SNDRV_PCM_RATE_32000 | \
1564 SNDRV_PCM_RATE_44100 | \
1565 SNDRV_PCM_RATE_48000 | \
1566 SNDRV_PCM_RATE_88200 | \
1567 SNDRV_PCM_RATE_96000)
1568
1569#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1570 SNDRV_PCM_RATE_11025 | \
1571 SNDRV_PCM_RATE_16000 | \
1572 SNDRV_PCM_RATE_22050 | \
1573 SNDRV_PCM_RATE_32000 | \
1574 SNDRV_PCM_RATE_44100 | \
1575 SNDRV_PCM_RATE_48000)
1576
1577#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1578 SNDRV_PCM_FMTBIT_S20_3LE |\
1579 SNDRV_PCM_FMTBIT_S24_LE)
1580
1581static struct snd_soc_dai_ops wm8903_dai_ops = {
1582 .hw_params = wm8903_hw_params,
1583 .digital_mute = wm8903_digital_mute,
1584 .set_fmt = wm8903_set_dai_fmt,
1585 .set_sysclk = wm8903_set_dai_sysclk,
1586};
1587
1588static struct snd_soc_dai_driver wm8903_dai = {
1589 .name = "wm8903-hifi",
1590 .playback = {
1591 .stream_name = "Playback",
1592 .channels_min = 2,
1593 .channels_max = 2,
1594 .rates = WM8903_PLAYBACK_RATES,
1595 .formats = WM8903_FORMATS,
1596 },
1597 .capture = {
1598 .stream_name = "Capture",
1599 .channels_min = 2,
1600 .channels_max = 2,
1601 .rates = WM8903_CAPTURE_RATES,
1602 .formats = WM8903_FORMATS,
1603 },
1604 .ops = &wm8903_dai_ops,
1605 .symmetric_rates = 1,
1606};
1607
1608static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
1609{
1610 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1611
1612 return 0;
1613}
1614
1615static int wm8903_resume(struct snd_soc_codec *codec)
1616{
1617 int i;
1618 u16 *reg_cache = codec->reg_cache;
1619 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
1620 GFP_KERNEL);
1621
1622
1623 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1624
1625
1626 if (tmp_cache) {
1627 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1628 if (tmp_cache[i] != reg_cache[i])
1629 snd_soc_write(codec, i, tmp_cache[i]);
1630 kfree(tmp_cache);
1631 } else {
1632 dev_err(codec->dev, "Failed to allocate temporary cache\n");
1633 }
1634
1635 return 0;
1636}
1637
1638static int wm8903_probe(struct snd_soc_codec *codec)
1639{
1640 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1641 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1642 int ret, i;
1643 int trigger, irq_pol;
1644 u16 val;
1645
1646 init_completion(&wm8903->wseq);
1647
1648 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1649 if (ret != 0) {
1650 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1651 return ret;
1652 }
1653
1654 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
1655 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1656 dev_err(codec->dev,
1657 "Device with ID register %x is not a WM8903\n", val);
1658 return -ENODEV;
1659 }
1660
1661 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1662 dev_info(codec->dev, "WM8903 revision %d\n",
1663 val & WM8903_CHIP_REV_MASK);
1664
1665 wm8903_reset(codec);
1666
1667
1668 if (pdata) {
1669 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1670 if (!pdata->gpio_cfg[i])
1671 continue;
1672
1673 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1674 pdata->gpio_cfg[i] & 0xffff);
1675 }
1676
1677 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1678 pdata->micdet_cfg);
1679
1680
1681 if (pdata->micdet_cfg)
1682 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1683 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1684
1685 wm8903->mic_delay = pdata->micdet_delay;
1686 }
1687
1688 if (wm8903->irq) {
1689 if (pdata && pdata->irq_active_low) {
1690 trigger = IRQF_TRIGGER_LOW;
1691 irq_pol = WM8903_IRQ_POL;
1692 } else {
1693 trigger = IRQF_TRIGGER_HIGH;
1694 irq_pol = 0;
1695 }
1696
1697 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1698 WM8903_IRQ_POL, irq_pol);
1699
1700 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
1701 trigger | IRQF_ONESHOT,
1702 "wm8903", codec);
1703 if (ret != 0) {
1704 dev_err(codec->dev, "Failed to request IRQ: %d\n",
1705 ret);
1706 return ret;
1707 }
1708
1709
1710 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1711 WM8903_IM_WSEQ_BUSY_EINT, 0);
1712 }
1713
1714
1715 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1716
1717
1718 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
1719 val |= WM8903_ADCVU;
1720 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1721 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
1722
1723 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
1724 val |= WM8903_DACVU;
1725 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1726 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
1727
1728 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
1729 val |= WM8903_HPOUTVU;
1730 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1731 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
1732
1733 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
1734 val |= WM8903_LINEOUTVU;
1735 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1736 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
1737
1738 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
1739 val |= WM8903_SPKVU;
1740 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1741 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
1742
1743
1744 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1745 val |= WM8903_DAC_MUTEMODE;
1746 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
1747
1748 snd_soc_add_controls(codec, wm8903_snd_controls,
1749 ARRAY_SIZE(wm8903_snd_controls));
1750 wm8903_add_widgets(codec);
1751
1752 return ret;
1753}
1754
1755
1756static int wm8903_remove(struct snd_soc_codec *codec)
1757{
1758 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1759 return 0;
1760}
1761
1762static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1763 .probe = wm8903_probe,
1764 .remove = wm8903_remove,
1765 .suspend = wm8903_suspend,
1766 .resume = wm8903_resume,
1767 .set_bias_level = wm8903_set_bias_level,
1768 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
1769 .reg_word_size = sizeof(u16),
1770 .reg_cache_default = wm8903_reg_defaults,
1771 .volatile_register = wm8903_volatile_register,
1772};
1773
1774#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1775static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1776 const struct i2c_device_id *id)
1777{
1778 struct wm8903_priv *wm8903;
1779 int ret;
1780
1781 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1782 if (wm8903 == NULL)
1783 return -ENOMEM;
1784
1785 i2c_set_clientdata(i2c, wm8903);
1786 wm8903->irq = i2c->irq;
1787
1788 ret = snd_soc_register_codec(&i2c->dev,
1789 &soc_codec_dev_wm8903, &wm8903_dai, 1);
1790 if (ret < 0)
1791 kfree(wm8903);
1792 return ret;
1793}
1794
1795static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1796{
1797 snd_soc_unregister_codec(&client->dev);
1798 kfree(i2c_get_clientdata(client));
1799 return 0;
1800}
1801
1802static const struct i2c_device_id wm8903_i2c_id[] = {
1803 { "wm8903", 0 },
1804 { }
1805};
1806MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1807
1808static struct i2c_driver wm8903_i2c_driver = {
1809 .driver = {
1810 .name = "wm8903-codec",
1811 .owner = THIS_MODULE,
1812 },
1813 .probe = wm8903_i2c_probe,
1814 .remove = __devexit_p(wm8903_i2c_remove),
1815 .id_table = wm8903_i2c_id,
1816};
1817#endif
1818
1819static int __init wm8903_modinit(void)
1820{
1821 int ret = 0;
1822#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1823 ret = i2c_add_driver(&wm8903_i2c_driver);
1824 if (ret != 0) {
1825 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
1826 ret);
1827 }
1828#endif
1829 return ret;
1830}
1831module_init(wm8903_modinit);
1832
1833static void __exit wm8903_exit(void)
1834{
1835#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1836 i2c_del_driver(&wm8903_i2c_driver);
1837#endif
1838}
1839module_exit(wm8903_exit);
1840
1841MODULE_DESCRIPTION("ASoC WM8903 driver");
1842MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1843MODULE_LICENSE("GPL");
1844
