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17#include <linux/types.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/serial_8250.h>
21#include <linux/gpio.h>
22#include <linux/i2c.h>
23#include <linux/irq.h>
24
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27#include <asm/mach/time.h>
28#include <asm/memory.h>
29#include <asm/mach/map.h>
30#include <mach/common.h>
31#include <mach/board-mx31ads.h>
32#include <mach/iomux-mx3.h>
33
34#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
35#include <linux/mfd/wm8350/audio.h>
36#include <linux/mfd/wm8350/core.h>
37#include <linux/mfd/wm8350/pmic.h>
38#endif
39
40#include "devices-imx31.h"
41#include "devices.h"
42
43
44#define PBC_INTSTATUS 0x000016
45
46
47#define PBC_INTCURR_STATUS 0x000018
48
49
50#define PBC_INTMASK_SET 0x00001A
51
52
53#define PBC_INTMASK_CLEAR 0x00001C
54
55
56#define PBC_SC16C652_UARTA 0x010000
57
58
59#define PBC_SC16C652_UARTB 0x010010
60
61#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
62#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
63#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
64#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
65
66#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
67
68#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
69#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
70
71#define MXC_MAX_EXP_IO_LINES 16
72
73
74
75
76static struct plat_serial8250_port serial_platform_data[] = {
77 {
78 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
79 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
80 .irq = EXPIO_INT_XUART_INTA,
81 .uartclk = 14745600,
82 .regshift = 0,
83 .iotype = UPIO_MEM,
84 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
85 }, {
86 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
87 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
88 .irq = EXPIO_INT_XUART_INTB,
89 .uartclk = 14745600,
90 .regshift = 0,
91 .iotype = UPIO_MEM,
92 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
93 },
94 {},
95};
96
97static struct platform_device serial_device = {
98 .name = "serial8250",
99 .id = 0,
100 .dev = {
101 .platform_data = serial_platform_data,
102 },
103};
104
105static int __init mxc_init_extuart(void)
106{
107 return platform_device_register(&serial_device);
108}
109
110static const struct imxuart_platform_data uart_pdata __initconst = {
111 .flags = IMXUART_HAVE_RTSCTS,
112};
113
114static unsigned int uart_pins[] = {
115 MX31_PIN_CTS1__CTS1,
116 MX31_PIN_RTS1__RTS1,
117 MX31_PIN_TXD1__TXD1,
118 MX31_PIN_RXD1__RXD1
119};
120
121static inline void mxc_init_imx_uart(void)
122{
123 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
124 imx31_add_imx_uart0(&uart_pdata);
125}
126
127static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
128{
129 u32 imr_val;
130 u32 int_valid;
131 u32 expio_irq;
132
133 imr_val = __raw_readw(PBC_INTMASK_SET_REG);
134 int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
135
136 expio_irq = MXC_EXP_IO_BASE;
137 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
138 if ((int_valid & 1) == 0)
139 continue;
140
141 generic_handle_irq(expio_irq);
142 }
143}
144
145
146
147
148
149static void expio_mask_irq(struct irq_data *d)
150{
151 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
152
153 __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
154 __raw_readw(PBC_INTMASK_CLEAR_REG);
155}
156
157
158
159
160
161static void expio_ack_irq(struct irq_data *d)
162{
163 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
164
165 __raw_writew(1 << expio, PBC_INTSTATUS_REG);
166}
167
168
169
170
171
172static void expio_unmask_irq(struct irq_data *d)
173{
174 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
175
176 __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
177}
178
179static struct irq_chip expio_irq_chip = {
180 .name = "EXPIO(CPLD)",
181 .irq_ack = expio_ack_irq,
182 .irq_mask = expio_mask_irq,
183 .irq_unmask = expio_unmask_irq,
184};
185
186static void __init mx31ads_init_expio(void)
187{
188 int i;
189
190 printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
191
192
193
194
195 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
196
197
198 __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
199 __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
200 for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
201 i++) {
202 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
203 set_irq_flags(i, IRQF_VALID);
204 }
205 irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
206 irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
207}
208
209#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
210
211
212
213
214
215
216
217
218
219static struct regulator_consumer_supply sw1a_consumers[] = {
220 {
221 .supply = "cpu_vcc",
222 }
223};
224
225static struct regulator_init_data sw1a_data = {
226 .constraints = {
227 .name = "SW1A",
228 .min_uV = 1275000,
229 .max_uV = 1600000,
230 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
231 REGULATOR_CHANGE_MODE,
232 .valid_modes_mask = REGULATOR_MODE_NORMAL |
233 REGULATOR_MODE_FAST,
234 .state_mem = {
235 .uV = 1400000,
236 .mode = REGULATOR_MODE_NORMAL,
237 .enabled = 1,
238 },
239 .initial_state = PM_SUSPEND_MEM,
240 .always_on = 1,
241 .boot_on = 1,
242 },
243 .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
244 .consumer_supplies = sw1a_consumers,
245};
246
247
248static struct regulator_init_data viohi_data = {
249 .constraints = {
250 .name = "VIOHO",
251 .min_uV = 2800000,
252 .max_uV = 2800000,
253 .state_mem = {
254 .uV = 2800000,
255 .mode = REGULATOR_MODE_NORMAL,
256 .enabled = 1,
257 },
258 .initial_state = PM_SUSPEND_MEM,
259 .always_on = 1,
260 .boot_on = 1,
261 },
262};
263
264
265static struct regulator_init_data violo_data = {
266 .constraints = {
267 .name = "VIOLO",
268 .min_uV = 1800000,
269 .max_uV = 1800000,
270 .state_mem = {
271 .uV = 1800000,
272 .mode = REGULATOR_MODE_NORMAL,
273 .enabled = 1,
274 },
275 .initial_state = PM_SUSPEND_MEM,
276 .always_on = 1,
277 .boot_on = 1,
278 },
279};
280
281
282static struct regulator_init_data sw2a_data = {
283 .constraints = {
284 .name = "SW2A",
285 .min_uV = 1800000,
286 .max_uV = 1800000,
287 .valid_modes_mask = REGULATOR_MODE_NORMAL,
288 .state_mem = {
289 .uV = 1800000,
290 .mode = REGULATOR_MODE_NORMAL,
291 .enabled = 1,
292 },
293 .state_disk = {
294 .mode = REGULATOR_MODE_NORMAL,
295 .enabled = 0,
296 },
297 .always_on = 1,
298 .boot_on = 1,
299 .initial_state = PM_SUSPEND_MEM,
300 },
301};
302
303static struct regulator_init_data ldo1_data = {
304 .constraints = {
305 .name = "VCAM/VMMC1/VMMC2",
306 .min_uV = 2800000,
307 .max_uV = 2800000,
308 .valid_modes_mask = REGULATOR_MODE_NORMAL,
309 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
310 .apply_uV = 1,
311 },
312};
313
314static struct regulator_consumer_supply ldo2_consumers[] = {
315 { .supply = "AVDD", .dev_name = "1-001a" },
316 { .supply = "HPVDD", .dev_name = "1-001a" },
317};
318
319
320static struct regulator_init_data ldo2_data = {
321 .constraints = {
322 .name = "VESIM/VSIM/AVDD",
323 .min_uV = 3300000,
324 .max_uV = 3300000,
325 .valid_modes_mask = REGULATOR_MODE_NORMAL,
326 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
327 .apply_uV = 1,
328 },
329 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
330 .consumer_supplies = ldo2_consumers,
331};
332
333
334static struct regulator_init_data vdig_data = {
335 .constraints = {
336 .name = "VDIG",
337 .min_uV = 1500000,
338 .max_uV = 1500000,
339 .valid_modes_mask = REGULATOR_MODE_NORMAL,
340 .apply_uV = 1,
341 .always_on = 1,
342 .boot_on = 1,
343 },
344};
345
346
347static struct regulator_init_data ldo4_data = {
348 .constraints = {
349 .name = "VRF1/CVDD_2.775",
350 .min_uV = 2500000,
351 .max_uV = 2500000,
352 .valid_modes_mask = REGULATOR_MODE_NORMAL,
353 .apply_uV = 1,
354 .always_on = 1,
355 .boot_on = 1,
356 },
357};
358
359static struct wm8350_led_platform_data wm8350_led_data = {
360 .name = "wm8350:white",
361 .default_trigger = "heartbeat",
362 .max_uA = 27899,
363};
364
365static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
366 .vmid_discharge_msecs = 1000,
367 .drain_msecs = 30,
368 .cap_discharge_msecs = 700,
369 .vmid_charge_msecs = 700,
370 .vmid_s_curve = WM8350_S_CURVE_SLOW,
371 .dis_out4 = WM8350_DISCHARGE_SLOW,
372 .dis_out3 = WM8350_DISCHARGE_SLOW,
373 .dis_out2 = WM8350_DISCHARGE_SLOW,
374 .dis_out1 = WM8350_DISCHARGE_SLOW,
375 .vroi_out4 = WM8350_TIE_OFF_500R,
376 .vroi_out3 = WM8350_TIE_OFF_500R,
377 .vroi_out2 = WM8350_TIE_OFF_500R,
378 .vroi_out1 = WM8350_TIE_OFF_500R,
379 .vroi_enable = 0,
380 .codec_current_on = WM8350_CODEC_ISEL_1_0,
381 .codec_current_standby = WM8350_CODEC_ISEL_0_5,
382 .codec_current_charge = WM8350_CODEC_ISEL_1_5,
383};
384
385static int mx31_wm8350_init(struct wm8350 *wm8350)
386{
387 wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
388 WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
389 WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
390 WM8350_GPIO_DEBOUNCE_ON);
391
392 wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
393 WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
394 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
395 WM8350_GPIO_DEBOUNCE_ON);
396
397 wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
398 WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
399 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
400 WM8350_GPIO_DEBOUNCE_OFF);
401
402 wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
403 WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
404 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
405 WM8350_GPIO_DEBOUNCE_OFF);
406
407 wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
408 WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
409 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
410 WM8350_GPIO_DEBOUNCE_OFF);
411
412 wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
413 WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
414 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
415 WM8350_GPIO_DEBOUNCE_OFF);
416
417 wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
418 WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
419 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
420 WM8350_GPIO_DEBOUNCE_OFF);
421
422 wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
423 wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
424 wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
425 wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
426 wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
427 wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
428 wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
429 wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
430
431
432 wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
433 WM8350_DC5_ERRACT_SHUTDOWN_CONV);
434 wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
435 WM8350_ISINK_FLASH_DISABLE,
436 WM8350_ISINK_FLASH_TRIG_BIT,
437 WM8350_ISINK_FLASH_DUR_32MS,
438 WM8350_ISINK_FLASH_ON_INSTANT,
439 WM8350_ISINK_FLASH_OFF_INSTANT,
440 WM8350_ISINK_FLASH_MODE_EN);
441 wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
442 WM8350_ISINK_MODE_BOOST,
443 WM8350_ISINK_ILIM_NORMAL,
444 WM8350_DC5_RMP_20V,
445 WM8350_DC5_FBSRC_ISINKA);
446 wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
447 &wm8350_led_data);
448
449 wm8350->codec.platform_data = &imx32ads_wm8350_setup;
450
451 regulator_has_full_constraints();
452
453 return 0;
454}
455
456static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
457 .init = mx31_wm8350_init,
458 .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
459};
460#endif
461
462static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
463#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
464 {
465 I2C_BOARD_INFO("wm8350", 0x1a),
466 .platform_data = &mx31_wm8350_pdata,
467 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
468 },
469#endif
470};
471
472static void mxc_init_i2c(void)
473{
474 i2c_register_board_info(1, mx31ads_i2c1_devices,
475 ARRAY_SIZE(mx31ads_i2c1_devices));
476
477 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
478 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
479
480 imx31_add_imx_i2c1(NULL);
481}
482
483static unsigned int ssi_pins[] = {
484 MX31_PIN_SFS5__SFS5,
485 MX31_PIN_SCK5__SCK5,
486 MX31_PIN_SRXD5__SRXD5,
487 MX31_PIN_STXD5__STXD5,
488};
489
490static void mxc_init_audio(void)
491{
492 imx31_add_imx_ssi(0, NULL);
493 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
494}
495
496
497static struct map_desc mx31ads_io_desc[] __initdata = {
498 {
499 .virtual = MX31_CS4_BASE_ADDR_VIRT,
500 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
501 .length = MX31_CS4_SIZE / 2,
502 .type = MT_DEVICE
503 },
504};
505
506static void __init mx31ads_map_io(void)
507{
508 mx31_map_io();
509 iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
510}
511
512static void __init mx31ads_init_irq(void)
513{
514 mx31_init_irq();
515 mx31ads_init_expio();
516}
517
518static void __init mx31ads_init(void)
519{
520 mxc_init_extuart();
521 mxc_init_imx_uart();
522 mxc_init_i2c();
523 mxc_init_audio();
524}
525
526static void __init mx31ads_timer_init(void)
527{
528 mx31_clocks_init(26000000);
529}
530
531static struct sys_timer mx31ads_timer = {
532 .init = mx31ads_timer_init,
533};
534
535MACHINE_START(MX31ADS, "Freescale MX31ADS")
536
537 .boot_params = MX3x_PHYS_OFFSET + 0x100,
538 .map_io = mx31ads_map_io,
539 .init_early = imx31_init_early,
540 .init_irq = mx31ads_init_irq,
541 .timer = &mx31ads_timer,
542 .init_machine = mx31ads_init,
543MACHINE_END
544
