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17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/serial_8250.h>
20#include <linux/i2c.h>
21#include <linux/gpio.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/fsl_devices.h>
27
28#include <mach/eukrea-baseboards.h>
29#include <mach/common.h>
30#include <mach/hardware.h>
31#include <mach/iomux-mx51.h>
32#include <mach/mxc_ehci.h>
33
34#include <asm/irq.h>
35#include <asm/setup.h>
36#include <asm/mach-types.h>
37#include <asm/mach/arch.h>
38#include <asm/mach/time.h>
39
40#include "devices-imx51.h"
41#include "devices.h"
42
43#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27)
44#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28)
45#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25)
46#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26)
47#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27)
48#define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
49#define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
50#define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
51#define CPUIMX51_QUARTD_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO)
52#define CPUIMX51_QUART_XTAL 14745600
53#define CPUIMX51_QUART_REGSHIFT 17
54
55
56#define MX51_USB_CTRL_1_OFFSET 0x10
57#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
58
59#define MX51_USB_PLLDIV_12_MHZ 0x00
60#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
61#define MX51_USB_PLL_DIV_24_MHZ 0x02
62
63static struct plat_serial8250_port serial_platform_data[] = {
64 {
65 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
66 .irq = CPUIMX51_QUARTA_IRQ,
67 .irqflags = IRQF_TRIGGER_HIGH,
68 .uartclk = CPUIMX51_QUART_XTAL,
69 .regshift = CPUIMX51_QUART_REGSHIFT,
70 .iotype = UPIO_MEM,
71 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
72 }, {
73 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
74 .irq = CPUIMX51_QUARTB_IRQ,
75 .irqflags = IRQF_TRIGGER_HIGH,
76 .uartclk = CPUIMX51_QUART_XTAL,
77 .regshift = CPUIMX51_QUART_REGSHIFT,
78 .iotype = UPIO_MEM,
79 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
80 }, {
81 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
82 .irq = CPUIMX51_QUARTC_IRQ,
83 .irqflags = IRQF_TRIGGER_HIGH,
84 .uartclk = CPUIMX51_QUART_XTAL,
85 .regshift = CPUIMX51_QUART_REGSHIFT,
86 .iotype = UPIO_MEM,
87 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
88 }, {
89 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
90 .irq = CPUIMX51_QUARTD_IRQ,
91 .irqflags = IRQF_TRIGGER_HIGH,
92 .uartclk = CPUIMX51_QUART_XTAL,
93 .regshift = CPUIMX51_QUART_REGSHIFT,
94 .iotype = UPIO_MEM,
95 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
96 }, {
97 }
98};
99
100static struct platform_device serial_device = {
101 .name = "serial8250",
102 .id = 0,
103 .dev = {
104 .platform_data = serial_platform_data,
105 },
106};
107
108static struct platform_device *devices[] __initdata = {
109 &serial_device,
110};
111
112static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
113
114 MX51_PAD_UART1_RXD__UART1_RXD,
115 MX51_PAD_UART1_TXD__UART1_TXD,
116 MX51_PAD_UART1_RTS__UART1_RTS,
117 MX51_PAD_UART1_CTS__UART1_CTS,
118
119
120 MX51_PAD_GPIO1_2__I2C2_SCL,
121 MX51_PAD_GPIO1_3__I2C2_SDA,
122 MX51_PAD_NANDF_D10__GPIO3_30,
123
124
125 MX51_PAD_NANDF_D15__GPIO3_25,
126 MX51_PAD_NANDF_D14__GPIO3_26,
127 MX51_PAD_NANDF_D13__GPIO3_27,
128 MX51_PAD_NANDF_D12__GPIO3_28,
129
130
131 MX51_PAD_USBH1_CLK__USBH1_CLK,
132 MX51_PAD_USBH1_DIR__USBH1_DIR,
133 MX51_PAD_USBH1_NXT__USBH1_NXT,
134 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
135 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
136 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
137 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
138 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
139 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
140 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
141 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
142 MX51_PAD_USBH1_STP__USBH1_STP,
143};
144
145static const struct mxc_nand_platform_data
146 eukrea_cpuimx51_nand_board_info __initconst = {
147 .width = 1,
148 .hw_ecc = 1,
149 .flash_bbt = 1,
150};
151
152static const struct imxuart_platform_data uart_pdata __initconst = {
153 .flags = IMXUART_HAVE_RTSCTS,
154};
155
156static const
157struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
158 .bitrate = 100000,
159};
160
161static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
162 {
163 I2C_BOARD_INFO("pcf8563", 0x51),
164 },
165};
166
167
168
169
170static int initialize_otg_port(struct platform_device *pdev)
171{
172 u32 v;
173 void __iomem *usb_base;
174 void __iomem *usbother_base;
175
176 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
177 if (!usb_base)
178 return -ENOMEM;
179 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
180
181
182 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
183 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
184 v |= MX51_USB_PLL_DIV_19_2_MHZ;
185 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
186 iounmap(usb_base);
187
188 mdelay(10);
189
190 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
191}
192
193static int initialize_usbh1_port(struct platform_device *pdev)
194{
195 u32 v;
196 void __iomem *usb_base;
197 void __iomem *usbother_base;
198
199 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
200 if (!usb_base)
201 return -ENOMEM;
202 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
203
204
205 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
206 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
207 iounmap(usb_base);
208
209 mdelay(10);
210
211 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
212 MXC_EHCI_ITC_NO_THRESHOLD);
213}
214
215static struct mxc_usbh_platform_data dr_utmi_config = {
216 .init = initialize_otg_port,
217 .portsc = MXC_EHCI_UTMI_16BIT,
218};
219
220static struct fsl_usb2_platform_data usb_pdata = {
221 .operating_mode = FSL_USB2_DR_DEVICE,
222 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
223};
224
225static struct mxc_usbh_platform_data usbh1_config = {
226 .init = initialize_usbh1_port,
227 .portsc = MXC_EHCI_MODE_ULPI,
228};
229
230static int otg_mode_host;
231
232static int __init eukrea_cpuimx51_otg_mode(char *options)
233{
234 if (!strcmp(options, "host"))
235 otg_mode_host = 1;
236 else if (!strcmp(options, "device"))
237 otg_mode_host = 0;
238 else
239 pr_info("otg_mode neither \"host\" nor \"device\". "
240 "Defaulting to device\n");
241 return 0;
242}
243__setup("otg_mode=", eukrea_cpuimx51_otg_mode);
244
245
246
247
248static void __init eukrea_cpuimx51_init(void)
249{
250 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
251 ARRAY_SIZE(eukrea_cpuimx51_pads));
252
253 imx51_add_imx_uart(0, &uart_pdata);
254 imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
255
256 gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
257 gpio_direction_input(CPUIMX51_QUARTA_GPIO);
258 gpio_free(CPUIMX51_QUARTA_GPIO);
259 gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
260 gpio_direction_input(CPUIMX51_QUARTB_GPIO);
261 gpio_free(CPUIMX51_QUARTB_GPIO);
262 gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
263 gpio_direction_input(CPUIMX51_QUARTC_GPIO);
264 gpio_free(CPUIMX51_QUARTC_GPIO);
265 gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
266 gpio_direction_input(CPUIMX51_QUARTD_GPIO);
267 gpio_free(CPUIMX51_QUARTD_GPIO);
268
269 imx51_add_fec(NULL);
270 platform_add_devices(devices, ARRAY_SIZE(devices));
271
272 imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
273 i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
274 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
275
276 if (otg_mode_host)
277 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
278 else {
279 initialize_otg_port(NULL);
280 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
281 }
282 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
283
284#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
285 eukrea_mbimx51_baseboard_init();
286#endif
287}
288
289static void __init eukrea_cpuimx51_timer_init(void)
290{
291 mx51_clocks_init(32768, 24000000, 22579200, 0);
292}
293
294static struct sys_timer mxc_timer = {
295 .init = eukrea_cpuimx51_timer_init,
296};
297
298MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
299
300 .boot_params = MX51_PHYS_OFFSET + 0x100,
301 .map_io = mx51_map_io,
302 .init_early = imx51_init_early,
303 .init_irq = mx51_init_irq,
304 .timer = &mxc_timer,
305 .init_machine = eukrea_cpuimx51_init,
306MACHINE_END
307
