LXR linux/arch/blackfin/include/asm/bfin

   1/*
   2 * bfin_serial.h - Blackfin UART/Serial definitions
   3 *
   4 * Copyright 2006-2010 Analog Devices Inc.
   5 *
   6 * Licensed under the GPL-2 or later.
   7 */
   8
   9#ifndef __BFIN_ASM_SERIAL_H__
  10#define __BFIN_ASM_SERIAL_H__
  11
  12#include <linux/serial_core.h>
  13#include <linux/spinlock.h>
  14#include <mach/anomaly.h>
  15#include <mach/bfin_serial.h>
  16
  17#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
  18    defined(CONFIG_BFIN_UART1_CTSRTS) || \
  19    defined(CONFIG_BFIN_UART2_CTSRTS) || \
  20    defined(CONFIG_BFIN_UART3_CTSRTS)
  21# ifdef BFIN_UART_BF54X_STYLE
  22#  define CONFIG_SERIAL_BFIN_HARD_CTSRTS
  23# else
  24#  define CONFIG_SERIAL_BFIN_CTSRTS
  25# endif
  26#endif
  27
  28struct circ_buf;
  29struct timer_list;
  30struct work_struct;
  31
  32struct bfin_serial_port {
  33        struct uart_port port;
  34        unsigned int old_status;
  35        int status_irq;
  36#ifndef BFIN_UART_BF54X_STYLE
  37        unsigned int lsr;
  38#endif
  39#ifdef CONFIG_SERIAL_BFIN_DMA
  40        int tx_done;
  41        int tx_count;
  42        struct circ_buf rx_dma_buf;
  43        struct timer_list rx_dma_timer;
  44        int rx_dma_nrows;
  45        spinlock_t rx_lock;
  46        unsigned int tx_dma_channel;
  47        unsigned int rx_dma_channel;
  48        struct work_struct tx_dma_workqueue;
  49#elif ANOMALY_05000363
  50        unsigned int anomaly_threshold;
  51#endif
  52#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
  53        int scts;
  54#endif
  55#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
  56        defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
  57        int cts_pin;
  58        int rts_pin;
  59#endif
  60};
  61
  62/* UART_LCR Masks */
  63#define WLS(x)                   (((x)-5) & 0x03)  /* Word Length Select */
  64#define STB                      0x04  /* Stop Bits */
  65#define PEN                      0x08  /* Parity Enable */
  66#define EPS                      0x10  /* Even Parity Select */
  67#define STP                      0x20  /* Stick Parity */
  68#define SB                       0x40  /* Set Break */
  69#define DLAB                     0x80  /* Divisor Latch Access */
  70
  71/* UART_LSR Masks */
  72#define DR                       0x01  /* Data Ready */
  73#define OE                       0x02  /* Overrun Error */
  74#define PE                       0x04  /* Parity Error */
  75#define FE                       0x08  /* Framing Error */
  76#define BI                       0x10  /* Break Interrupt */
  77#define THRE                     0x20  /* THR Empty */
  78#define TEMT                     0x40  /* TSR and UART_THR Empty */
  79#define TFI                      0x80  /* Transmission Finished Indicator */
  80
  81/* UART_IER Masks */
  82#define ERBFI                    0x01  /* Enable Receive Buffer Full Interrupt */
  83#define ETBEI                    0x02  /* Enable Transmit Buffer Empty Interrupt */
  84#define ELSI                     0x04  /* Enable RX Status Interrupt */
  85#define EDSSI                    0x08  /* Enable Modem Status Interrupt */
  86#define EDTPTI                   0x10  /* Enable DMA Transmit PIRQ Interrupt */
  87#define ETFI                     0x20  /* Enable Transmission Finished Interrupt */
  88#define ERFCI                    0x40  /* Enable Receive FIFO Count Interrupt */
  89
  90/* UART_MCR Masks */
  91#define XOFF                     0x01  /* Transmitter Off */
  92#define MRTS                     0x02  /* Manual Request To Send */
  93#define RFIT                     0x04  /* Receive FIFO IRQ Threshold */
  94#define RFRT                     0x08  /* Receive FIFO RTS Threshold */
  95#define LOOP_ENA                 0x10  /* Loopback Mode Enable */
  96#define FCPOL                    0x20  /* Flow Control Pin Polarity */
  97#define ARTS                     0x40  /* Automatic Request To Send */
  98#define ACTS                     0x80  /* Automatic Clear To Send */
  99
 100/* UART_MSR Masks */
 101#define SCTS                     0x01  /* Sticky CTS */
 102#define CTS                      0x10  /* Clear To Send */
 103#define RFCS                     0x20  /* Receive FIFO Count Status */
 104
 105/* UART_GCTL Masks */
 106#define UCEN                     0x01  /* Enable UARTx Clocks */
 107#define IREN                     0x02  /* Enable IrDA Mode */
 108#define TPOLC                    0x04  /* IrDA TX Polarity Change */
 109#define RPOLC                    0x08  /* IrDA RX Polarity Change */
 110#define FPE                      0x10  /* Force Parity Error On Transmit */
 111#define FFE                      0x20  /* Force Framing Error On Transmit */
 112
 113#ifdef BFIN_UART_BF54X_STYLE
 114# define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)        */
 115# define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)       */
 116# define OFFSET_GCTL             0x08  /* Global Control Register         */
 117# define OFFSET_LCR              0x0C  /* Line Control Register           */
 118# define OFFSET_MCR              0x10  /* Modem Control Register          */
 119# define OFFSET_LSR              0x14  /* Line Status Register            */
 120# define OFFSET_MSR              0x18  /* Modem Status Register           */
 121# define OFFSET_SCR              0x1C  /* SCR Scratch Register            */
 122# define OFFSET_IER_SET          0x20  /* Set Interrupt Enable Register   */
 123# define OFFSET_IER_CLEAR        0x24  /* Clear Interrupt Enable Register */
 124# define OFFSET_THR              0x28  /* Transmit Holding register       */
 125# define OFFSET_RBR              0x2C  /* Receive Buffer register         */
 126#else /* BF533 style */
 127# define OFFSET_THR              0x00  /* Transmit Holding register         */
 128# define OFFSET_RBR              0x00  /* Receive Buffer register           */
 129# define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)          */
 130# define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)         */
 131# define OFFSET_IER              0x04  /* Interrupt Enable Register         */
 132# define OFFSET_IIR              0x08  /* Interrupt Identification Register */
 133# define OFFSET_LCR              0x0C  /* Line Control Register             */
 134# define OFFSET_MCR              0x10  /* Modem Control Register            */
 135# define OFFSET_LSR              0x14  /* Line Status Register              */
 136# define OFFSET_MSR              0x18  /* Modem Status Register             */
 137# define OFFSET_SCR              0x1C  /* SCR Scratch Register              */
 138# define OFFSET_GCTL             0x24  /* Global Control Register           */
 139/* code should not need IIR, so force build error if they use it */
 140# undef OFFSET_IIR
 141#endif
 142
 143/*
 144 * All Blackfin system MMRs are padded to 32bits even if the register
 145 * itself is only 16bits.  So use a helper macro to streamline this.
 146 */
 147#define __BFP(m) u16 m; u16 __pad_##m
 148struct bfin_uart_regs {
 149#ifdef BFIN_UART_BF54X_STYLE
 150        __BFP(dll);
 151        __BFP(dlh);
 152        __BFP(gctl);
 153        __BFP(lcr);
 154        __BFP(mcr);
 155        __BFP(lsr);
 156        __BFP(msr);
 157        __BFP(scr);
 158        __BFP(ier_set);
 159        __BFP(ier_clear);
 160        __BFP(thr);
 161        __BFP(rbr);
 162#else
 163        union {
 164                u16 dll;
 165                u16 thr;
 166                const u16 rbr;
 167        };
 168        const u16 __pad0;
 169        union {
 170                u16 dlh;
 171                u16 ier;
 172        };
 173        const u16 __pad1;
 174        const __BFP(iir);
 175        __BFP(lcr);
 176        __BFP(mcr);
 177        __BFP(lsr);
 178        __BFP(msr);
 179        __BFP(scr);
 180        const u32 __pad2;
 181        __BFP(gctl);
 182#endif
 183};
 184#undef __BFP
 185
 186#ifndef port_membase
 187# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase)
 188#endif
 189
 190#define UART_GET_CHAR(p)      bfin_read16(port_membase(p) + OFFSET_RBR)
 191#define UART_GET_DLL(p)       bfin_read16(port_membase(p) + OFFSET_DLL)
 192#define UART_GET_DLH(p)       bfin_read16(port_membase(p) + OFFSET_DLH)
 193#define UART_GET_GCTL(p)      bfin_read16(port_membase(p) + OFFSET_GCTL)
 194#define UART_GET_LCR(p)       bfin_read16(port_membase(p) + OFFSET_LCR)
 195#define UART_GET_MCR(p)       bfin_read16(port_membase(p) + OFFSET_MCR)
 196#define UART_GET_MSR(p)       bfin_read16(port_membase(p) + OFFSET_MSR)
 197
 198#define UART_PUT_CHAR(p, v)   bfin_write16(port_membase(p) + OFFSET_THR, v)
 199#define UART_PUT_DLL(p, v)    bfin_write16(port_membase(p) + OFFSET_DLL, v)
 200#define UART_PUT_DLH(p, v)    bfin_write16(port_membase(p) + OFFSET_DLH, v)
 201#define UART_PUT_GCTL(p, v)   bfin_write16(port_membase(p) + OFFSET_GCTL, v)
 202#define UART_PUT_LCR(p, v)    bfin_write16(port_membase(p) + OFFSET_LCR, v)
 203#define UART_PUT_MCR(p, v)    bfin_write16(port_membase(p) + OFFSET_MCR, v)
 204
 205#ifdef BFIN_UART_BF54X_STYLE
 206
 207#define UART_CLEAR_IER(p, v)  bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
 208#define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER_SET)
 209#define UART_SET_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
 210
 211#define UART_CLEAR_DLAB(p)    /* MMRs not muxed on BF54x */
 212#define UART_SET_DLAB(p)      /* MMRs not muxed on BF54x */
 213
 214#define UART_CLEAR_LSR(p)     bfin_write16(port_membase(p) + OFFSET_LSR, -1)
 215#define UART_GET_LSR(p)       bfin_read16(port_membase(p) + OFFSET_LSR)
 216#define UART_PUT_LSR(p, v)    bfin_write16(port_membase(p) + OFFSET_LSR, v)
 217
 218/* This handles hard CTS/RTS */
 219#define BFIN_UART_CTSRTS_HARD
 220#define UART_CLEAR_SCTS(p)      bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
 221#define UART_GET_CTS(x)         (UART_GET_MSR(x) & CTS)
 222#define UART_DISABLE_RTS(x)     UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
 223#define UART_ENABLE_RTS(x)      UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
 224#define UART_ENABLE_INTS(x, v)  UART_SET_IER(x, v)
 225#define UART_DISABLE_INTS(x)    UART_CLEAR_IER(x, 0xF)
 226
 227#else /* BF533 style */
 228
 229#define UART_CLEAR_IER(p, v)  UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
 230#define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER)
 231#define UART_PUT_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER, v)
 232#define UART_SET_IER(p, v)    UART_PUT_IER(p, UART_GET_IER(p) | (v))
 233
 234#define UART_CLEAR_DLAB(p)    do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
 235#define UART_SET_DLAB(p)      do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
 236
 237#ifndef put_lsr_cache
 238# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v))
 239#endif
 240#ifndef get_lsr_cache
 241# define get_lsr_cache(p)    (((struct bfin_serial_port *)(p))->lsr)
 242#endif
 243
 244/* The hardware clears the LSR bits upon read, so we need to cache
 245 * some of the more fun bits in software so they don't get lost
 246 * when checking the LSR in other code paths (TX).
 247 */
 248static inline void UART_CLEAR_LSR(void *p)
 249{
 250        put_lsr_cache(p, 0);
 251        bfin_write16(port_membase(p) + OFFSET_LSR, -1);
 252}
 253static inline unsigned int UART_GET_LSR(void *p)
 254{
 255        unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
 256        put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
 257        return lsr | get_lsr_cache(p);
 258}
 259static inline void UART_PUT_LSR(void *p, uint16_t val)
 260{
 261        put_lsr_cache(p, get_lsr_cache(p) & ~val);
 262}
 263
 264/* This handles soft CTS/RTS */
 265#define UART_GET_CTS(x)        gpio_get_value((x)->cts_pin)
 266#define UART_DISABLE_RTS(x)    gpio_set_value((x)->rts_pin, 1)
 267#define UART_ENABLE_RTS(x)     gpio_set_value((x)->rts_pin, 0)
 268#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
 269#define UART_DISABLE_INTS(x)   UART_PUT_IER(x, 0)
 270
 271#endif
 272
 273#ifndef BFIN_UART_TX_FIFO_SIZE
 274# define BFIN_UART_TX_FIFO_SIZE 2
 275#endif
 276
 277#endif /* __BFIN_ASM_SERIAL_H__ */
 278