1#ifndef _ASM_ARCH_CRIS_DMA_H
2#define _ASM_ARCH_CRIS_DMA_H
3
4
5
6#define MAX_DMA_CHANNELS 12
7
8#define NETWORK_ETH_TX_DMA_NBR 0
9#define NETWORK_ETH_RX_DMA_NBR 1
10
11#define IO_PROC_DMA_TX_DMA_NBR 4
12#define IO_PROC_DMA_RX_DMA_NBR 5
13
14#define ASYNC_SER3_TX_DMA_NBR 2
15#define ASYNC_SER3_RX_DMA_NBR 3
16
17#define ASYNC_SER2_TX_DMA_NBR 6
18#define ASYNC_SER2_RX_DMA_NBR 7
19
20#define ASYNC_SER1_TX_DMA_NBR 4
21#define ASYNC_SER1_RX_DMA_NBR 5
22
23#define SYNC_SER_TX_DMA_NBR 6
24#define SYNC_SER_RX_DMA_NBR 7
25
26#define ASYNC_SER0_TX_DMA_NBR 0
27#define ASYNC_SER0_RX_DMA_NBR 1
28
29#define STRCOP_TX_DMA_NBR 2
30#define STRCOP_RX_DMA_NBR 3
31
32#define dma_eth0 dma_eth
33#define dma_eth1 dma_eth
34
35enum dma_owner {
36 dma_eth,
37 dma_ser0,
38 dma_ser1,
39 dma_ser2,
40 dma_ser3,
41 dma_ser4,
42 dma_iop,
43 dma_sser,
44 dma_strp,
45 dma_h264,
46 dma_jpeg
47};
48
49int crisv32_request_dma(unsigned int dmanr, const char *device_id,
50 unsigned options, unsigned bandwidth, enum dma_owner owner);
51void crisv32_free_dma(unsigned int dmanr);
52
53
54#define DMA_VERBOSE_ON_ERROR 1
55#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
56#define DMA_INT_MEM 4
57
58#endif
59