1/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version 2 from ../../inst/intr_vect/rtl/guinness/ivmask.config.r 3version . */ 4 5#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R 6#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R 7#define MEMARB_INTR_VECT 0x31 8#define GEN_IO_INTR_VECT 0x32 9#define GIO_INTR_VECT GEN_IO_INTR_VECT 10#define IOP0_INTR_VECT 0x33 11#define IOP1_INTR_VECT 0x34 12#define IOP2_INTR_VECT 0x35 13#define IOP3_INTR_VECT 0x36 14#define DMA0_INTR_VECT 0x37 15#define DMA1_INTR_VECT 0x38 16#define DMA2_INTR_VECT 0x39 17#define DMA3_INTR_VECT 0x3a 18#define DMA4_INTR_VECT 0x3b 19#define DMA5_INTR_VECT 0x3c 20#define DMA6_INTR_VECT 0x3d 21#define DMA7_INTR_VECT 0x3e 22#define DMA8_INTR_VECT 0x3f 23#define DMA9_INTR_VECT 0x40 24#define ATA_INTR_VECT 0x41 25#define SSER0_INTR_VECT 0x42 26#define SSER1_INTR_VECT 0x43 27#define SER0_INTR_VECT 0x44 28#define SER1_INTR_VECT 0x45 29#define SER2_INTR_VECT 0x46 30#define SER3_INTR_VECT 0x47 31#define P21_INTR_VECT 0x48 32#define ETH0_INTR_VECT 0x49 33#define ETH1_INTR_VECT 0x4a 34#define TIMER_INTR_VECT 0x4b 35#define TIMER0_INTR_VECT TIMER_INTR_VECT 36#define BIF_ARB_INTR_VECT 0x4c 37#define BIF_DMA_INTR_VECT 0x4d 38#define EXT_INTR_VECT 0x4e 39#define IPI_INTR_VECT 0x4f 40#define NBR_INTR_VECT 0x50 41#endif 42