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7
8
9#include <linux/init.h>
10#include <linux/console.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/serial.h>
15#include <linux/smp.h>
16#include <linux/types.h>
17#include <linux/string.h>
18#include <linux/tty.h>
19#include <linux/time.h>
20#include <linux/platform_device.h>
21#include <linux/serial_core.h>
22#include <linux/serial_8250.h>
23
24#include <asm/processor.h>
25#include <asm/reboot.h>
26#include <asm/smp-ops.h>
27#include <asm/system.h>
28#include <asm/irq_cpu.h>
29#include <asm/mipsregs.h>
30#include <asm/bootinfo.h>
31#include <asm/sections.h>
32#include <asm/time.h>
33
34#include <asm/octeon/octeon.h>
35#include <asm/octeon/pci-octeon.h>
36#include <asm/octeon/cvmx-mio-defs.h>
37
38#ifdef CONFIG_CAVIUM_DECODE_RSL
39extern void cvmx_interrupt_rsl_decode(void);
40extern int __cvmx_interrupt_ecc_report_single_bit_errors;
41extern void cvmx_interrupt_rsl_enable(void);
42#endif
43
44extern struct plat_smp_ops octeon_smp_ops;
45
46#ifdef CONFIG_PCI
47extern void pci_console_init(const char *arg);
48#endif
49
50static unsigned long long MAX_MEMORY = 512ull << 20;
51
52struct octeon_boot_descriptor *octeon_boot_desc_ptr;
53
54struct cvmx_bootinfo *octeon_bootinfo;
55EXPORT_SYMBOL(octeon_bootinfo);
56
57#ifdef CONFIG_CAVIUM_RESERVE32
58uint64_t octeon_reserve32_memory;
59EXPORT_SYMBOL(octeon_reserve32_memory);
60#endif
61
62static int octeon_uart;
63
64extern asmlinkage void handle_int(void);
65extern asmlinkage void plat_irq_dispatch(void);
66
67
68
69
70
71
72int octeon_is_simulation(void)
73{
74 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
75}
76EXPORT_SYMBOL(octeon_is_simulation);
77
78
79
80
81
82
83
84int octeon_is_pci_host(void)
85{
86#ifdef CONFIG_PCI
87 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
88#else
89 return 0;
90#endif
91}
92
93
94
95
96
97
98uint64_t octeon_get_clock_rate(void)
99{
100 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
101
102 return sysinfo->cpu_clock_hz;
103}
104EXPORT_SYMBOL(octeon_get_clock_rate);
105
106static u64 octeon_io_clock_rate;
107
108u64 octeon_get_io_clock_rate(void)
109{
110 return octeon_io_clock_rate;
111}
112EXPORT_SYMBOL(octeon_get_io_clock_rate);
113
114
115
116
117
118
119
120
121
122void octeon_write_lcd(const char *s)
123{
124 if (octeon_bootinfo->led_display_base_addr) {
125 void __iomem *lcd_address =
126 ioremap_nocache(octeon_bootinfo->led_display_base_addr,
127 8);
128 int i;
129 for (i = 0; i < 8; i++, s++) {
130 if (*s)
131 iowrite8(*s, lcd_address + i);
132 else
133 iowrite8(' ', lcd_address + i);
134 }
135 iounmap(lcd_address);
136 }
137}
138
139
140
141
142
143
144int octeon_get_boot_uart(void)
145{
146 int uart;
147#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
148 uart = 1;
149#else
150 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
151 1 : 0;
152#endif
153 return uart;
154}
155
156
157
158
159
160
161int octeon_get_boot_coremask(void)
162{
163 return octeon_boot_desc_ptr->core_mask;
164}
165
166
167
168
169void octeon_check_cpu_bist(void)
170{
171 const int coreid = cvmx_get_core_num();
172 unsigned long long mask;
173 unsigned long long bist_val;
174
175
176 mask = 0x1f00000000ull;
177 bist_val = read_octeon_c0_icacheerr();
178 if (bist_val & mask)
179 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
180 coreid, bist_val);
181
182 bist_val = read_octeon_c0_dcacheerr();
183 if (bist_val & 1)
184 pr_err("Core%d L1 Dcache parity error: "
185 "CacheErr(dcache) = 0x%llx\n",
186 coreid, bist_val);
187
188 mask = 0xfc00000000000000ull;
189 bist_val = read_c0_cvmmemctl();
190 if (bist_val & mask)
191 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
192 coreid, bist_val);
193
194 write_octeon_c0_dcacheerr(0);
195}
196
197
198
199
200
201
202static void octeon_restart(char *command)
203{
204
205#ifdef CONFIG_SMP
206 int cpu;
207 for_each_online_cpu(cpu)
208 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
209#else
210 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
211#endif
212
213 mb();
214 while (1)
215 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
216}
217
218
219
220
221
222
223
224static void octeon_kill_core(void *arg)
225{
226 mb();
227 if (octeon_is_simulation()) {
228
229 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
230
231 asm volatile ("sync\nbreak");
232 }
233}
234
235
236
237
238
239static void octeon_halt(void)
240{
241 smp_call_function(octeon_kill_core, NULL, 0);
242
243 switch (octeon_bootinfo->board_type) {
244 case CVMX_BOARD_TYPE_NAO38:
245
246 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
247 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
248 break;
249 default:
250 octeon_write_lcd("PowerOff");
251 break;
252 }
253
254 octeon_kill_core(NULL);
255}
256
257
258
259
260
261#ifdef CONFIG_CAVIUM_DECODE_RSL
262static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id)
263{
264 cvmx_interrupt_rsl_decode();
265 return IRQ_HANDLED;
266}
267#endif
268
269
270
271
272
273
274const char *octeon_board_type_string(void)
275{
276 static char name[80];
277 sprintf(name, "%s (%s)",
278 cvmx_board_type_to_string(octeon_bootinfo->board_type),
279 octeon_model_get_string(read_c0_prid()));
280 return name;
281}
282
283const char *get_system_type(void)
284 __attribute__ ((alias("octeon_board_type_string")));
285
286void octeon_user_io_init(void)
287{
288 union octeon_cvmemctl cvmmemctl;
289 union cvmx_iob_fau_timeout fau_timeout;
290 union cvmx_pow_nw_tim nm_tim;
291 uint64_t cvmctl;
292
293
294 cvmmemctl.u64 = read_c0_cvmmemctl();
295
296
297
298 cvmmemctl.s.dismarkwblongto = 1;
299
300
301 cvmmemctl.s.dismrgclrwbto = 0;
302
303
304
305 cvmmemctl.s.iobdmascrmsb = 0;
306
307
308
309
310 cvmmemctl.s.syncwsmarked = 0;
311
312 cvmmemctl.s.dissyncws = 0;
313
314 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
315 cvmmemctl.s.diswbfst = 1;
316 else
317 cvmmemctl.s.diswbfst = 0;
318
319
320 cvmmemctl.s.xkmemenas = 0;
321
322
323
324 cvmmemctl.s.xkmemenau = 0;
325
326
327
328 cvmmemctl.s.xkioenas = 0;
329
330
331
332 cvmmemctl.s.xkioenau = 0;
333
334
335
336 cvmmemctl.s.allsyncw = 0;
337
338
339
340 cvmmemctl.s.nomerge = 0;
341
342
343
344
345 cvmmemctl.s.didtto = 0;
346
347 cvmmemctl.s.csrckalwys = 0;
348
349 cvmmemctl.s.mclkalwys = 0;
350
351
352
353
354
355
356 cvmmemctl.s.wbfltime = 0;
357
358 cvmmemctl.s.istrnol2 = 0;
359
360
361
362
363
364
365
366 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
367 cvmmemctl.s.wbthresh = 4;
368 else
369 cvmmemctl.s.wbthresh = 10;
370
371
372
373#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
374 cvmmemctl.s.cvmsegenak = 1;
375#else
376 cvmmemctl.s.cvmsegenak = 0;
377#endif
378
379
380 cvmmemctl.s.cvmsegenas = 0;
381
382
383 cvmmemctl.s.cvmsegenau = 0;
384
385
386 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
387
388 write_c0_cvmmemctl(cvmmemctl.u64);
389
390 if (smp_processor_id() == 0)
391 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
392 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
393 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
394
395
396 cvmctl = read_c0_cvmctl();
397 cvmctl &= ~(7 << 7);
398 cvmctl |= 6 << 7;
399 write_c0_cvmctl(cvmctl);
400
401
402 fau_timeout.u64 = 0;
403 fau_timeout.s.tout_val = 0xfff;
404
405 fau_timeout.s.tout_enb = 0;
406 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
407
408 nm_tim.u64 = 0;
409
410 nm_tim.s.nw_tim = 3;
411 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
412
413 write_octeon_c0_icacheerr(0);
414 write_c0_derraddr1(0);
415}
416
417
418
419
420void __init prom_init(void)
421{
422 struct cvmx_sysinfo *sysinfo;
423 int i;
424 int argc;
425#ifdef CONFIG_CAVIUM_RESERVE32
426 int64_t addr = -1;
427#endif
428
429
430
431
432 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
433 octeon_bootinfo =
434 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
435 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
436
437 sysinfo = cvmx_sysinfo_get();
438 memset(sysinfo, 0, sizeof(*sysinfo));
439 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
440 sysinfo->phy_mem_desc_ptr =
441 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
442 sysinfo->core_mask = octeon_bootinfo->core_mask;
443 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
444 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
445 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
446 sysinfo->board_type = octeon_bootinfo->board_type;
447 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
448 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
449 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
450 sizeof(sysinfo->mac_addr_base));
451 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
452 memcpy(sysinfo->board_serial_number,
453 octeon_bootinfo->board_serial_number,
454 sizeof(sysinfo->board_serial_number));
455 sysinfo->compact_flash_common_base_addr =
456 octeon_bootinfo->compact_flash_common_base_addr;
457 sysinfo->compact_flash_attribute_base_addr =
458 octeon_bootinfo->compact_flash_attribute_base_addr;
459 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
460 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
461 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
462
463 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
464
465 union cvmx_mio_rst_boot rst_boot;
466 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
467 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
468 } else {
469 octeon_io_clock_rate = sysinfo->cpu_clock_hz;
470 }
471
472
473
474
475
476 if (!octeon_is_simulation() &&
477 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
478 cvmx_write_csr(CVMX_LED_EN, 0);
479 cvmx_write_csr(CVMX_LED_PRT, 0);
480 cvmx_write_csr(CVMX_LED_DBG, 0);
481 cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
482 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
483 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
484 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
485 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
486 cvmx_write_csr(CVMX_LED_EN, 1);
487 }
488#ifdef CONFIG_CAVIUM_RESERVE32
489
490
491
492
493
494
495
496
497
498
499 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
500 0, 0, 2 << 20,
501 "CAVIUM_RESERVE32", 0);
502 if (addr < 0)
503 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
504 else
505 octeon_reserve32_memory = addr;
506#endif
507
508#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
509 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
510 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
511 } else {
512 uint32_t ebase = read_c0_ebase() & 0x3ffff000;
513#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
514
515 cvmx_l2c_lock_mem_region(ebase, 0x100);
516#endif
517#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
518
519 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
520#endif
521#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
522
523 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
524#endif
525#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
526 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
527 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
528#endif
529#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
530 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
531#endif
532 }
533#endif
534
535 octeon_check_cpu_bist();
536
537 octeon_uart = octeon_get_boot_uart();
538
539#ifdef CONFIG_SMP
540 octeon_write_lcd("LinuxSMP");
541#else
542 octeon_write_lcd("Linux");
543#endif
544
545#ifdef CONFIG_CAVIUM_GDB
546
547
548
549
550 if (octeon_get_boot_debug_flag()) {
551 cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num());
552 cvmx_read_csr(CVMX_CIU_DINT);
553 }
554#endif
555
556
557
558
559
560
561
562 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
563 OCTEON_IS_MODEL(OCTEON_CN31XX))
564 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
565 else
566 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
567
568
569 if (octeon_is_simulation())
570 MAX_MEMORY = 64ull << 20;
571
572 arcs_cmdline[0] = 0;
573 argc = octeon_boot_desc_ptr->argc;
574 for (i = 0; i < argc; i++) {
575 const char *arg =
576 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
577 if ((strncmp(arg, "MEM=", 4) == 0) ||
578 (strncmp(arg, "mem=", 4) == 0)) {
579 sscanf(arg + 4, "%llu", &MAX_MEMORY);
580 MAX_MEMORY <<= 20;
581 if (MAX_MEMORY == 0)
582 MAX_MEMORY = 32ull << 30;
583 } else if (strcmp(arg, "ecc_verbose") == 0) {
584#ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC
585 __cvmx_interrupt_ecc_report_single_bit_errors = 1;
586 pr_notice("Reporting of single bit ECC errors is "
587 "turned on\n");
588#endif
589 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
590 sizeof(arcs_cmdline) - 1) {
591 strcat(arcs_cmdline, " ");
592 strcat(arcs_cmdline, arg);
593 }
594 }
595
596 if (strstr(arcs_cmdline, "console=") == NULL) {
597#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
598 strcat(arcs_cmdline, " console=ttyS0,115200");
599#else
600 if (octeon_uart == 1)
601 strcat(arcs_cmdline, " console=ttyS1,115200");
602 else
603 strcat(arcs_cmdline, " console=ttyS0,115200");
604#endif
605 }
606
607 if (octeon_is_simulation()) {
608
609
610
611
612
613 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
614 }
615
616 mips_hpt_frequency = octeon_get_clock_rate();
617
618 octeon_init_cvmcount();
619 octeon_setup_delays();
620
621 _machine_restart = octeon_restart;
622 _machine_halt = octeon_halt;
623
624 octeon_user_io_init();
625 register_smp_ops(&octeon_smp_ops);
626}
627
628
629static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
630{
631 if (addr > *mem && addr < *mem + *size) {
632 u64 inc = addr - *mem;
633 add_memory_region(*mem, inc, BOOT_MEM_RAM);
634 *mem += inc;
635 *size -= inc;
636 }
637
638 if (addr == *mem && *size > PAGE_SIZE) {
639 *mem += PAGE_SIZE;
640 *size -= PAGE_SIZE;
641 }
642}
643
644void __init plat_mem_setup(void)
645{
646 uint64_t mem_alloc_size;
647 uint64_t total;
648 int64_t memory;
649
650 total = 0;
651
652
653 memory = __pa_symbol(&__init_begin) & PAGE_MASK;
654 mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory;
655 if (mem_alloc_size > 0) {
656 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
657 total += mem_alloc_size;
658 }
659
660
661
662
663
664
665
666
667 mem_alloc_size = 4 << 20;
668 if (mem_alloc_size > MAX_MEMORY)
669 mem_alloc_size = MAX_MEMORY;
670
671
672
673
674
675
676 cvmx_bootmem_lock();
677 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
678 && (total < MAX_MEMORY)) {
679#if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR)
680 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
681 __pa_symbol(&__init_end), -1,
682 0x100000,
683 CVMX_BOOTMEM_FLAG_NO_LOCKING);
684#elif defined(CONFIG_HIGHMEM)
685 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31,
686 0x100000,
687 CVMX_BOOTMEM_FLAG_NO_LOCKING);
688#else
689 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20,
690 0x100000,
691 CVMX_BOOTMEM_FLAG_NO_LOCKING);
692#endif
693 if (memory >= 0) {
694 u64 size = mem_alloc_size;
695
696
697
698
699
700
701
702 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
703 &memory, &size);
704 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
705 CVMX_PCIE_BAR1_PHYS_SIZE,
706 &memory, &size);
707
708
709
710
711
712
713 if (size)
714 add_memory_region(memory, size, BOOT_MEM_RAM);
715 total += mem_alloc_size;
716 } else {
717 break;
718 }
719 }
720 cvmx_bootmem_unlock();
721
722#ifdef CONFIG_CAVIUM_RESERVE32
723
724
725
726
727
728 if (octeon_reserve32_memory)
729 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
730#endif
731
732 if (total == 0)
733 panic("Unable to allocate memory from "
734 "cvmx_bootmem_phy_alloc\n");
735}
736
737
738
739
740
741int prom_putchar(char c)
742{
743 uint64_t lsrval;
744
745
746 do {
747 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
748 } while ((lsrval & 0x20) == 0);
749
750
751 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
752 return 1;
753}
754EXPORT_SYMBOL(prom_putchar);
755
756void prom_free_prom_memory(void)
757{
758 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
759
760 u32 insn;
761 u32 *foo;
762
763 foo = &insn;
764
765 asm volatile("# before" : : : "memory");
766 prefetch(foo);
767 asm volatile(
768 ".set push\n\t"
769 ".set noreorder\n\t"
770 "bal 1f\n\t"
771 "nop\n"
772 "1:\tlw %0,-12($31)\n\t"
773 ".set pop\n\t"
774 : "=r" (insn) : : "$31", "memory");
775
776 if ((insn >> 26) != 0x33)
777 panic("No PREF instruction at Core-14449 probe point.\n");
778
779 if (((insn >> 16) & 0x1f) != 28)
780 panic("Core-14449 WAR not in place (%04x).\n"
781 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn);
782 }
783#ifdef CONFIG_CAVIUM_DECODE_RSL
784 cvmx_interrupt_rsl_enable();
785
786
787 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
788 "RML/RSL", octeon_rlm_interrupt)) {
789 panic("Unable to request_irq(OCTEON_IRQ_RML)\n");
790 }
791#endif
792}
793