LXR linux/arch/mips/include/asm/mach-loongson/loongson.h

   1/*
   2 * Copyright (C) 2009 Lemote, Inc.
   3 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
   4 *
   5 * This program is free software; you can redistribute  it and/or modify it
   6 * under  the terms of  the GNU General  Public License as published by the
   7 * Free Software Foundation;  either version 2 of the  License, or (at your
   8 * option) any later version.
   9 */
  10
  11#ifndef __ASM_MACH_LOONGSON_LOONGSON_H
  12#define __ASM_MACH_LOONGSON_LOONGSON_H
  13
  14#include <linux/io.h>
  15#include <linux/init.h>
  16#include <linux/irq.h>
  17
  18/* loongson internal northbridge initialization */
  19extern void bonito_irq_init(void);
  20
  21/* machine-specific reboot/halt operation */
  22extern void mach_prepare_reboot(void);
  23extern void mach_prepare_shutdown(void);
  24
  25/* environment arguments from bootloader */
  26extern unsigned long cpu_clock_freq;
  27extern unsigned long memsize, highmemsize;
  28
  29/* loongson-specific command line, env and memory initialization */
  30extern void __init prom_init_memory(void);
  31extern void __init prom_init_cmdline(void);
  32extern void __init prom_init_machtype(void);
  33extern void __init prom_init_env(void);
  34#ifdef CONFIG_LOONGSON_UART_BASE
  35extern unsigned long _loongson_uart_base, loongson_uart_base;
  36extern void prom_init_loongson_uart_base(void);
  37#endif
  38
  39static inline void prom_init_uart_base(void)
  40{
  41#ifdef CONFIG_LOONGSON_UART_BASE
  42        prom_init_loongson_uart_base();
  43#endif
  44}
  45
  46/* irq operation functions */
  47extern void bonito_irqdispatch(void);
  48extern void __init bonito_irq_init(void);
  49extern void __init mach_init_irq(void);
  50extern void mach_irq_dispatch(unsigned int pending);
  51extern int mach_i8259_irq(void);
  52
  53/* We need this in some places... */
  54#define delay() ({              \
  55        int x;                          \
  56        for (x = 0; x < 100000; x++)    \
  57                __asm__ __volatile__(""); \
  58})
  59
  60#define LOONGSON_REG(x) \
  61        (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
  62
  63#define LOONGSON_IRQ_BASE       32
  64#define LOONGSON2_PERFCNT_IRQ   (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
  65
  66#include <linux/interrupt.h>
  67static inline void do_perfcnt_IRQ(void)
  68{
  69#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE)
  70        do_IRQ(LOONGSON2_PERFCNT_IRQ);
  71#endif
  72}
  73
  74#define LOONGSON_FLASH_BASE     0x1c000000
  75#define LOONGSON_FLASH_SIZE     0x02000000      /* 32M */
  76#define LOONGSON_FLASH_TOP      (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
  77
  78#define LOONGSON_LIO0_BASE      0x1e000000
  79#define LOONGSON_LIO0_SIZE      0x01C00000      /* 28M */
  80#define LOONGSON_LIO0_TOP       (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
  81
  82#define LOONGSON_BOOT_BASE      0x1fc00000
  83#define LOONGSON_BOOT_SIZE      0x00100000      /* 1M */
  84#define LOONGSON_BOOT_TOP       (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
  85#define LOONGSON_REG_BASE       0x1fe00000
  86#define LOONGSON_REG_SIZE       0x00100000      /* 256Bytes + 256Bytes + ??? */
  87#define LOONGSON_REG_TOP        (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
  88
  89#define LOONGSON_LIO1_BASE      0x1ff00000
  90#define LOONGSON_LIO1_SIZE      0x00100000      /* 1M */
  91#define LOONGSON_LIO1_TOP       (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
  92
  93#define LOONGSON_PCILO0_BASE    0x10000000
  94#define LOONGSON_PCILO1_BASE    0x14000000
  95#define LOONGSON_PCILO2_BASE    0x18000000
  96#define LOONGSON_PCILO_BASE     LOONGSON_PCILO0_BASE
  97#define LOONGSON_PCILO_SIZE     0x0c000000      /* 64M * 3 */
  98#define LOONGSON_PCILO_TOP      (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
  99
 100#define LOONGSON_PCICFG_BASE    0x1fe80000
 101#define LOONGSON_PCICFG_SIZE    0x00000800      /* 2K */
 102#define LOONGSON_PCICFG_TOP     (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
 103#define LOONGSON_PCIIO_BASE     0x1fd00000
 104#define LOONGSON_PCIIO_SIZE     0x00100000      /* 1M */
 105#define LOONGSON_PCIIO_TOP      (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
 106
 107/* Loongson Register Bases */
 108
 109#define LOONGSON_PCICONFIGBASE  0x00
 110#define LOONGSON_REGBASE        0x100
 111
 112/* PCI Configuration Registers */
 113
 114#define LOONGSON_PCI_REG(x)     LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
 115#define LOONGSON_PCIDID         LOONGSON_PCI_REG(0x00)
 116#define LOONGSON_PCICMD         LOONGSON_PCI_REG(0x04)
 117#define LOONGSON_PCICLASS       LOONGSON_PCI_REG(0x08)
 118#define LOONGSON_PCILTIMER      LOONGSON_PCI_REG(0x0c)
 119#define LOONGSON_PCIBASE0       LOONGSON_PCI_REG(0x10)
 120#define LOONGSON_PCIBASE1       LOONGSON_PCI_REG(0x14)
 121#define LOONGSON_PCIBASE2       LOONGSON_PCI_REG(0x18)
 122#define LOONGSON_PCIBASE3       LOONGSON_PCI_REG(0x1c)
 123#define LOONGSON_PCIBASE4       LOONGSON_PCI_REG(0x20)
 124#define LOONGSON_PCIEXPRBASE    LOONGSON_PCI_REG(0x30)
 125#define LOONGSON_PCIINT         LOONGSON_PCI_REG(0x3c)
 126
 127#define LOONGSON_PCI_ISR4C      LOONGSON_PCI_REG(0x4c)
 128
 129#define LOONGSON_PCICMD_PERR_CLR        0x80000000
 130#define LOONGSON_PCICMD_SERR_CLR        0x40000000
 131#define LOONGSON_PCICMD_MABORT_CLR      0x20000000
 132#define LOONGSON_PCICMD_MTABORT_CLR     0x10000000
 133#define LOONGSON_PCICMD_TABORT_CLR      0x08000000
 134#define LOONGSON_PCICMD_MPERR_CLR       0x01000000
 135#define LOONGSON_PCICMD_PERRRESPEN      0x00000040
 136#define LOONGSON_PCICMD_ASTEPEN         0x00000080
 137#define LOONGSON_PCICMD_SERREN          0x00000100
 138#define LOONGSON_PCILTIMER_BUSLATENCY   0x0000ff00
 139#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT     8
 140
 141/* Loongson h/w Configuration */
 142
 143#define LOONGSON_GENCFG_OFFSET          0x4
 144#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
 145
 146#define LOONGSON_GENCFG_DEBUGMODE       0x00000001
 147#define LOONGSON_GENCFG_SNOOPEN         0x00000002
 148#define LOONGSON_GENCFG_CPUSELFRESET    0x00000004
 149
 150#define LOONGSON_GENCFG_FORCE_IRQA      0x00000008
 151#define LOONGSON_GENCFG_IRQA_ISOUT      0x00000010
 152#define LOONGSON_GENCFG_IRQA_FROM_INT1  0x00000020
 153#define LOONGSON_GENCFG_BYTESWAP        0x00000040
 154
 155#define LOONGSON_GENCFG_UNCACHED        0x00000080
 156#define LOONGSON_GENCFG_PREFETCHEN      0x00000100
 157#define LOONGSON_GENCFG_WBEHINDEN       0x00000200
 158#define LOONGSON_GENCFG_CACHEALG        0x00000c00
 159#define LOONGSON_GENCFG_CACHEALG_SHIFT  10
 160#define LOONGSON_GENCFG_PCIQUEUE        0x00001000
 161#define LOONGSON_GENCFG_CACHESTOP       0x00002000
 162#define LOONGSON_GENCFG_MSTRBYTESWAP    0x00004000
 163#define LOONGSON_GENCFG_BUSERREN        0x00008000
 164#define LOONGSON_GENCFG_NORETRYTIMEOUT  0x00010000
 165#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT        0x00020000
 166
 167/* PCI address map control */
 168
 169#define LOONGSON_PCIMAP                 LOONGSON_REG(LOONGSON_REGBASE + 0x10)
 170#define LOONGSON_PCIMEMBASECFG          LOONGSON_REG(LOONGSON_REGBASE + 0x14)
 171#define LOONGSON_PCIMAP_CFG             LOONGSON_REG(LOONGSON_REGBASE + 0x18)
 172
 173/* GPIO Regs - r/w */
 174
 175#define LOONGSON_GPIODATA               LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
 176#define LOONGSON_GPIOIE                 LOONGSON_REG(LOONGSON_REGBASE + 0x20)
 177
 178/* ICU Configuration Regs - r/w */
 179
 180#define LOONGSON_INTEDGE                LOONGSON_REG(LOONGSON_REGBASE + 0x24)
 181#define LOONGSON_INTSTEER               LOONGSON_REG(LOONGSON_REGBASE + 0x28)
 182#define LOONGSON_INTPOL                 LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
 183
 184/* ICU Enable Regs - IntEn & IntISR are r/o. */
 185
 186#define LOONGSON_INTENSET               LOONGSON_REG(LOONGSON_REGBASE + 0x30)
 187#define LOONGSON_INTENCLR               LOONGSON_REG(LOONGSON_REGBASE + 0x34)
 188#define LOONGSON_INTEN                  LOONGSON_REG(LOONGSON_REGBASE + 0x38)
 189#define LOONGSON_INTISR                 LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
 190
 191/* ICU */
 192#define LOONGSON_ICU_MBOXES             0x0000000f
 193#define LOONGSON_ICU_MBOXES_SHIFT       0
 194#define LOONGSON_ICU_DMARDY             0x00000010
 195#define LOONGSON_ICU_DMAEMPTY           0x00000020
 196#define LOONGSON_ICU_COPYRDY            0x00000040
 197#define LOONGSON_ICU_COPYEMPTY          0x00000080
 198#define LOONGSON_ICU_COPYERR            0x00000100
 199#define LOONGSON_ICU_PCIIRQ             0x00000200
 200#define LOONGSON_ICU_MASTERERR          0x00000400
 201#define LOONGSON_ICU_SYSTEMERR          0x00000800
 202#define LOONGSON_ICU_DRAMPERR           0x00001000
 203#define LOONGSON_ICU_RETRYERR           0x00002000
 204#define LOONGSON_ICU_GPIOS              0x01ff0000
 205#define LOONGSON_ICU_GPIOS_SHIFT                16
 206#define LOONGSON_ICU_GPINS              0x7e000000
 207#define LOONGSON_ICU_GPINS_SHIFT                25
 208#define LOONGSON_ICU_MBOX(N)            (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
 209#define LOONGSON_ICU_GPIO(N)            (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
 210#define LOONGSON_ICU_GPIN(N)            (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
 211
 212/* PCI prefetch window base & mask */
 213
 214#define LOONGSON_MEM_WIN_BASE_L         LOONGSON_REG(LOONGSON_REGBASE + 0x40)
 215#define LOONGSON_MEM_WIN_BASE_H         LOONGSON_REG(LOONGSON_REGBASE + 0x44)
 216#define LOONGSON_MEM_WIN_MASK_L         LOONGSON_REG(LOONGSON_REGBASE + 0x48)
 217#define LOONGSON_MEM_WIN_MASK_H         LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
 218
 219/* PCI_Hit*_Sel_* */
 220
 221#define LOONGSON_PCI_HIT0_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x50)
 222#define LOONGSON_PCI_HIT0_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x54)
 223#define LOONGSON_PCI_HIT1_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x58)
 224#define LOONGSON_PCI_HIT1_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
 225#define LOONGSON_PCI_HIT2_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x60)
 226#define LOONGSON_PCI_HIT2_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x64)
 227
 228/* PXArb Config & Status */
 229
 230#define LOONGSON_PXARB_CFG              LOONGSON_REG(LOONGSON_REGBASE + 0x68)
 231#define LOONGSON_PXARB_STATUS           LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
 232
 233/* pcimap */
 234
 235#define LOONGSON_PCIMAP_PCIMAP_LO0      0x0000003f
 236#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT        0
 237#define LOONGSON_PCIMAP_PCIMAP_LO1      0x00000fc0
 238#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT        6
 239#define LOONGSON_PCIMAP_PCIMAP_LO2      0x0003f000
 240#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT        12
 241#define LOONGSON_PCIMAP_PCIMAP_2        0x00040000
 242#define LOONGSON_PCIMAP_WIN(WIN, ADDR)  \
 243        ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
 244
 245#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
 246#include <linux/cpufreq.h>
 247extern void loongson2_cpu_wait(void);
 248extern struct cpufreq_frequency_table loongson2_clockmod_table[];
 249
 250/* Chip Config */
 251#define LOONGSON_CHIPCFG0               LOONGSON_REG(LOONGSON_REGBASE + 0x80)
 252#endif
 253
 254/*
 255 * address windows configuration module
 256 *
 257 * loongson2e do not have this module
 258 */
 259#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
 260
 261/* address window config module base address */
 262#define LOONGSON_ADDRWINCFG_BASE                0x3ff00000ul
 263#define LOONGSON_ADDRWINCFG_SIZE                0x180
 264
 265extern unsigned long _loongson_addrwincfg_base;
 266#define LOONGSON_ADDRWINCFG(offset) \
 267        (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
 268
 269#define CPU_WIN0_BASE   LOONGSON_ADDRWINCFG(0x00)
 270#define CPU_WIN1_BASE   LOONGSON_ADDRWINCFG(0x08)
 271#define CPU_WIN2_BASE   LOONGSON_ADDRWINCFG(0x10)
 272#define CPU_WIN3_BASE   LOONGSON_ADDRWINCFG(0x18)
 273
 274#define CPU_WIN0_MASK   LOONGSON_ADDRWINCFG(0x20)
 275#define CPU_WIN1_MASK   LOONGSON_ADDRWINCFG(0x28)
 276#define CPU_WIN2_MASK   LOONGSON_ADDRWINCFG(0x30)
 277#define CPU_WIN3_MASK   LOONGSON_ADDRWINCFG(0x38)
 278
 279#define CPU_WIN0_MMAP   LOONGSON_ADDRWINCFG(0x40)
 280#define CPU_WIN1_MMAP   LOONGSON_ADDRWINCFG(0x48)
 281#define CPU_WIN2_MMAP   LOONGSON_ADDRWINCFG(0x50)
 282#define CPU_WIN3_MMAP   LOONGSON_ADDRWINCFG(0x58)
 283
 284#define PCIDMA_WIN0_BASE        LOONGSON_ADDRWINCFG(0x60)
 285#define PCIDMA_WIN1_BASE        LOONGSON_ADDRWINCFG(0x68)
 286#define PCIDMA_WIN2_BASE        LOONGSON_ADDRWINCFG(0x70)
 287#define PCIDMA_WIN3_BASE        LOONGSON_ADDRWINCFG(0x78)
 288
 289#define PCIDMA_WIN0_MASK        LOONGSON_ADDRWINCFG(0x80)
 290#define PCIDMA_WIN1_MASK        LOONGSON_ADDRWINCFG(0x88)
 291#define PCIDMA_WIN2_MASK        LOONGSON_ADDRWINCFG(0x90)
 292#define PCIDMA_WIN3_MASK        LOONGSON_ADDRWINCFG(0x98)
 293
 294#define PCIDMA_WIN0_MMAP        LOONGSON_ADDRWINCFG(0xa0)
 295#define PCIDMA_WIN1_MMAP        LOONGSON_ADDRWINCFG(0xa8)
 296#define PCIDMA_WIN2_MMAP        LOONGSON_ADDRWINCFG(0xb0)
 297#define PCIDMA_WIN3_MMAP        LOONGSON_ADDRWINCFG(0xb8)
 298
 299#define ADDRWIN_WIN0    0
 300#define ADDRWIN_WIN1    1
 301#define ADDRWIN_WIN2    2
 302#define ADDRWIN_WIN3    3
 303
 304#define ADDRWIN_MAP_DST_DDR     0
 305#define ADDRWIN_MAP_DST_PCI     1
 306#define ADDRWIN_MAP_DST_LIO     1
 307
 308/*
 309 * s: CPU, PCIDMA
 310 * d: DDR, PCI, LIO
 311 * win: 0, 1, 2, 3
 312 * src: map source
 313 * dst: map destination
 314 * size: ~mask + 1
 315 */
 316#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
 317        s##_WIN##w##_BASE = (src); \
 318        s##_WIN##w##_MMAP = (dst) | ADDRWIN_MAP_DST_##d; \
 319        s##_WIN##w##_MASK = ~(size-1); \
 320} while (0)
 321
 322#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
 323        LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
 324#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
 325        LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
 326#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
 327        LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
 328
 329#endif  /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
 330
 331#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
 332