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28#include "linux/string.h"
29#include "linux/bitops.h"
30#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
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87
88void
89i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
90{
91 drm_i915_private_t *dev_priv = dev->dev_private;
92 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
93 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
94
95 if (IS_GEN5(dev) || IS_GEN6(dev)) {
96
97
98
99 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
100 swizzle_y = I915_BIT_6_SWIZZLE_9;
101 } else if (IS_GEN2(dev)) {
102
103
104
105 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
106 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
107 } else if (IS_MOBILE(dev)) {
108 uint32_t dcc;
109
110
111
112
113
114
115
116
117
118 dcc = I915_READ(DCC);
119 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
120 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
121 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
122 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
123 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
124 break;
125 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
126 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
127
128
129
130 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
131 swizzle_y = I915_BIT_6_SWIZZLE_9;
132 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
133
134 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
135 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
136 } else {
137
138 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
139 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
140 }
141 break;
142 }
143 if (dcc == 0xffffffff) {
144 DRM_ERROR("Couldn't read from MCHBAR. "
145 "Disabling tiling.\n");
146 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
147 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
148 }
149 } else {
150
151
152
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159
160
161
162
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164
165
166
167
168
169
170 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
171 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
172 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
173 } else {
174 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
175 swizzle_y = I915_BIT_6_SWIZZLE_9;
176 }
177 }
178
179 dev_priv->mm.bit_6_swizzle_x = swizzle_x;
180 dev_priv->mm.bit_6_swizzle_y = swizzle_y;
181}
182
183
184static bool
185i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
186{
187 int tile_width;
188
189
190 if (tiling_mode == I915_TILING_NONE)
191 return true;
192
193 if (IS_GEN2(dev) ||
194 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
195 tile_width = 128;
196 else
197 tile_width = 512;
198
199
200 if (INTEL_INFO(dev)->gen >= 4) {
201
202
203 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
204 return false;
205 } else {
206 if (stride > 8192)
207 return false;
208
209 if (IS_GEN3(dev)) {
210 if (size > I830_FENCE_MAX_SIZE_VAL << 20)
211 return false;
212 } else {
213 if (size > I830_FENCE_MAX_SIZE_VAL << 19)
214 return false;
215 }
216 }
217
218
219 if (INTEL_INFO(dev)->gen >= 4) {
220 if (stride & (tile_width - 1))
221 return false;
222 return true;
223 }
224
225
226 if (stride < tile_width)
227 return false;
228
229 if (stride & (stride - 1))
230 return false;
231
232 return true;
233}
234
235
236static bool
237i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
238{
239 u32 size;
240
241 if (tiling_mode == I915_TILING_NONE)
242 return true;
243
244 if (INTEL_INFO(obj->base.dev)->gen >= 4)
245 return true;
246
247 if (INTEL_INFO(obj->base.dev)->gen == 3) {
248 if (obj->gtt_offset & ~I915_FENCE_START_MASK)
249 return false;
250 } else {
251 if (obj->gtt_offset & ~I830_FENCE_START_MASK)
252 return false;
253 }
254
255
256
257
258
259 if (INTEL_INFO(obj->base.dev)->gen == 3)
260 size = 1024*1024;
261 else
262 size = 512*1024;
263
264 while (size < obj->base.size)
265 size <<= 1;
266
267 if (obj->gtt_space->size != size)
268 return false;
269
270 if (obj->gtt_offset & (size - 1))
271 return false;
272
273 return true;
274}
275
276
277
278
279
280int
281i915_gem_set_tiling(struct drm_device *dev, void *data,
282 struct drm_file *file)
283{
284 struct drm_i915_gem_set_tiling *args = data;
285 drm_i915_private_t *dev_priv = dev->dev_private;
286 struct drm_i915_gem_object *obj;
287 int ret = 0;
288
289 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
290 if (&obj->base == NULL)
291 return -ENOENT;
292
293 if (!i915_tiling_ok(dev,
294 args->stride, obj->base.size, args->tiling_mode)) {
295 drm_gem_object_unreference_unlocked(&obj->base);
296 return -EINVAL;
297 }
298
299 if (obj->pin_count) {
300 drm_gem_object_unreference_unlocked(&obj->base);
301 return -EBUSY;
302 }
303
304 if (args->tiling_mode == I915_TILING_NONE) {
305 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
306 args->stride = 0;
307 } else {
308 if (args->tiling_mode == I915_TILING_X)
309 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
310 else
311 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
312
313
314
315
316
317
318
319
320 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
321 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
322 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
323 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
324
325
326 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
327 args->tiling_mode = I915_TILING_NONE;
328 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
329 args->stride = 0;
330 }
331 }
332
333 mutex_lock(&dev->struct_mutex);
334 if (args->tiling_mode != obj->tiling_mode ||
335 args->stride != obj->stride) {
336
337
338
339
340
341 i915_gem_release_mmap(obj);
342
343 obj->map_and_fenceable =
344 obj->gtt_space == NULL ||
345 (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end &&
346 i915_gem_object_fence_ok(obj, args->tiling_mode));
347
348
349 if (!obj->map_and_fenceable) {
350 u32 unfenced_alignment =
351 i915_gem_get_unfenced_gtt_alignment(obj);
352 if (obj->gtt_offset & (unfenced_alignment - 1))
353 ret = i915_gem_object_unbind(obj);
354 }
355
356 if (ret == 0) {
357 obj->tiling_changed = true;
358 obj->tiling_mode = args->tiling_mode;
359 obj->stride = args->stride;
360 }
361 }
362
363 args->stride = obj->stride;
364 args->tiling_mode = obj->tiling_mode;
365 drm_gem_object_unreference(&obj->base);
366 mutex_unlock(&dev->struct_mutex);
367
368 return ret;
369}
370
371
372
373
374int
375i915_gem_get_tiling(struct drm_device *dev, void *data,
376 struct drm_file *file)
377{
378 struct drm_i915_gem_get_tiling *args = data;
379 drm_i915_private_t *dev_priv = dev->dev_private;
380 struct drm_i915_gem_object *obj;
381
382 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
383 if (&obj->base == NULL)
384 return -ENOENT;
385
386 mutex_lock(&dev->struct_mutex);
387
388 args->tiling_mode = obj->tiling_mode;
389 switch (obj->tiling_mode) {
390 case I915_TILING_X:
391 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
392 break;
393 case I915_TILING_Y:
394 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
395 break;
396 case I915_TILING_NONE:
397 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
398 break;
399 default:
400 DRM_ERROR("unknown tiling mode\n");
401 }
402
403
404 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
405 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
406 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
407 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
408
409 drm_gem_object_unreference(&obj->base);
410 mutex_unlock(&dev->struct_mutex);
411
412 return 0;
413}
414
415
416
417
418
419
420static void
421i915_gem_swizzle_page(struct page *page)
422{
423 char temp[64];
424 char *vaddr;
425 int i;
426
427 vaddr = kmap(page);
428
429 for (i = 0; i < PAGE_SIZE; i += 128) {
430 memcpy(temp, &vaddr[i], 64);
431 memcpy(&vaddr[i], &vaddr[i + 64], 64);
432 memcpy(&vaddr[i + 64], temp, 64);
433 }
434
435 kunmap(page);
436}
437
438void
439i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
440{
441 struct drm_device *dev = obj->base.dev;
442 drm_i915_private_t *dev_priv = dev->dev_private;
443 int page_count = obj->base.size >> PAGE_SHIFT;
444 int i;
445
446 if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
447 return;
448
449 if (obj->bit_17 == NULL)
450 return;
451
452 for (i = 0; i < page_count; i++) {
453 char new_bit_17 = page_to_phys(obj->pages[i]) >> 17;
454 if ((new_bit_17 & 0x1) !=
455 (test_bit(i, obj->bit_17) != 0)) {
456 i915_gem_swizzle_page(obj->pages[i]);
457 set_page_dirty(obj->pages[i]);
458 }
459 }
460}
461
462void
463i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
464{
465 struct drm_device *dev = obj->base.dev;
466 drm_i915_private_t *dev_priv = dev->dev_private;
467 int page_count = obj->base.size >> PAGE_SHIFT;
468 int i;
469
470 if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
471 return;
472
473 if (obj->bit_17 == NULL) {
474 obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
475 sizeof(long), GFP_KERNEL);
476 if (obj->bit_17 == NULL) {
477 DRM_ERROR("Failed to allocate memory for bit 17 "
478 "record\n");
479 return;
480 }
481 }
482
483 for (i = 0; i < page_count; i++) {
484 if (page_to_phys(obj->pages[i]) & (1 << 17))
485 __set_bit(i, obj->bit_17);
486 else
487 __clear_bit(i, obj->bit_17);
488 }
489}
490