1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28#include "ixgbe.h"
29#ifdef CONFIG_IXGBE_DCB
30#include "ixgbe_dcb_82599.h"
31#endif
32#include <linux/if_ether.h>
33#include <linux/gfp.h>
34#include <linux/if_vlan.h>
35#include <scsi/scsi_cmnd.h>
36#include <scsi/scsi_device.h>
37#include <scsi/fc/fc_fs.h>
38#include <scsi/fc/fc_fcoe.h>
39#include <scsi/libfc.h>
40#include <scsi/libfcoe.h>
41
42
43
44
45
46
47
48static inline bool ixgbe_rx_is_fcoe(union ixgbe_adv_rx_desc *rx_desc)
49{
50 u16 p;
51
52 p = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info);
53 if (p & IXGBE_RXDADV_PKTTYPE_ETQF) {
54 p &= IXGBE_RXDADV_PKTTYPE_ETQF_MASK;
55 p >>= IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT;
56 return p == IXGBE_ETQF_FILTER_FCOE;
57 }
58 return false;
59}
60
61
62
63
64
65
66
67
68static inline void ixgbe_fcoe_clear_ddp(struct ixgbe_fcoe_ddp *ddp)
69{
70 ddp->len = 0;
71 ddp->err = 1;
72 ddp->udl = NULL;
73 ddp->udp = 0UL;
74 ddp->sgl = NULL;
75 ddp->sgc = 0;
76}
77
78
79
80
81
82
83
84
85
86
87
88
89int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid)
90{
91 int len = 0;
92 struct ixgbe_fcoe *fcoe;
93 struct ixgbe_adapter *adapter;
94 struct ixgbe_fcoe_ddp *ddp;
95 u32 fcbuff;
96
97 if (!netdev)
98 goto out_ddp_put;
99
100 if (xid >= IXGBE_FCOE_DDP_MAX)
101 goto out_ddp_put;
102
103 adapter = netdev_priv(netdev);
104 fcoe = &adapter->fcoe;
105 ddp = &fcoe->ddp[xid];
106 if (!ddp->udl)
107 goto out_ddp_put;
108
109 len = ddp->len;
110
111 if (ddp->err) {
112 spin_lock_bh(&fcoe->lock);
113 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLT, 0);
114 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLTRW,
115 (xid | IXGBE_FCFLTRW_WE));
116 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCBUFF, 0);
117 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCDMARW,
118 (xid | IXGBE_FCDMARW_WE));
119
120
121 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCDMARW,
122 (xid | IXGBE_FCDMARW_RE));
123 fcbuff = IXGBE_READ_REG(&adapter->hw, IXGBE_FCBUFF);
124 spin_unlock_bh(&fcoe->lock);
125 if (fcbuff & IXGBE_FCBUFF_VALID)
126 udelay(100);
127 }
128 if (ddp->sgl)
129 pci_unmap_sg(adapter->pdev, ddp->sgl, ddp->sgc,
130 DMA_FROM_DEVICE);
131 pci_pool_free(fcoe->pool, ddp->udl, ddp->udp);
132 ixgbe_fcoe_clear_ddp(ddp);
133
134out_ddp_put:
135 return len;
136}
137
138
139
140
141
142
143
144
145
146
147
148static int ixgbe_fcoe_ddp_setup(struct net_device *netdev, u16 xid,
149 struct scatterlist *sgl, unsigned int sgc,
150 int target_mode)
151{
152 struct ixgbe_adapter *adapter;
153 struct ixgbe_hw *hw;
154 struct ixgbe_fcoe *fcoe;
155 struct ixgbe_fcoe_ddp *ddp;
156 struct scatterlist *sg;
157 unsigned int i, j, dmacount;
158 unsigned int len;
159 static const unsigned int bufflen = IXGBE_FCBUFF_MIN;
160 unsigned int firstoff = 0;
161 unsigned int lastsize;
162 unsigned int thisoff = 0;
163 unsigned int thislen = 0;
164 u32 fcbuff, fcdmarw, fcfltrw, fcrxctl;
165 dma_addr_t addr = 0;
166
167 if (!netdev || !sgl)
168 return 0;
169
170 adapter = netdev_priv(netdev);
171 if (xid >= IXGBE_FCOE_DDP_MAX) {
172 e_warn(drv, "xid=0x%x out-of-range\n", xid);
173 return 0;
174 }
175
176
177 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
178 test_bit(__IXGBE_RESETTING, &adapter->state))
179 return 0;
180
181 fcoe = &adapter->fcoe;
182 if (!fcoe->pool) {
183 e_warn(drv, "xid=0x%x no ddp pool for fcoe\n", xid);
184 return 0;
185 }
186
187 ddp = &fcoe->ddp[xid];
188 if (ddp->sgl) {
189 e_err(drv, "xid 0x%x w/ non-null sgl=%p nents=%d\n",
190 xid, ddp->sgl, ddp->sgc);
191 return 0;
192 }
193 ixgbe_fcoe_clear_ddp(ddp);
194
195
196 dmacount = pci_map_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE);
197 if (dmacount == 0) {
198 e_err(drv, "xid 0x%x DMA map error\n", xid);
199 return 0;
200 }
201
202
203 ddp->udl = pci_pool_alloc(fcoe->pool, GFP_ATOMIC, &ddp->udp);
204 if (!ddp->udl) {
205 e_err(drv, "failed allocated ddp context\n");
206 goto out_noddp_unmap;
207 }
208 ddp->sgl = sgl;
209 ddp->sgc = sgc;
210
211 j = 0;
212 for_each_sg(sgl, sg, dmacount, i) {
213 addr = sg_dma_address(sg);
214 len = sg_dma_len(sg);
215 while (len) {
216
217 if (j >= IXGBE_BUFFCNT_MAX) {
218 e_err(drv, "xid=%x:%d,%d,%d:addr=%llx "
219 "not enough descriptors\n",
220 xid, i, j, dmacount, (u64)addr);
221 goto out_noddp_free;
222 }
223
224
225 thisoff = addr & ((dma_addr_t)bufflen - 1);
226 thislen = min((bufflen - thisoff), len);
227
228
229
230
231 if ((j != 0) && (thisoff))
232 goto out_noddp_free;
233
234
235
236
237
238 if (((i != (dmacount - 1)) || (thislen != len))
239 && ((thislen + thisoff) != bufflen))
240 goto out_noddp_free;
241
242 ddp->udl[j] = (u64)(addr - thisoff);
243
244 if (j == 0)
245 firstoff = thisoff;
246 len -= thislen;
247 addr += thislen;
248 j++;
249 }
250 }
251
252 lastsize = thisoff + thislen;
253
254
255
256
257
258 if (lastsize == bufflen) {
259 if (j >= IXGBE_BUFFCNT_MAX) {
260 e_err(drv, "xid=%x:%d,%d,%d:addr=%llx "
261 "not enough user buffers. We need an extra "
262 "buffer because lastsize is bufflen.\n",
263 xid, i, j, dmacount, (u64)addr);
264 goto out_noddp_free;
265 }
266
267 ddp->udl[j] = (u64)(fcoe->extra_ddp_buffer_dma);
268 j++;
269 lastsize = 1;
270 }
271
272 fcbuff = (IXGBE_FCBUFF_4KB << IXGBE_FCBUFF_BUFFSIZE_SHIFT);
273 fcbuff |= ((j & 0xff) << IXGBE_FCBUFF_BUFFCNT_SHIFT);
274 fcbuff |= (firstoff << IXGBE_FCBUFF_OFFSET_SHIFT);
275
276 if (target_mode)
277 fcbuff |= (IXGBE_FCBUFF_WRCONTX);
278 fcbuff |= (IXGBE_FCBUFF_VALID);
279
280 fcdmarw = xid;
281 fcdmarw |= IXGBE_FCDMARW_WE;
282 fcdmarw |= (lastsize << IXGBE_FCDMARW_LASTSIZE_SHIFT);
283
284 fcfltrw = xid;
285 fcfltrw |= IXGBE_FCFLTRW_WE;
286
287
288 hw = &adapter->hw;
289 spin_lock_bh(&fcoe->lock);
290
291
292
293 if (target_mode && !test_bit(__IXGBE_FCOE_TARGET, &fcoe->mode)) {
294 set_bit(__IXGBE_FCOE_TARGET, &fcoe->mode);
295 fcrxctl = IXGBE_READ_REG(hw, IXGBE_FCRXCTRL);
296 fcrxctl |= IXGBE_FCRXCTRL_LASTSEQH;
297 IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL, fcrxctl);
298 }
299
300 IXGBE_WRITE_REG(hw, IXGBE_FCPTRL, ddp->udp & DMA_BIT_MASK(32));
301 IXGBE_WRITE_REG(hw, IXGBE_FCPTRH, (u64)ddp->udp >> 32);
302 IXGBE_WRITE_REG(hw, IXGBE_FCBUFF, fcbuff);
303 IXGBE_WRITE_REG(hw, IXGBE_FCDMARW, fcdmarw);
304
305 IXGBE_WRITE_REG(hw, IXGBE_FCPARAM, 0);
306 IXGBE_WRITE_REG(hw, IXGBE_FCFLT, IXGBE_FCFLT_VALID);
307 IXGBE_WRITE_REG(hw, IXGBE_FCFLTRW, fcfltrw);
308
309 spin_unlock_bh(&fcoe->lock);
310
311 return 1;
312
313out_noddp_free:
314 pci_pool_free(fcoe->pool, ddp->udl, ddp->udp);
315 ixgbe_fcoe_clear_ddp(ddp);
316
317out_noddp_unmap:
318 pci_unmap_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE);
319 return 0;
320}
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
337 struct scatterlist *sgl, unsigned int sgc)
338{
339 return ixgbe_fcoe_ddp_setup(netdev, xid, sgl, sgc, 0);
340}
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
358 struct scatterlist *sgl, unsigned int sgc)
359{
360 return ixgbe_fcoe_ddp_setup(netdev, xid, sgl, sgc, 1);
361}
362
363
364
365
366
367
368
369
370
371
372
373
374
375int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
376 union ixgbe_adv_rx_desc *rx_desc,
377 struct sk_buff *skb)
378{
379 u16 xid;
380 u32 fctl;
381 u32 sterr, fceofe, fcerr, fcstat;
382 int rc = -EINVAL;
383 struct ixgbe_fcoe *fcoe;
384 struct ixgbe_fcoe_ddp *ddp;
385 struct fc_frame_header *fh;
386 struct fcoe_crc_eof *crc;
387
388 if (!ixgbe_rx_is_fcoe(rx_desc))
389 goto ddp_out;
390
391 sterr = le32_to_cpu(rx_desc->wb.upper.status_error);
392 fcerr = (sterr & IXGBE_RXDADV_ERR_FCERR);
393 fceofe = (sterr & IXGBE_RXDADV_ERR_FCEOFE);
394 if (fcerr == IXGBE_FCERR_BADCRC)
395 skb_checksum_none_assert(skb);
396 else
397 skb->ip_summed = CHECKSUM_UNNECESSARY;
398
399 if (eth_hdr(skb)->h_proto == htons(ETH_P_8021Q))
400 fh = (struct fc_frame_header *)(skb->data +
401 sizeof(struct vlan_hdr) + sizeof(struct fcoe_hdr));
402 else
403 fh = (struct fc_frame_header *)(skb->data +
404 sizeof(struct fcoe_hdr));
405 fctl = ntoh24(fh->fh_f_ctl);
406 if (fctl & FC_FC_EX_CTX)
407 xid = be16_to_cpu(fh->fh_ox_id);
408 else
409 xid = be16_to_cpu(fh->fh_rx_id);
410
411 if (xid >= IXGBE_FCOE_DDP_MAX)
412 goto ddp_out;
413
414 fcoe = &adapter->fcoe;
415 ddp = &fcoe->ddp[xid];
416 if (!ddp->udl)
417 goto ddp_out;
418
419 ddp->err = (fcerr | fceofe);
420 if (ddp->err)
421 goto ddp_out;
422
423 fcstat = (sterr & IXGBE_RXDADV_STAT_FCSTAT);
424 if (fcstat) {
425
426 ddp->len = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
427
428 if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_FCPRSP) {
429 pci_unmap_sg(adapter->pdev, ddp->sgl,
430 ddp->sgc, DMA_FROM_DEVICE);
431 ddp->sgl = NULL;
432 ddp->sgc = 0;
433 }
434
435 if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_DDP)
436 rc = 0;
437 else if (ddp->len)
438 rc = ddp->len;
439 }
440
441
442
443
444
445
446
447 if ((fh->fh_r_ctl == FC_RCTL_DD_SOL_DATA) &&
448 (fctl & FC_FC_END_SEQ)) {
449 crc = (struct fcoe_crc_eof *)skb_put(skb, sizeof(*crc));
450 crc->fcoe_eof = FC_EOF_T;
451 }
452ddp_out:
453 return rc;
454}
455
456
457
458
459
460
461
462
463
464
465
466
467
468int ixgbe_fso(struct ixgbe_adapter *adapter,
469 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
470 u32 tx_flags, u8 *hdr_len)
471{
472 u8 sof, eof;
473 u32 vlan_macip_lens;
474 u32 fcoe_sof_eof;
475 u32 type_tucmd;
476 u32 mss_l4len_idx;
477 int mss = 0;
478 unsigned int i;
479 struct ixgbe_tx_buffer *tx_buffer_info;
480 struct ixgbe_adv_tx_context_desc *context_desc;
481 struct fc_frame_header *fh;
482
483 if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_type != SKB_GSO_FCOE)) {
484 e_err(drv, "Wrong gso type %d:expecting SKB_GSO_FCOE\n",
485 skb_shinfo(skb)->gso_type);
486 return -EINVAL;
487 }
488
489
490 skb_set_network_header(skb, skb->mac_len);
491 skb_set_transport_header(skb, skb->mac_len +
492 sizeof(struct fcoe_hdr));
493
494
495 fcoe_sof_eof = 0;
496 sof = ((struct fcoe_hdr *)skb_network_header(skb))->fcoe_sof;
497 switch (sof) {
498 case FC_SOF_I2:
499 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIS;
500 break;
501 case FC_SOF_I3:
502 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_SOF;
503 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIS;
504 break;
505 case FC_SOF_N2:
506 break;
507 case FC_SOF_N3:
508 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_SOF;
509 break;
510 default:
511 e_warn(drv, "unknown sof = 0x%x\n", sof);
512 return -EINVAL;
513 }
514
515
516 skb_copy_bits(skb, skb->len - 4, &eof, 1);
517
518 switch (eof) {
519 case FC_EOF_N:
520 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N;
521 break;
522 case FC_EOF_T:
523
524 if (skb_is_gso(skb)) {
525 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N;
526 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIE;
527 } else {
528 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_T;
529 }
530 break;
531 case FC_EOF_NI:
532 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_NI;
533 break;
534 case FC_EOF_A:
535 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_A;
536 break;
537 default:
538 e_warn(drv, "unknown eof = 0x%x\n", eof);
539 return -EINVAL;
540 }
541
542
543 fh = (struct fc_frame_header *)skb_transport_header(skb);
544 if (fh->fh_f_ctl[2] & FC_FC_REL_OFF)
545 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_PARINC;
546
547
548 *hdr_len = sizeof(struct fcoe_crc_eof);
549 if (skb_is_gso(skb))
550 *hdr_len += (skb_transport_offset(skb) +
551 sizeof(struct fc_frame_header));
552
553 vlan_macip_lens = (skb_transport_offset(skb) +
554 sizeof(struct fc_frame_header));
555 vlan_macip_lens |= ((skb_transport_offset(skb) - 4)
556 << IXGBE_ADVTXD_MACLEN_SHIFT);
557 vlan_macip_lens |= (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
558
559
560 type_tucmd = IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT |
561 IXGBE_ADVTXT_TUCMD_FCOE;
562 if (skb_is_gso(skb))
563 mss = skb_shinfo(skb)->gso_size;
564
565 mss_l4len_idx = (mss << IXGBE_ADVTXD_MSS_SHIFT) |
566 (1 << IXGBE_ADVTXD_IDX_SHIFT);
567
568
569 i = tx_ring->next_to_use;
570 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
571 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
572 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
573 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
574 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
575
576 tx_buffer_info = &tx_ring->tx_buffer_info[i];
577 tx_buffer_info->time_stamp = jiffies;
578 tx_buffer_info->next_to_watch = i;
579
580 i++;
581 if (i == tx_ring->count)
582 i = 0;
583 tx_ring->next_to_use = i;
584
585 return skb_is_gso(skb);
586}
587
588
589
590
591
592
593
594
595
596void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter)
597{
598 int i, fcoe_q, fcoe_i;
599 struct ixgbe_hw *hw = &adapter->hw;
600 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
601 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
602#ifdef CONFIG_IXGBE_DCB
603 u8 tc;
604 u32 up2tc;
605#endif
606
607
608 if (!fcoe->pool) {
609
610 fcoe->pool = pci_pool_create("ixgbe_fcoe_ddp",
611 adapter->pdev, IXGBE_FCPTR_MAX,
612 IXGBE_FCPTR_ALIGN, PAGE_SIZE);
613 if (!fcoe->pool)
614 e_err(drv, "failed to allocated FCoE DDP pool\n");
615
616 spin_lock_init(&fcoe->lock);
617
618
619 fcoe->extra_ddp_buffer = kmalloc(IXGBE_FCBUFF_MIN, GFP_ATOMIC);
620 if (fcoe->extra_ddp_buffer == NULL) {
621 e_err(drv, "failed to allocated extra DDP buffer\n");
622 goto out_extra_ddp_buffer_alloc;
623 }
624
625 fcoe->extra_ddp_buffer_dma =
626 dma_map_single(&adapter->pdev->dev,
627 fcoe->extra_ddp_buffer,
628 IXGBE_FCBUFF_MIN,
629 DMA_FROM_DEVICE);
630 if (dma_mapping_error(&adapter->pdev->dev,
631 fcoe->extra_ddp_buffer_dma)) {
632 e_err(drv, "failed to map extra DDP buffer\n");
633 goto out_extra_ddp_buffer_dma;
634 }
635 }
636
637
638 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FCOE),
639 (ETH_P_FCOE | IXGBE_ETQF_FCOE | IXGBE_ETQF_FILTER_EN));
640
641 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FIP),
642 (ETH_P_FIP | IXGBE_ETQF_FILTER_EN));
643 if (adapter->ring_feature[RING_F_FCOE].indices) {
644
645 for (i = 0; i < IXGBE_FCRETA_SIZE; i++) {
646 fcoe_i = f->mask + i % f->indices;
647 fcoe_i &= IXGBE_FCRETA_ENTRY_MASK;
648 fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx;
649 IXGBE_WRITE_REG(hw, IXGBE_FCRETA(i), fcoe_q);
650 }
651 IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, IXGBE_FCRECTL_ENA);
652 IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), 0);
653 } else {
654
655 fcoe_i = f->mask;
656 fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx;
657 IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, 0);
658 IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE),
659 IXGBE_ETQS_QUEUE_EN |
660 (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT));
661 }
662
663 fcoe_i = f->mask;
664 fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx;
665 IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FIP),
666 IXGBE_ETQS_QUEUE_EN |
667 (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT));
668
669 IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL,
670 IXGBE_FCRXCTRL_FCOELLI |
671 IXGBE_FCRXCTRL_FCCRCBO |
672 (FC_FCOE_VER << IXGBE_FCRXCTRL_FCOEVER_SHIFT));
673#ifdef CONFIG_IXGBE_DCB
674 up2tc = IXGBE_READ_REG(&adapter->hw, IXGBE_RTTUP2TC);
675 for (i = 0; i < MAX_USER_PRIORITY; i++) {
676 tc = (u8)(up2tc >> (i * IXGBE_RTTUP2TC_UP_SHIFT));
677 tc &= (MAX_TRAFFIC_CLASS - 1);
678 if (fcoe->tc == tc) {
679 fcoe->up = i;
680 break;
681 }
682 }
683#endif
684
685 return;
686
687out_extra_ddp_buffer_dma:
688 kfree(fcoe->extra_ddp_buffer);
689out_extra_ddp_buffer_alloc:
690 pci_pool_destroy(fcoe->pool);
691 fcoe->pool = NULL;
692}
693
694
695
696
697
698
699
700
701
702void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter)
703{
704 int i;
705 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
706
707
708 if (fcoe->pool) {
709 for (i = 0; i < IXGBE_FCOE_DDP_MAX; i++)
710 ixgbe_fcoe_ddp_put(adapter->netdev, i);
711 dma_unmap_single(&adapter->pdev->dev,
712 fcoe->extra_ddp_buffer_dma,
713 IXGBE_FCBUFF_MIN,
714 DMA_FROM_DEVICE);
715 kfree(fcoe->extra_ddp_buffer);
716 pci_pool_destroy(fcoe->pool);
717 fcoe->pool = NULL;
718 }
719}
720
721
722
723
724
725
726
727
728
729int ixgbe_fcoe_enable(struct net_device *netdev)
730{
731 int rc = -EINVAL;
732 struct ixgbe_adapter *adapter = netdev_priv(netdev);
733 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
734
735
736 if (!(adapter->flags & IXGBE_FLAG_FCOE_CAPABLE))
737 goto out_enable;
738
739 atomic_inc(&fcoe->refcnt);
740 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
741 goto out_enable;
742
743 e_info(drv, "Enabling FCoE offload features.\n");
744 if (netif_running(netdev))
745 netdev->netdev_ops->ndo_stop(netdev);
746
747 ixgbe_clear_interrupt_scheme(adapter);
748
749 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
750 adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
751 netdev->features |= NETIF_F_FCOE_CRC;
752 netdev->features |= NETIF_F_FSO;
753 netdev->features |= NETIF_F_FCOE_MTU;
754 netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
755
756 ixgbe_init_interrupt_scheme(adapter);
757 netdev_features_change(netdev);
758
759 if (netif_running(netdev))
760 netdev->netdev_ops->ndo_open(netdev);
761 rc = 0;
762
763out_enable:
764 return rc;
765}
766
767
768
769
770
771
772
773
774
775int ixgbe_fcoe_disable(struct net_device *netdev)
776{
777 int rc = -EINVAL;
778 struct ixgbe_adapter *adapter = netdev_priv(netdev);
779 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
780
781 if (!(adapter->flags & IXGBE_FLAG_FCOE_CAPABLE))
782 goto out_disable;
783
784 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
785 goto out_disable;
786
787 if (!atomic_dec_and_test(&fcoe->refcnt))
788 goto out_disable;
789
790 e_info(drv, "Disabling FCoE offload features.\n");
791 netdev->features &= ~NETIF_F_FCOE_CRC;
792 netdev->features &= ~NETIF_F_FSO;
793 netdev->features &= ~NETIF_F_FCOE_MTU;
794 netdev->fcoe_ddp_xid = 0;
795 netdev_features_change(netdev);
796
797 if (netif_running(netdev))
798 netdev->netdev_ops->ndo_stop(netdev);
799
800 ixgbe_clear_interrupt_scheme(adapter);
801 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
802 adapter->ring_feature[RING_F_FCOE].indices = 0;
803 ixgbe_cleanup_fcoe(adapter);
804 ixgbe_init_interrupt_scheme(adapter);
805
806 if (netif_running(netdev))
807 netdev->netdev_ops->ndo_open(netdev);
808 rc = 0;
809
810out_disable:
811 return rc;
812}
813
814#ifdef CONFIG_IXGBE_DCB
815
816
817
818
819
820
821
822
823
824
825u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up)
826{
827 int i;
828 u32 up2tc;
829
830
831 if (up) {
832
833 up2tc = IXGBE_READ_REG(&adapter->hw, IXGBE_RTTUP2TC);
834 for (i = 0; i < MAX_USER_PRIORITY; i++) {
835 if (up & (1 << i)) {
836 up2tc >>= (i * IXGBE_RTTUP2TC_UP_SHIFT);
837 up2tc &= (MAX_TRAFFIC_CLASS - 1);
838 adapter->fcoe.tc = (u8)up2tc;
839 adapter->fcoe.up = i;
840 return 0;
841 }
842 }
843 }
844
845 return 1;
846}
847#endif
848
849
850
851
852
853
854
855
856
857
858
859
860
861int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type)
862{
863 int rc = -EINVAL;
864 u16 prefix = 0xffff;
865 struct ixgbe_adapter *adapter = netdev_priv(netdev);
866 struct ixgbe_mac_info *mac = &adapter->hw.mac;
867
868 switch (type) {
869 case NETDEV_FCOE_WWNN:
870 prefix = mac->wwnn_prefix;
871 break;
872 case NETDEV_FCOE_WWPN:
873 prefix = mac->wwpn_prefix;
874 break;
875 default:
876 break;
877 }
878
879 if ((prefix != 0xffff) &&
880 is_valid_ether_addr(mac->san_addr)) {
881 *wwn = ((u64) prefix << 48) |
882 ((u64) mac->san_addr[0] << 40) |
883 ((u64) mac->san_addr[1] << 32) |
884 ((u64) mac->san_addr[2] << 24) |
885 ((u64) mac->san_addr[3] << 16) |
886 ((u64) mac->san_addr[4] << 8) |
887 ((u64) mac->san_addr[5]);
888 rc = 0;
889 }
890 return rc;
891}
892