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17#include <linux/io.h>
18#include <linux/slab.h>
19#include <asm/unaligned.h>
20
21#include "hw.h"
22#include "hw-ops.h"
23#include "rc.h"
24#include "ar9003_mac.h"
25
26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
27
28MODULE_AUTHOR("Atheros Communications");
29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31MODULE_LICENSE("Dual BSD/GPL");
32
33static int __init ath9k_init(void)
34{
35 return 0;
36}
37module_init(ath9k_init);
38
39static void __exit ath9k_exit(void)
40{
41 return;
42}
43module_exit(ath9k_exit);
44
45
46
47static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48{
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50}
51
52static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55}
56
57static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59{
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61}
62
63static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64{
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69}
70
71static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72{
73
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78}
79
80
81
82
83
84static void ath9k_hw_set_clockrate(struct ath_hw *ah)
85{
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
89
90 if (!ah->curchan)
91 clockrate = ATH9K_CLOCK_RATE_CCK;
92 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
96 else
97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
98
99 if (conf_is_ht40(conf))
100 clockrate *= 2;
101
102 common->clockrate = clockrate;
103}
104
105static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
106{
107 struct ath_common *common = ath9k_hw_common(ah);
108
109 return usecs * common->clockrate;
110}
111
112bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
113{
114 int i;
115
116 BUG_ON(timeout < AH_TIME_QUANTUM);
117
118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
119 if ((REG_READ(ah, reg) & mask) == val)
120 return true;
121
122 udelay(AH_TIME_QUANTUM);
123 }
124
125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 timeout, reg, REG_READ(ah, reg), mask, val);
128
129 return false;
130}
131EXPORT_SYMBOL(ath9k_hw_wait);
132
133u32 ath9k_hw_reverse_bits(u32 val, u32 n)
134{
135 u32 retval;
136 int i;
137
138 for (i = 0, retval = 0; i < n; i++) {
139 retval = (retval << 1) | (val & 1);
140 val >>= 1;
141 }
142 return retval;
143}
144
145bool ath9k_get_channel_edges(struct ath_hw *ah,
146 u16 flags, u16 *low,
147 u16 *high)
148{
149 struct ath9k_hw_capabilities *pCap = &ah->caps;
150
151 if (flags & CHANNEL_5GHZ) {
152 *low = pCap->low_5ghz_chan;
153 *high = pCap->high_5ghz_chan;
154 return true;
155 }
156 if ((flags & CHANNEL_2GHZ)) {
157 *low = pCap->low_2ghz_chan;
158 *high = pCap->high_2ghz_chan;
159 return true;
160 }
161 return false;
162}
163
164u16 ath9k_hw_computetxtime(struct ath_hw *ah,
165 u8 phy, int kbps,
166 u32 frameLen, u16 rateix,
167 bool shortPreamble)
168{
169 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
170
171 if (kbps == 0)
172 return 0;
173
174 switch (phy) {
175 case WLAN_RC_PHY_CCK:
176 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
177 if (shortPreamble)
178 phyTime >>= 1;
179 numBits = frameLen << 3;
180 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
181 break;
182 case WLAN_RC_PHY_OFDM:
183 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
184 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
185 numBits = OFDM_PLCP_BITS + (frameLen << 3);
186 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
187 txTime = OFDM_SIFS_TIME_QUARTER
188 + OFDM_PREAMBLE_TIME_QUARTER
189 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
190 } else if (ah->curchan &&
191 IS_CHAN_HALF_RATE(ah->curchan)) {
192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
193 numBits = OFDM_PLCP_BITS + (frameLen << 3);
194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
195 txTime = OFDM_SIFS_TIME_HALF +
196 OFDM_PREAMBLE_TIME_HALF
197 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
198 } else {
199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
200 numBits = OFDM_PLCP_BITS + (frameLen << 3);
201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
202 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
203 + (numSymbols * OFDM_SYMBOL_TIME);
204 }
205 break;
206 default:
207 ath_err(ath9k_hw_common(ah),
208 "Unknown phy %u (rate ix %u)\n", phy, rateix);
209 txTime = 0;
210 break;
211 }
212
213 return txTime;
214}
215EXPORT_SYMBOL(ath9k_hw_computetxtime);
216
217void ath9k_hw_get_channel_centers(struct ath_hw *ah,
218 struct ath9k_channel *chan,
219 struct chan_centers *centers)
220{
221 int8_t extoff;
222
223 if (!IS_CHAN_HT40(chan)) {
224 centers->ctl_center = centers->ext_center =
225 centers->synth_center = chan->channel;
226 return;
227 }
228
229 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
230 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
231 centers->synth_center =
232 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
233 extoff = 1;
234 } else {
235 centers->synth_center =
236 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
237 extoff = -1;
238 }
239
240 centers->ctl_center =
241 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
242
243 centers->ext_center =
244 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
245}
246
247
248
249
250
251static void ath9k_hw_read_revisions(struct ath_hw *ah)
252{
253 u32 val;
254
255 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
256
257 if (val == 0xFF) {
258 val = REG_READ(ah, AR_SREV);
259 ah->hw_version.macVersion =
260 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
261 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
262 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
263 } else {
264 if (!AR_SREV_9100(ah))
265 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
266
267 ah->hw_version.macRev = val & AR_SREV_REVISION;
268
269 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
270 ah->is_pciexpress = true;
271 }
272}
273
274
275
276
277
278static void ath9k_hw_disablepcie(struct ath_hw *ah)
279{
280 if (!AR_SREV_5416(ah))
281 return;
282
283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
292
293 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
294}
295
296
297static bool ath9k_hw_chip_test(struct ath_hw *ah)
298{
299 struct ath_common *common = ath9k_hw_common(ah);
300 u32 regAddr[2] = { AR_STA_ID0 };
301 u32 regHold[2];
302 static const u32 patternData[4] = {
303 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
304 };
305 int i, j, loop_max;
306
307 if (!AR_SREV_9300_20_OR_LATER(ah)) {
308 loop_max = 2;
309 regAddr[1] = AR_PHY_BASE + (8 << 2);
310 } else
311 loop_max = 1;
312
313 for (i = 0; i < loop_max; i++) {
314 u32 addr = regAddr[i];
315 u32 wrData, rdData;
316
317 regHold[i] = REG_READ(ah, addr);
318 for (j = 0; j < 0x100; j++) {
319 wrData = (j << 16) | j;
320 REG_WRITE(ah, addr, wrData);
321 rdData = REG_READ(ah, addr);
322 if (rdData != wrData) {
323 ath_err(common,
324 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
325 addr, wrData, rdData);
326 return false;
327 }
328 }
329 for (j = 0; j < 4; j++) {
330 wrData = patternData[j];
331 REG_WRITE(ah, addr, wrData);
332 rdData = REG_READ(ah, addr);
333 if (wrData != rdData) {
334 ath_err(common,
335 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
336 addr, wrData, rdData);
337 return false;
338 }
339 }
340 REG_WRITE(ah, regAddr[i], regHold[i]);
341 }
342 udelay(100);
343
344 return true;
345}
346
347static void ath9k_hw_init_config(struct ath_hw *ah)
348{
349 int i;
350
351 ah->config.dma_beacon_response_time = 2;
352 ah->config.sw_beacon_response_time = 10;
353 ah->config.additional_swba_backoff = 0;
354 ah->config.ack_6mb = 0x0;
355 ah->config.cwm_ignore_extcca = 0;
356 ah->config.pcie_powersave_enable = 0;
357 ah->config.pcie_clock_req = 0;
358 ah->config.pcie_waen = 0;
359 ah->config.analog_shiftreg = 1;
360 ah->config.enable_ani = true;
361
362 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
363 ah->config.spurchans[i][0] = AR_NO_SPUR;
364 ah->config.spurchans[i][1] = AR_NO_SPUR;
365 }
366
367 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
368 ah->config.ht_enable = 1;
369 else
370 ah->config.ht_enable = 0;
371
372
373 ah->config.paprd_disable = 1;
374
375 ah->config.rx_intr_mitigation = true;
376 ah->config.pcieSerDesWrite = true;
377
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389
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391
392
393
394 if (num_possible_cpus() > 1)
395 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
396}
397
398static void ath9k_hw_init_defaults(struct ath_hw *ah)
399{
400 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
401
402 regulatory->country_code = CTRY_DEFAULT;
403 regulatory->power_limit = MAX_RATE_POWER;
404 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
405
406 ah->hw_version.magic = AR5416_MAGIC;
407 ah->hw_version.subvendorid = 0;
408
409 ah->atim_window = 0;
410 ah->sta_id1_defaults =
411 AR_STA_ID1_CRPT_MIC_ENABLE |
412 AR_STA_ID1_MCAST_KSRCH;
413 ah->enable_32kHz_clock = DONT_USE_32KHZ;
414 ah->slottime = 20;
415 ah->globaltxtimeout = (u32) -1;
416 ah->power_mode = ATH9K_PM_UNDEFINED;
417}
418
419static int ath9k_hw_init_macaddr(struct ath_hw *ah)
420{
421 struct ath_common *common = ath9k_hw_common(ah);
422 u32 sum;
423 int i;
424 u16 eeval;
425 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
426
427 sum = 0;
428 for (i = 0; i < 3; i++) {
429 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
430 sum += eeval;
431 common->macaddr[2 * i] = eeval >> 8;
432 common->macaddr[2 * i + 1] = eeval & 0xff;
433 }
434 if (sum == 0 || sum == 0xffff * 3)
435 return -EADDRNOTAVAIL;
436
437 return 0;
438}
439
440static int ath9k_hw_post_init(struct ath_hw *ah)
441{
442 struct ath_common *common = ath9k_hw_common(ah);
443 int ecode;
444
445 if (common->bus_ops->ath_bus_type != ATH_USB) {
446 if (!ath9k_hw_chip_test(ah))
447 return -ENODEV;
448 }
449
450 if (!AR_SREV_9300_20_OR_LATER(ah)) {
451 ecode = ar9002_hw_rf_claim(ah);
452 if (ecode != 0)
453 return ecode;
454 }
455
456 ecode = ath9k_hw_eeprom_init(ah);
457 if (ecode != 0)
458 return ecode;
459
460 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
461 "Eeprom VER: %d, REV: %d\n",
462 ah->eep_ops->get_eeprom_ver(ah),
463 ah->eep_ops->get_eeprom_rev(ah));
464
465 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
466 if (ecode) {
467 ath_err(ath9k_hw_common(ah),
468 "Failed allocating banks for external radio\n");
469 ath9k_hw_rf_free_ext_banks(ah);
470 return ecode;
471 }
472
473 if (!AR_SREV_9100(ah)) {
474 ath9k_hw_ani_setup(ah);
475 ath9k_hw_ani_init(ah);
476 }
477
478 return 0;
479}
480
481static void ath9k_hw_attach_ops(struct ath_hw *ah)
482{
483 if (AR_SREV_9300_20_OR_LATER(ah))
484 ar9003_hw_attach_ops(ah);
485 else
486 ar9002_hw_attach_ops(ah);
487}
488
489
490static int __ath9k_hw_init(struct ath_hw *ah)
491{
492 struct ath_common *common = ath9k_hw_common(ah);
493 int r = 0;
494
495 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
496 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
497
498 ath9k_hw_read_revisions(ah);
499
500
501
502
503
504
505 ah->WARegVal = REG_READ(ah, AR_WA);
506 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
507 AR_WA_ASPM_TIMER_BASED_DISABLE);
508
509 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
510 ath_err(common, "Couldn't reset chip\n");
511 return -EIO;
512 }
513
514 ath9k_hw_init_defaults(ah);
515 ath9k_hw_init_config(ah);
516
517 ath9k_hw_attach_ops(ah);
518
519 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
520 ath_err(common, "Couldn't wakeup chip\n");
521 return -EIO;
522 }
523
524 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
525 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
526 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
527 !ah->is_pciexpress)) {
528 ah->config.serialize_regmode =
529 SER_REG_MODE_ON;
530 } else {
531 ah->config.serialize_regmode =
532 SER_REG_MODE_OFF;
533 }
534 }
535
536 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
537 ah->config.serialize_regmode);
538
539 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
540 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
541 else
542 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
543
544 switch (ah->hw_version.macVersion) {
545 case AR_SREV_VERSION_5416_PCI:
546 case AR_SREV_VERSION_5416_PCIE:
547 case AR_SREV_VERSION_9160:
548 case AR_SREV_VERSION_9100:
549 case AR_SREV_VERSION_9280:
550 case AR_SREV_VERSION_9285:
551 case AR_SREV_VERSION_9287:
552 case AR_SREV_VERSION_9271:
553 case AR_SREV_VERSION_9300:
554 case AR_SREV_VERSION_9485:
555 break;
556 default:
557 ath_err(common,
558 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
559 ah->hw_version.macVersion, ah->hw_version.macRev);
560 return -EOPNOTSUPP;
561 }
562
563 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
564 ah->is_pciexpress = false;
565
566 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
567 ath9k_hw_init_cal_settings(ah);
568
569 ah->ani_function = ATH9K_ANI_ALL;
570 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
571 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
572 if (!AR_SREV_9300_20_OR_LATER(ah))
573 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
574
575 ath9k_hw_init_mode_regs(ah);
576
577
578 if (ah->is_pciexpress)
579 ath9k_hw_configpcipowersave(ah, 0, 0);
580 else
581 ath9k_hw_disablepcie(ah);
582
583 if (!AR_SREV_9300_20_OR_LATER(ah))
584 ar9002_hw_cck_chan14_spread(ah);
585
586 r = ath9k_hw_post_init(ah);
587 if (r)
588 return r;
589
590 ath9k_hw_init_mode_gain_regs(ah);
591 r = ath9k_hw_fill_cap_info(ah);
592 if (r)
593 return r;
594
595 r = ath9k_hw_init_macaddr(ah);
596 if (r) {
597 ath_err(common, "Failed to initialize MAC address\n");
598 return r;
599 }
600
601 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
602 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
603 else
604 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
605
606 ah->bb_watchdog_timeout_ms = 25;
607
608 common->state = ATH_HW_INITIALIZED;
609
610 return 0;
611}
612
613int ath9k_hw_init(struct ath_hw *ah)
614{
615 int ret;
616 struct ath_common *common = ath9k_hw_common(ah);
617
618
619 switch (ah->hw_version.devid) {
620 case AR5416_DEVID_PCI:
621 case AR5416_DEVID_PCIE:
622 case AR5416_AR9100_DEVID:
623 case AR9160_DEVID_PCI:
624 case AR9280_DEVID_PCI:
625 case AR9280_DEVID_PCIE:
626 case AR9285_DEVID_PCIE:
627 case AR9287_DEVID_PCI:
628 case AR9287_DEVID_PCIE:
629 case AR2427_DEVID_PCIE:
630 case AR9300_DEVID_PCIE:
631 case AR9300_DEVID_AR9485_PCIE:
632 break;
633 default:
634 if (common->bus_ops->ath_bus_type == ATH_USB)
635 break;
636 ath_err(common, "Hardware device ID 0x%04x not supported\n",
637 ah->hw_version.devid);
638 return -EOPNOTSUPP;
639 }
640
641 ret = __ath9k_hw_init(ah);
642 if (ret) {
643 ath_err(common,
644 "Unable to initialize hardware; initialization status: %d\n",
645 ret);
646 return ret;
647 }
648
649 return 0;
650}
651EXPORT_SYMBOL(ath9k_hw_init);
652
653static void ath9k_hw_init_qos(struct ath_hw *ah)
654{
655 ENABLE_REGWRITE_BUFFER(ah);
656
657 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
658 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
659
660 REG_WRITE(ah, AR_QOS_NO_ACK,
661 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
662 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
663 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
664
665 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
666 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
667 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
668 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
670
671 REGWRITE_BUFFER_FLUSH(ah);
672}
673
674unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
675{
676 REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK)));
677 udelay(100);
678 REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK));
679
680 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
681 udelay(100);
682
683 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
684}
685EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
686
687#define DPLL2_KD_VAL 0x3D
688#define DPLL2_KI_VAL 0x06
689#define DPLL3_PHASE_SHIFT_VAL 0x1
690
691static void ath9k_hw_init_pll(struct ath_hw *ah,
692 struct ath9k_channel *chan)
693{
694 u32 pll;
695
696 if (AR_SREV_9485(ah)) {
697 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
698 REG_WRITE(ah, AR_CH0_DDR_DPLL2, 0x19e82f01);
699
700 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
701 AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
702
703 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
704 udelay(1000);
705
706 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
707
708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
709 AR_CH0_DPLL2_KD, DPLL2_KD_VAL);
710 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
711 AR_CH0_DPLL2_KI, DPLL2_KI_VAL);
712
713 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
714 AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
715 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);
716 udelay(1000);
717 }
718
719 pll = ath9k_hw_compute_pll_control(ah, chan);
720
721 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
722
723
724 if (AR_SREV_9271(ah)) {
725 udelay(500);
726 REG_WRITE(ah, 0x50040, 0x304);
727 }
728
729 udelay(RTC_PLL_SETTLE_DELAY);
730
731 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
732}
733
734static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
735 enum nl80211_iftype opmode)
736{
737 u32 imr_reg = AR_IMR_TXERR |
738 AR_IMR_TXURN |
739 AR_IMR_RXERR |
740 AR_IMR_RXORN |
741 AR_IMR_BCNMISC;
742
743 if (AR_SREV_9300_20_OR_LATER(ah)) {
744 imr_reg |= AR_IMR_RXOK_HP;
745 if (ah->config.rx_intr_mitigation)
746 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
747 else
748 imr_reg |= AR_IMR_RXOK_LP;
749
750 } else {
751 if (ah->config.rx_intr_mitigation)
752 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
753 else
754 imr_reg |= AR_IMR_RXOK;
755 }
756
757 if (ah->config.tx_intr_mitigation)
758 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
759 else
760 imr_reg |= AR_IMR_TXOK;
761
762 if (opmode == NL80211_IFTYPE_AP)
763 imr_reg |= AR_IMR_MIB;
764
765 ENABLE_REGWRITE_BUFFER(ah);
766
767 REG_WRITE(ah, AR_IMR, imr_reg);
768 ah->imrs2_reg |= AR_IMR_S2_GTT;
769 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
770
771 if (!AR_SREV_9100(ah)) {
772 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
773 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
774 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
775 }
776
777 REGWRITE_BUFFER_FLUSH(ah);
778
779 if (AR_SREV_9300_20_OR_LATER(ah)) {
780 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
781 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
782 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
783 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
784 }
785}
786
787static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
788{
789 u32 val = ath9k_hw_mac_to_clks(ah, us);
790 val = min(val, (u32) 0xFFFF);
791 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
792}
793
794static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
795{
796 u32 val = ath9k_hw_mac_to_clks(ah, us);
797 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
798 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
799}
800
801static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
802{
803 u32 val = ath9k_hw_mac_to_clks(ah, us);
804 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
805 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
806}
807
808static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
809{
810 if (tu > 0xFFFF) {
811 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
812 "bad global tx timeout %u\n", tu);
813 ah->globaltxtimeout = (u32) -1;
814 return false;
815 } else {
816 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
817 ah->globaltxtimeout = tu;
818 return true;
819 }
820}
821
822void ath9k_hw_init_global_settings(struct ath_hw *ah)
823{
824 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
825 int acktimeout;
826 int slottime;
827 int sifstime;
828
829 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
830 ah->misc_mode);
831
832 if (ah->misc_mode != 0)
833 REG_WRITE(ah, AR_PCU_MISC,
834 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
835
836 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
837 sifstime = 16;
838 else
839 sifstime = 10;
840
841
842 slottime = ah->slottime + 3 * ah->coverage_class;
843 acktimeout = slottime + sifstime;
844
845
846
847
848
849
850
851
852 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
853 acktimeout += 64 - sifstime - ah->slottime;
854
855 ath9k_hw_setslottime(ah, ah->slottime);
856 ath9k_hw_set_ack_timeout(ah, acktimeout);
857 ath9k_hw_set_cts_timeout(ah, acktimeout);
858 if (ah->globaltxtimeout != (u32) -1)
859 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
860}
861EXPORT_SYMBOL(ath9k_hw_init_global_settings);
862
863void ath9k_hw_deinit(struct ath_hw *ah)
864{
865 struct ath_common *common = ath9k_hw_common(ah);
866
867 if (common->state < ATH_HW_INITIALIZED)
868 goto free_hw;
869
870 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
871
872free_hw:
873 ath9k_hw_rf_free_ext_banks(ah);
874}
875EXPORT_SYMBOL(ath9k_hw_deinit);
876
877
878
879
880
881u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
882{
883 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
884
885 if (IS_CHAN_B(chan))
886 ctl |= CTL_11B;
887 else if (IS_CHAN_G(chan))
888 ctl |= CTL_11G;
889 else
890 ctl |= CTL_11A;
891
892 return ctl;
893}
894
895
896
897
898
899static inline void ath9k_hw_set_dma(struct ath_hw *ah)
900{
901 struct ath_common *common = ath9k_hw_common(ah);
902 u32 regval;
903
904 ENABLE_REGWRITE_BUFFER(ah);
905
906
907
908
909 if (!AR_SREV_9300_20_OR_LATER(ah)) {
910 regval = REG_READ(ah, AR_AHB_MODE);
911 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
912 }
913
914
915
916
917 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
918 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
919
920 REGWRITE_BUFFER_FLUSH(ah);
921
922
923
924
925
926
927 if (!AR_SREV_9300_20_OR_LATER(ah))
928 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
929
930 ENABLE_REGWRITE_BUFFER(ah);
931
932
933
934
935 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
936 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
937
938
939
940
941 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
942
943 if (AR_SREV_9300_20_OR_LATER(ah)) {
944 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
945 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
946
947 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
948 ah->caps.rx_status_len);
949 }
950
951
952
953
954
955 if (AR_SREV_9285(ah)) {
956
957
958
959
960 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
961 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
962 } else if (!AR_SREV_9271(ah)) {
963 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
964 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
965 }
966
967 REGWRITE_BUFFER_FLUSH(ah);
968
969 if (AR_SREV_9300_20_OR_LATER(ah))
970 ath9k_hw_reset_txstatus_ring(ah);
971}
972
973static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
974{
975 u32 val;
976
977 val = REG_READ(ah, AR_STA_ID1);
978 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
979 switch (opmode) {
980 case NL80211_IFTYPE_AP:
981 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
982 | AR_STA_ID1_KSRCH_MODE);
983 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
984 break;
985 case NL80211_IFTYPE_ADHOC:
986 case NL80211_IFTYPE_MESH_POINT:
987 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
988 | AR_STA_ID1_KSRCH_MODE);
989 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
990 break;
991 case NL80211_IFTYPE_STATION:
992 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
993 break;
994 default:
995 if (ah->is_monitoring)
996 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
997 break;
998 }
999}
1000
1001void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1002 u32 *coef_mantissa, u32 *coef_exponent)
1003{
1004 u32 coef_exp, coef_man;
1005
1006 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1007 if ((coef_scaled >> coef_exp) & 0x1)
1008 break;
1009
1010 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1011
1012 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1013
1014 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1015 *coef_exponent = coef_exp - 16;
1016}
1017
1018static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1019{
1020 u32 rst_flags;
1021 u32 tmpReg;
1022
1023 if (AR_SREV_9100(ah)) {
1024 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1025 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1026 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1027 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1028 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1029 }
1030
1031 ENABLE_REGWRITE_BUFFER(ah);
1032
1033 if (AR_SREV_9300_20_OR_LATER(ah)) {
1034 REG_WRITE(ah, AR_WA, ah->WARegVal);
1035 udelay(10);
1036 }
1037
1038 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1039 AR_RTC_FORCE_WAKE_ON_INT);
1040
1041 if (AR_SREV_9100(ah)) {
1042 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1043 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1044 } else {
1045 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1046 if (tmpReg &
1047 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1048 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1049 u32 val;
1050 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1051
1052 val = AR_RC_HOSTIF;
1053 if (!AR_SREV_9300_20_OR_LATER(ah))
1054 val |= AR_RC_AHB;
1055 REG_WRITE(ah, AR_RC, val);
1056
1057 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1058 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1059
1060 rst_flags = AR_RTC_RC_MAC_WARM;
1061 if (type == ATH9K_RESET_COLD)
1062 rst_flags |= AR_RTC_RC_MAC_COLD;
1063 }
1064
1065 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1066
1067 REGWRITE_BUFFER_FLUSH(ah);
1068
1069 udelay(50);
1070
1071 REG_WRITE(ah, AR_RTC_RC, 0);
1072 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1073 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1074 "RTC stuck in MAC reset\n");
1075 return false;
1076 }
1077
1078 if (!AR_SREV_9100(ah))
1079 REG_WRITE(ah, AR_RC, 0);
1080
1081 if (AR_SREV_9100(ah))
1082 udelay(50);
1083
1084 return true;
1085}
1086
1087static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1088{
1089 ENABLE_REGWRITE_BUFFER(ah);
1090
1091 if (AR_SREV_9300_20_OR_LATER(ah)) {
1092 REG_WRITE(ah, AR_WA, ah->WARegVal);
1093 udelay(10);
1094 }
1095
1096 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1097 AR_RTC_FORCE_WAKE_ON_INT);
1098
1099 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1100 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1101
1102 REG_WRITE(ah, AR_RTC_RESET, 0);
1103
1104 REGWRITE_BUFFER_FLUSH(ah);
1105
1106 if (!AR_SREV_9300_20_OR_LATER(ah))
1107 udelay(2);
1108
1109 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1110 REG_WRITE(ah, AR_RC, 0);
1111
1112 REG_WRITE(ah, AR_RTC_RESET, 1);
1113
1114 if (!ath9k_hw_wait(ah,
1115 AR_RTC_STATUS,
1116 AR_RTC_STATUS_M,
1117 AR_RTC_STATUS_ON,
1118 AH_WAIT_TIMEOUT)) {
1119 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1120 "RTC not waking up\n");
1121 return false;
1122 }
1123
1124 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1125}
1126
1127static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1128{
1129 if (AR_SREV_9300_20_OR_LATER(ah)) {
1130 REG_WRITE(ah, AR_WA, ah->WARegVal);
1131 udelay(10);
1132 }
1133
1134 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1135 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1136
1137 switch (type) {
1138 case ATH9K_RESET_POWER_ON:
1139 return ath9k_hw_set_reset_power_on(ah);
1140 case ATH9K_RESET_WARM:
1141 case ATH9K_RESET_COLD:
1142 return ath9k_hw_set_reset(ah, type);
1143 default:
1144 return false;
1145 }
1146}
1147
1148static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1149 struct ath9k_channel *chan)
1150{
1151 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1152 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1153 return false;
1154 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1155 return false;
1156
1157 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1158 return false;
1159
1160 ah->chip_fullsleep = false;
1161 ath9k_hw_init_pll(ah, chan);
1162 ath9k_hw_set_rfmode(ah, chan);
1163
1164 return true;
1165}
1166
1167static bool ath9k_hw_channel_change(struct ath_hw *ah,
1168 struct ath9k_channel *chan)
1169{
1170 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1171 struct ath_common *common = ath9k_hw_common(ah);
1172 struct ieee80211_channel *channel = chan->chan;
1173 u32 qnum;
1174 int r;
1175
1176 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1177 if (ath9k_hw_numtxpending(ah, qnum)) {
1178 ath_dbg(common, ATH_DBG_QUEUE,
1179 "Transmit frames pending on queue %d\n", qnum);
1180 return false;
1181 }
1182 }
1183
1184 if (!ath9k_hw_rfbus_req(ah)) {
1185 ath_err(common, "Could not kill baseband RX\n");
1186 return false;
1187 }
1188
1189 ath9k_hw_set_channel_regs(ah, chan);
1190
1191 r = ath9k_hw_rf_set_freq(ah, chan);
1192 if (r) {
1193 ath_err(common, "Failed to set channel\n");
1194 return false;
1195 }
1196 ath9k_hw_set_clockrate(ah);
1197
1198 ah->eep_ops->set_txpower(ah, chan,
1199 ath9k_regd_get_ctl(regulatory, chan),
1200 channel->max_antenna_gain * 2,
1201 channel->max_power * 2,
1202 min((u32) MAX_RATE_POWER,
1203 (u32) regulatory->power_limit), false);
1204
1205 ath9k_hw_rfbus_done(ah);
1206
1207 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1208 ath9k_hw_set_delta_slope(ah, chan);
1209
1210 ath9k_hw_spur_mitigate_freq(ah, chan);
1211
1212 return true;
1213}
1214
1215bool ath9k_hw_check_alive(struct ath_hw *ah)
1216{
1217 int count = 50;
1218 u32 reg;
1219
1220 if (AR_SREV_9285_12_OR_LATER(ah))
1221 return true;
1222
1223 do {
1224 reg = REG_READ(ah, AR_OBS_BUS_1);
1225
1226 if ((reg & 0x7E7FFFEF) == 0x00702400)
1227 continue;
1228
1229 switch (reg & 0x7E000B00) {
1230 case 0x1E000000:
1231 case 0x52000B00:
1232 case 0x18000B00:
1233 continue;
1234 default:
1235 return true;
1236 }
1237 } while (count-- > 0);
1238
1239 return false;
1240}
1241EXPORT_SYMBOL(ath9k_hw_check_alive);
1242
1243int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1244 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1245{
1246 struct ath_common *common = ath9k_hw_common(ah);
1247 u32 saveLedState;
1248 struct ath9k_channel *curchan = ah->curchan;
1249 u32 saveDefAntenna;
1250 u32 macStaId1;
1251 u64 tsf = 0;
1252 int i, r;
1253
1254 ah->txchainmask = common->tx_chainmask;
1255 ah->rxchainmask = common->rx_chainmask;
1256
1257 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1258 return -EIO;
1259
1260 if (curchan && !ah->chip_fullsleep)
1261 ath9k_hw_getnf(ah, curchan);
1262
1263 ah->caldata = caldata;
1264 if (caldata &&
1265 (chan->channel != caldata->channel ||
1266 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1267 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1268
1269 memset(caldata, 0, sizeof(*caldata));
1270 ath9k_init_nfcal_hist_buffer(ah, chan);
1271 }
1272
1273 if (bChannelChange &&
1274 (ah->chip_fullsleep != true) &&
1275 (ah->curchan != NULL) &&
1276 (chan->channel != ah->curchan->channel) &&
1277 ((chan->channelFlags & CHANNEL_ALL) ==
1278 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1279 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1280
1281 if (ath9k_hw_channel_change(ah, chan)) {
1282 ath9k_hw_loadnf(ah, ah->curchan);
1283 ath9k_hw_start_nfcal(ah, true);
1284 if (AR_SREV_9271(ah))
1285 ar9002_hw_load_ani_reg(ah, chan);
1286 return 0;
1287 }
1288 }
1289
1290 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1291 if (saveDefAntenna == 0)
1292 saveDefAntenna = 1;
1293
1294 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1295
1296
1297 if (AR_SREV_9100(ah) ||
1298 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1299 tsf = ath9k_hw_gettsf64(ah);
1300
1301 saveLedState = REG_READ(ah, AR_CFG_LED) &
1302 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1303 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1304
1305 ath9k_hw_mark_phy_inactive(ah);
1306
1307 ah->paprd_table_write_done = false;
1308
1309
1310 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1311 REG_WRITE(ah,
1312 AR9271_RESET_POWER_DOWN_CONTROL,
1313 AR9271_RADIO_RF_RST);
1314 udelay(50);
1315 }
1316
1317 if (!ath9k_hw_chip_reset(ah, chan)) {
1318 ath_err(common, "Chip reset failed\n");
1319 return -EINVAL;
1320 }
1321
1322
1323 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1324 ah->htc_reset_init = false;
1325 REG_WRITE(ah,
1326 AR9271_RESET_POWER_DOWN_CONTROL,
1327 AR9271_GATE_MAC_CTL);
1328 udelay(50);
1329 }
1330
1331
1332 if (tsf)
1333 ath9k_hw_settsf64(ah, tsf);
1334
1335 if (AR_SREV_9280_20_OR_LATER(ah))
1336 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1337
1338 if (!AR_SREV_9300_20_OR_LATER(ah))
1339 ar9002_hw_enable_async_fifo(ah);
1340
1341 r = ath9k_hw_process_ini(ah, chan);
1342 if (r)
1343 return r;
1344
1345
1346
1347
1348
1349
1350
1351 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1352 tsf += 1500;
1353 ath9k_hw_settsf64(ah, tsf);
1354 }
1355
1356
1357 if (AR_SREV_9280_20_OR_LATER(ah)) {
1358
1359
1360 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1361 0xc7ff);
1362 ah->sw_mgmt_crypto = false;
1363 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1364
1365 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1366 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1367 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1368 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1369 ah->sw_mgmt_crypto = true;
1370 } else
1371 ah->sw_mgmt_crypto = true;
1372
1373 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1374 ath9k_hw_set_delta_slope(ah, chan);
1375
1376 ath9k_hw_spur_mitigate_freq(ah, chan);
1377 ah->eep_ops->set_board_values(ah, chan);
1378
1379 ENABLE_REGWRITE_BUFFER(ah);
1380
1381 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1382 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1383 | macStaId1
1384 | AR_STA_ID1_RTS_USE_DEF
1385 | (ah->config.
1386 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1387 | ah->sta_id1_defaults);
1388 ath_hw_setbssidmask(common);
1389 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1390 ath9k_hw_write_associd(ah);
1391 REG_WRITE(ah, AR_ISR, ~0);
1392 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1393
1394 REGWRITE_BUFFER_FLUSH(ah);
1395
1396 ath9k_hw_set_operating_mode(ah, ah->opmode);
1397
1398 r = ath9k_hw_rf_set_freq(ah, chan);
1399 if (r)
1400 return r;
1401
1402 ath9k_hw_set_clockrate(ah);
1403
1404 ENABLE_REGWRITE_BUFFER(ah);
1405
1406 for (i = 0; i < AR_NUM_DCU; i++)
1407 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1408
1409 REGWRITE_BUFFER_FLUSH(ah);
1410
1411 ah->intr_txqs = 0;
1412 for (i = 0; i < ah->caps.total_queues; i++)
1413 ath9k_hw_resettxqueue(ah, i);
1414
1415 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1416 ath9k_hw_ani_cache_ini_regs(ah);
1417 ath9k_hw_init_qos(ah);
1418
1419 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1420 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1421
1422 ath9k_hw_init_global_settings(ah);
1423
1424 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1425 ar9002_hw_update_async_fifo(ah);
1426 ar9002_hw_enable_wep_aggregation(ah);
1427 }
1428
1429 REG_WRITE(ah, AR_STA_ID1,
1430 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1431
1432 ath9k_hw_set_dma(ah);
1433
1434 REG_WRITE(ah, AR_OBS, 8);
1435
1436 if (ah->config.rx_intr_mitigation) {
1437 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1438 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1439 }
1440
1441 if (ah->config.tx_intr_mitigation) {
1442 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1443 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1444 }
1445
1446 ath9k_hw_init_bb(ah, chan);
1447
1448 if (!ath9k_hw_init_cal(ah, chan))
1449 return -EIO;
1450
1451 ENABLE_REGWRITE_BUFFER(ah);
1452
1453 ath9k_hw_restore_chainmask(ah);
1454 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1455
1456 REGWRITE_BUFFER_FLUSH(ah);
1457
1458
1459
1460
1461 if (AR_SREV_9100(ah)) {
1462 u32 mask;
1463 mask = REG_READ(ah, AR_CFG);
1464 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1465 ath_dbg(common, ATH_DBG_RESET,
1466 "CFG Byte Swap Set 0x%x\n", mask);
1467 } else {
1468 mask =
1469 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1470 REG_WRITE(ah, AR_CFG, mask);
1471 ath_dbg(common, ATH_DBG_RESET,
1472 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1473 }
1474 } else {
1475 if (common->bus_ops->ath_bus_type == ATH_USB) {
1476
1477 if (AR_SREV_9271(ah))
1478 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1479 else
1480 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1481 }
1482#ifdef __BIG_ENDIAN
1483 else
1484 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1485#endif
1486 }
1487
1488 if (ah->btcoex_hw.enabled)
1489 ath9k_hw_btcoex_enable(ah);
1490
1491 if (AR_SREV_9300_20_OR_LATER(ah))
1492 ar9003_hw_bb_watchdog_config(ah);
1493
1494 return 0;
1495}
1496EXPORT_SYMBOL(ath9k_hw_reset);
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1507{
1508 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1509 if (setChip) {
1510
1511
1512
1513
1514 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1515 AR_RTC_FORCE_WAKE_EN);
1516 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1517 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1518
1519
1520 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1521 REG_CLR_BIT(ah, (AR_RTC_RESET),
1522 AR_RTC_RESET_EN);
1523 }
1524
1525
1526 if (AR_SREV_9300_20_OR_LATER(ah))
1527 REG_WRITE(ah, AR_WA,
1528 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1529}
1530
1531
1532
1533
1534
1535
1536static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1537{
1538 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1539 if (setChip) {
1540 struct ath9k_hw_capabilities *pCap = &ah->caps;
1541
1542 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1543
1544 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1545 AR_RTC_FORCE_WAKE_ON_INT);
1546 } else {
1547
1548
1549
1550
1551 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1552 AR_RTC_FORCE_WAKE_EN);
1553 }
1554 }
1555
1556
1557 if (AR_SREV_9300_20_OR_LATER(ah))
1558 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1559}
1560
1561static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1562{
1563 u32 val;
1564 int i;
1565
1566
1567 if (AR_SREV_9300_20_OR_LATER(ah)) {
1568 REG_WRITE(ah, AR_WA, ah->WARegVal);
1569 udelay(10);
1570 }
1571
1572 if (setChip) {
1573 if ((REG_READ(ah, AR_RTC_STATUS) &
1574 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1575 if (ath9k_hw_set_reset_reg(ah,
1576 ATH9K_RESET_POWER_ON) != true) {
1577 return false;
1578 }
1579 if (!AR_SREV_9300_20_OR_LATER(ah))
1580 ath9k_hw_init_pll(ah, NULL);
1581 }
1582 if (AR_SREV_9100(ah))
1583 REG_SET_BIT(ah, AR_RTC_RESET,
1584 AR_RTC_RESET_EN);
1585
1586 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1587 AR_RTC_FORCE_WAKE_EN);
1588 udelay(50);
1589
1590 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1591 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1592 if (val == AR_RTC_STATUS_ON)
1593 break;
1594 udelay(50);
1595 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1596 AR_RTC_FORCE_WAKE_EN);
1597 }
1598 if (i == 0) {
1599 ath_err(ath9k_hw_common(ah),
1600 "Failed to wakeup in %uus\n",
1601 POWER_UP_TIME / 20);
1602 return false;
1603 }
1604 }
1605
1606 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1607
1608 return true;
1609}
1610
1611bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1612{
1613 struct ath_common *common = ath9k_hw_common(ah);
1614 int status = true, setChip = true;
1615 static const char *modes[] = {
1616 "AWAKE",
1617 "FULL-SLEEP",
1618 "NETWORK SLEEP",
1619 "UNDEFINED"
1620 };
1621
1622 if (ah->power_mode == mode)
1623 return status;
1624
1625 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1626 modes[ah->power_mode], modes[mode]);
1627
1628 switch (mode) {
1629 case ATH9K_PM_AWAKE:
1630 status = ath9k_hw_set_power_awake(ah, setChip);
1631 break;
1632 case ATH9K_PM_FULL_SLEEP:
1633 ath9k_set_power_sleep(ah, setChip);
1634 ah->chip_fullsleep = true;
1635 break;
1636 case ATH9K_PM_NETWORK_SLEEP:
1637 ath9k_set_power_network_sleep(ah, setChip);
1638 break;
1639 default:
1640 ath_err(common, "Unknown power mode %u\n", mode);
1641 return false;
1642 }
1643 ah->power_mode = mode;
1644
1645
1646
1647
1648
1649
1650
1651 if (!(ah->ah_flags & AH_UNPLUGGED))
1652 ATH_DBG_WARN_ON_ONCE(!status);
1653
1654 return status;
1655}
1656EXPORT_SYMBOL(ath9k_hw_setpower);
1657
1658
1659
1660
1661
1662void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1663{
1664 int flags = 0;
1665
1666 ENABLE_REGWRITE_BUFFER(ah);
1667
1668 switch (ah->opmode) {
1669 case NL80211_IFTYPE_ADHOC:
1670 case NL80211_IFTYPE_MESH_POINT:
1671 REG_SET_BIT(ah, AR_TXCFG,
1672 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1673 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1674 TU_TO_USEC(next_beacon +
1675 (ah->atim_window ? ah->
1676 atim_window : 1)));
1677 flags |= AR_NDP_TIMER_EN;
1678 case NL80211_IFTYPE_AP:
1679 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1680 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1681 TU_TO_USEC(next_beacon -
1682 ah->config.
1683 dma_beacon_response_time));
1684 REG_WRITE(ah, AR_NEXT_SWBA,
1685 TU_TO_USEC(next_beacon -
1686 ah->config.
1687 sw_beacon_response_time));
1688 flags |=
1689 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1690 break;
1691 default:
1692 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1693 "%s: unsupported opmode: %d\n",
1694 __func__, ah->opmode);
1695 return;
1696 break;
1697 }
1698
1699 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1700 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1701 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1702 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1703
1704 REGWRITE_BUFFER_FLUSH(ah);
1705
1706 beacon_period &= ~ATH9K_BEACON_ENA;
1707 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1708 ath9k_hw_reset_tsf(ah);
1709 }
1710
1711 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1712}
1713EXPORT_SYMBOL(ath9k_hw_beaconinit);
1714
1715void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1716 const struct ath9k_beacon_state *bs)
1717{
1718 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1719 struct ath9k_hw_capabilities *pCap = &ah->caps;
1720 struct ath_common *common = ath9k_hw_common(ah);
1721
1722 ENABLE_REGWRITE_BUFFER(ah);
1723
1724 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1725
1726 REG_WRITE(ah, AR_BEACON_PERIOD,
1727 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1728 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1729 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1730
1731 REGWRITE_BUFFER_FLUSH(ah);
1732
1733 REG_RMW_FIELD(ah, AR_RSSI_THR,
1734 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1735
1736 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1737
1738 if (bs->bs_sleepduration > beaconintval)
1739 beaconintval = bs->bs_sleepduration;
1740
1741 dtimperiod = bs->bs_dtimperiod;
1742 if (bs->bs_sleepduration > dtimperiod)
1743 dtimperiod = bs->bs_sleepduration;
1744
1745 if (beaconintval == dtimperiod)
1746 nextTbtt = bs->bs_nextdtim;
1747 else
1748 nextTbtt = bs->bs_nexttbtt;
1749
1750 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1751 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1752 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1753 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1754
1755 ENABLE_REGWRITE_BUFFER(ah);
1756
1757 REG_WRITE(ah, AR_NEXT_DTIM,
1758 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1759 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1760
1761 REG_WRITE(ah, AR_SLEEP1,
1762 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1763 | AR_SLEEP1_ASSUME_DTIM);
1764
1765 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1766 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1767 else
1768 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1769
1770 REG_WRITE(ah, AR_SLEEP2,
1771 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1772
1773 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1774 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1775
1776 REGWRITE_BUFFER_FLUSH(ah);
1777
1778 REG_SET_BIT(ah, AR_TIMER_MODE,
1779 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1780 AR_DTIM_TIMER_EN);
1781
1782
1783 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1784}
1785EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1786
1787
1788
1789
1790
1791int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1792{
1793 struct ath9k_hw_capabilities *pCap = &ah->caps;
1794 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1795 struct ath_common *common = ath9k_hw_common(ah);
1796 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1797
1798 u16 capField = 0, eeval;
1799 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1800
1801 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1802 regulatory->current_rd = eeval;
1803
1804 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1805 if (AR_SREV_9285_12_OR_LATER(ah))
1806 eeval |= AR9285_RDEXT_DEFAULT;
1807 regulatory->current_rd_ext = eeval;
1808
1809 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1810
1811 if (ah->opmode != NL80211_IFTYPE_AP &&
1812 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1813 if (regulatory->current_rd == 0x64 ||
1814 regulatory->current_rd == 0x65)
1815 regulatory->current_rd += 5;
1816 else if (regulatory->current_rd == 0x41)
1817 regulatory->current_rd = 0x43;
1818 ath_dbg(common, ATH_DBG_REGULATORY,
1819 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1820 }
1821
1822 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1823 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1824 ath_err(common,
1825 "no band has been marked as supported in EEPROM\n");
1826 return -EINVAL;
1827 }
1828
1829 if (eeval & AR5416_OPFLAGS_11A)
1830 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1831
1832 if (eeval & AR5416_OPFLAGS_11G)
1833 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1834
1835 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1836
1837
1838
1839
1840 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1841 !(eeval & AR5416_OPFLAGS_11A) &&
1842 !(AR_SREV_9271(ah)))
1843
1844 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1845 else
1846
1847 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1848
1849 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1850
1851
1852 if (AR_SREV_9300_20_OR_LATER(ah))
1853 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1854
1855 pCap->low_2ghz_chan = 2312;
1856 pCap->high_2ghz_chan = 2732;
1857
1858 pCap->low_5ghz_chan = 4920;
1859 pCap->high_5ghz_chan = 6100;
1860
1861 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1862
1863 if (ah->config.ht_enable)
1864 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1865 else
1866 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1867
1868 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1869 pCap->total_queues =
1870 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1871 else
1872 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
1873
1874 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
1875 pCap->keycache_size =
1876 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
1877 else
1878 pCap->keycache_size = AR_KEYTABLE_SIZE;
1879
1880 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1881 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
1882 else
1883 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
1884
1885 if (AR_SREV_9271(ah))
1886 pCap->num_gpio_pins = AR9271_NUM_GPIO;
1887 else if (AR_DEVID_7010(ah))
1888 pCap->num_gpio_pins = AR7010_NUM_GPIO;
1889 else if (AR_SREV_9285_12_OR_LATER(ah))
1890 pCap->num_gpio_pins = AR9285_NUM_GPIO;
1891 else if (AR_SREV_9280_20_OR_LATER(ah))
1892 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1893 else
1894 pCap->num_gpio_pins = AR_NUM_GPIO;
1895
1896 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1897 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1898 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1899 } else {
1900 pCap->rts_aggr_limit = (8 * 1024);
1901 }
1902
1903 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
1904
1905#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1906 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1907 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1908 ah->rfkill_gpio =
1909 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1910 ah->rfkill_polarity =
1911 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1912
1913 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1914 }
1915#endif
1916 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
1917 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1918 else
1919 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1920
1921 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1922 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1923 else
1924 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1925
1926 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
1927 pCap->reg_cap =
1928 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1929 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
1930 AR_EEPROM_EEREGCAP_EN_KK_U2 |
1931 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
1932 } else {
1933 pCap->reg_cap =
1934 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1935 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
1936 }
1937
1938
1939 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
1940 AR_SREV_5416(ah))
1941 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
1942
1943 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
1944 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1945 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
1946
1947 if (AR_SREV_9285(ah)) {
1948 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1949 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
1950 } else {
1951 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1952 }
1953 } else {
1954 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
1955 }
1956
1957 if (AR_SREV_9300_20_OR_LATER(ah)) {
1958 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
1959 if (!AR_SREV_9485(ah))
1960 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1961
1962 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1963 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1964 pCap->rx_status_len = sizeof(struct ar9003_rxs);
1965 pCap->tx_desc_len = sizeof(struct ar9003_txc);
1966 pCap->txs_len = sizeof(struct ar9003_txs);
1967 if (!ah->config.paprd_disable &&
1968 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1969 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1970 } else {
1971 pCap->tx_desc_len = sizeof(struct ath_desc);
1972 if (AR_SREV_9280_20(ah) &&
1973 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1974 AR5416_EEP_MINOR_VER_16) ||
1975 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
1976 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
1977 }
1978
1979 if (AR_SREV_9300_20_OR_LATER(ah))
1980 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
1981
1982 if (AR_SREV_9300_20_OR_LATER(ah))
1983 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
1984
1985 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
1986 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1987
1988 if (AR_SREV_9285(ah))
1989 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
1990 ant_div_ctl1 =
1991 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1992 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1993 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
1994 }
1995 if (AR_SREV_9300_20_OR_LATER(ah)) {
1996 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
1997 pCap->hw_caps |= ATH9K_HW_CAP_APM;
1998 }
1999
2000
2001
2002 if (AR_SREV_9485_10(ah)) {
2003 pCap->pcie_lcr_extsync_en = true;
2004 pCap->pcie_lcr_offset = 0x80;
2005 }
2006
2007 tx_chainmask = pCap->tx_chainmask;
2008 rx_chainmask = pCap->rx_chainmask;
2009 while (tx_chainmask || rx_chainmask) {
2010 if (tx_chainmask & BIT(0))
2011 pCap->max_txchains++;
2012 if (rx_chainmask & BIT(0))
2013 pCap->max_rxchains++;
2014
2015 tx_chainmask >>= 1;
2016 rx_chainmask >>= 1;
2017 }
2018
2019 return 0;
2020}
2021
2022
2023
2024
2025
2026static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2027 u32 gpio, u32 type)
2028{
2029 int addr;
2030 u32 gpio_shift, tmp;
2031
2032 if (gpio > 11)
2033 addr = AR_GPIO_OUTPUT_MUX3;
2034 else if (gpio > 5)
2035 addr = AR_GPIO_OUTPUT_MUX2;
2036 else
2037 addr = AR_GPIO_OUTPUT_MUX1;
2038
2039 gpio_shift = (gpio % 6) * 5;
2040
2041 if (AR_SREV_9280_20_OR_LATER(ah)
2042 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2043 REG_RMW(ah, addr, (type << gpio_shift),
2044 (0x1f << gpio_shift));
2045 } else {
2046 tmp = REG_READ(ah, addr);
2047 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2048 tmp &= ~(0x1f << gpio_shift);
2049 tmp |= (type << gpio_shift);
2050 REG_WRITE(ah, addr, tmp);
2051 }
2052}
2053
2054void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2055{
2056 u32 gpio_shift;
2057
2058 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2059
2060 if (AR_DEVID_7010(ah)) {
2061 gpio_shift = gpio;
2062 REG_RMW(ah, AR7010_GPIO_OE,
2063 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2064 (AR7010_GPIO_OE_MASK << gpio_shift));
2065 return;
2066 }
2067
2068 gpio_shift = gpio << 1;
2069 REG_RMW(ah,
2070 AR_GPIO_OE_OUT,
2071 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2072 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2073}
2074EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2075
2076u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2077{
2078#define MS_REG_READ(x, y) \
2079 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2080
2081 if (gpio >= ah->caps.num_gpio_pins)
2082 return 0xffffffff;
2083
2084 if (AR_DEVID_7010(ah)) {
2085 u32 val;
2086 val = REG_READ(ah, AR7010_GPIO_IN);
2087 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2088 } else if (AR_SREV_9300_20_OR_LATER(ah))
2089 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2090 AR_GPIO_BIT(gpio)) != 0;
2091 else if (AR_SREV_9271(ah))
2092 return MS_REG_READ(AR9271, gpio) != 0;
2093 else if (AR_SREV_9287_11_OR_LATER(ah))
2094 return MS_REG_READ(AR9287, gpio) != 0;
2095 else if (AR_SREV_9285_12_OR_LATER(ah))
2096 return MS_REG_READ(AR9285, gpio) != 0;
2097 else if (AR_SREV_9280_20_OR_LATER(ah))
2098 return MS_REG_READ(AR928X, gpio) != 0;
2099 else
2100 return MS_REG_READ(AR, gpio) != 0;
2101}
2102EXPORT_SYMBOL(ath9k_hw_gpio_get);
2103
2104void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2105 u32 ah_signal_type)
2106{
2107 u32 gpio_shift;
2108
2109 if (AR_DEVID_7010(ah)) {
2110 gpio_shift = gpio;
2111 REG_RMW(ah, AR7010_GPIO_OE,
2112 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2113 (AR7010_GPIO_OE_MASK << gpio_shift));
2114 return;
2115 }
2116
2117 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2118 gpio_shift = 2 * gpio;
2119 REG_RMW(ah,
2120 AR_GPIO_OE_OUT,
2121 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2122 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2123}
2124EXPORT_SYMBOL(ath9k_hw_cfg_output);
2125
2126void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2127{
2128 if (AR_DEVID_7010(ah)) {
2129 val = val ? 0 : 1;
2130 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2131 AR_GPIO_BIT(gpio));
2132 return;
2133 }
2134
2135 if (AR_SREV_9271(ah))
2136 val = ~val;
2137
2138 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2139 AR_GPIO_BIT(gpio));
2140}
2141EXPORT_SYMBOL(ath9k_hw_set_gpio);
2142
2143u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2144{
2145 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2146}
2147EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2148
2149void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2150{
2151 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2152}
2153EXPORT_SYMBOL(ath9k_hw_setantenna);
2154
2155
2156
2157
2158
2159u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2160{
2161 u32 bits = REG_READ(ah, AR_RX_FILTER);
2162 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2163
2164 if (phybits & AR_PHY_ERR_RADAR)
2165 bits |= ATH9K_RX_FILTER_PHYRADAR;
2166 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2167 bits |= ATH9K_RX_FILTER_PHYERR;
2168
2169 return bits;
2170}
2171EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2172
2173void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2174{
2175 u32 phybits;
2176
2177 ENABLE_REGWRITE_BUFFER(ah);
2178
2179 REG_WRITE(ah, AR_RX_FILTER, bits);
2180
2181 phybits = 0;
2182 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2183 phybits |= AR_PHY_ERR_RADAR;
2184 if (bits & ATH9K_RX_FILTER_PHYERR)
2185 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2186 REG_WRITE(ah, AR_PHY_ERR, phybits);
2187
2188 if (phybits)
2189 REG_WRITE(ah, AR_RXCFG,
2190 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2191 else
2192 REG_WRITE(ah, AR_RXCFG,
2193 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2194
2195 REGWRITE_BUFFER_FLUSH(ah);
2196}
2197EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2198
2199bool ath9k_hw_phy_disable(struct ath_hw *ah)
2200{
2201 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2202 return false;
2203
2204 ath9k_hw_init_pll(ah, NULL);
2205 return true;
2206}
2207EXPORT_SYMBOL(ath9k_hw_phy_disable);
2208
2209bool ath9k_hw_disable(struct ath_hw *ah)
2210{
2211 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2212 return false;
2213
2214 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2215 return false;
2216
2217 ath9k_hw_init_pll(ah, NULL);
2218 return true;
2219}
2220EXPORT_SYMBOL(ath9k_hw_disable);
2221
2222void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2223{
2224 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2225 struct ath9k_channel *chan = ah->curchan;
2226 struct ieee80211_channel *channel = chan->chan;
2227
2228 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2229
2230 ah->eep_ops->set_txpower(ah, chan,
2231 ath9k_regd_get_ctl(regulatory, chan),
2232 channel->max_antenna_gain * 2,
2233 channel->max_power * 2,
2234 min((u32) MAX_RATE_POWER,
2235 (u32) regulatory->power_limit), test);
2236}
2237EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2238
2239void ath9k_hw_setopmode(struct ath_hw *ah)
2240{
2241 ath9k_hw_set_operating_mode(ah, ah->opmode);
2242}
2243EXPORT_SYMBOL(ath9k_hw_setopmode);
2244
2245void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2246{
2247 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2248 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2249}
2250EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2251
2252void ath9k_hw_write_associd(struct ath_hw *ah)
2253{
2254 struct ath_common *common = ath9k_hw_common(ah);
2255
2256 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2257 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2258 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2259}
2260EXPORT_SYMBOL(ath9k_hw_write_associd);
2261
2262#define ATH9K_MAX_TSF_READ 10
2263
2264u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2265{
2266 u32 tsf_lower, tsf_upper1, tsf_upper2;
2267 int i;
2268
2269 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2270 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2271 tsf_lower = REG_READ(ah, AR_TSF_L32);
2272 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2273 if (tsf_upper2 == tsf_upper1)
2274 break;
2275 tsf_upper1 = tsf_upper2;
2276 }
2277
2278 WARN_ON( i == ATH9K_MAX_TSF_READ );
2279
2280 return (((u64)tsf_upper1 << 32) | tsf_lower);
2281}
2282EXPORT_SYMBOL(ath9k_hw_gettsf64);
2283
2284void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2285{
2286 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2287 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2288}
2289EXPORT_SYMBOL(ath9k_hw_settsf64);
2290
2291void ath9k_hw_reset_tsf(struct ath_hw *ah)
2292{
2293 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2294 AH_TSF_WRITE_TIMEOUT))
2295 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2296 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2297
2298 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2299}
2300EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2301
2302void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2303{
2304 if (setting)
2305 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2306 else
2307 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2308}
2309EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2310
2311void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2312{
2313 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2314 u32 macmode;
2315
2316 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2317 macmode = AR_2040_JOINED_RX_CLEAR;
2318 else
2319 macmode = 0;
2320
2321 REG_WRITE(ah, AR_2040_MODE, macmode);
2322}
2323
2324
2325
2326static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2327{
2328 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2329 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2330 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2331 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2332 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2333 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2334 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2335 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2336 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2337 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2338 AR_NDP2_TIMER_MODE, 0x0002},
2339 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2340 AR_NDP2_TIMER_MODE, 0x0004},
2341 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2342 AR_NDP2_TIMER_MODE, 0x0008},
2343 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2344 AR_NDP2_TIMER_MODE, 0x0010},
2345 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2346 AR_NDP2_TIMER_MODE, 0x0020},
2347 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2348 AR_NDP2_TIMER_MODE, 0x0040},
2349 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2350 AR_NDP2_TIMER_MODE, 0x0080}
2351};
2352
2353
2354
2355
2356static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2357{
2358 u32 b;
2359
2360 b = *mask;
2361 b &= (0-b);
2362 *mask &= ~b;
2363 b *= debruijn32;
2364 b >>= 27;
2365
2366 return timer_table->gen_timer_index[b];
2367}
2368
2369static u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2370{
2371 return REG_READ(ah, AR_TSF_L32);
2372}
2373
2374struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2375 void (*trigger)(void *),
2376 void (*overflow)(void *),
2377 void *arg,
2378 u8 timer_index)
2379{
2380 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2381 struct ath_gen_timer *timer;
2382
2383 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2384
2385 if (timer == NULL) {
2386 ath_err(ath9k_hw_common(ah),
2387 "Failed to allocate memory for hw timer[%d]\n",
2388 timer_index);
2389 return NULL;
2390 }
2391
2392
2393 timer_table->timers[timer_index] = timer;
2394 timer->index = timer_index;
2395 timer->trigger = trigger;
2396 timer->overflow = overflow;
2397 timer->arg = arg;
2398
2399 return timer;
2400}
2401EXPORT_SYMBOL(ath_gen_timer_alloc);
2402
2403void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2404 struct ath_gen_timer *timer,
2405 u32 timer_next,
2406 u32 timer_period)
2407{
2408 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2409 u32 tsf;
2410
2411 BUG_ON(!timer_period);
2412
2413 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2414
2415 tsf = ath9k_hw_gettsf32(ah);
2416
2417 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2418 "current tsf %x period %x timer_next %x\n",
2419 tsf, timer_period, timer_next);
2420
2421
2422
2423
2424
2425 if (timer_next < tsf)
2426 timer_next = tsf + timer_period;
2427
2428
2429
2430
2431 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2432 timer_next);
2433 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2434 timer_period);
2435 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2436 gen_tmr_configuration[timer->index].mode_mask);
2437
2438
2439 REG_SET_BIT(ah, AR_IMR_S5,
2440 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2441 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2442}
2443EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2444
2445void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2446{
2447 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2448
2449 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2450 (timer->index >= ATH_MAX_GEN_TIMER)) {
2451 return;
2452 }
2453
2454
2455 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2456 gen_tmr_configuration[timer->index].mode_mask);
2457
2458
2459 REG_CLR_BIT(ah, AR_IMR_S5,
2460 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2461 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2462
2463 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2464}
2465EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2466
2467void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2468{
2469 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2470
2471
2472 timer_table->timers[timer->index] = NULL;
2473 kfree(timer);
2474}
2475EXPORT_SYMBOL(ath_gen_timer_free);
2476
2477
2478
2479
2480void ath_gen_timer_isr(struct ath_hw *ah)
2481{
2482 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2483 struct ath_gen_timer *timer;
2484 struct ath_common *common = ath9k_hw_common(ah);
2485 u32 trigger_mask, thresh_mask, index;
2486
2487
2488 trigger_mask = ah->intr_gen_timer_trigger;
2489 thresh_mask = ah->intr_gen_timer_thresh;
2490 trigger_mask &= timer_table->timer_mask.val;
2491 thresh_mask &= timer_table->timer_mask.val;
2492
2493 trigger_mask &= ~thresh_mask;
2494
2495 while (thresh_mask) {
2496 index = rightmost_index(timer_table, &thresh_mask);
2497 timer = timer_table->timers[index];
2498 BUG_ON(!timer);
2499 ath_dbg(common, ATH_DBG_HWTIMER,
2500 "TSF overflow for Gen timer %d\n", index);
2501 timer->overflow(timer->arg);
2502 }
2503
2504 while (trigger_mask) {
2505 index = rightmost_index(timer_table, &trigger_mask);
2506 timer = timer_table->timers[index];
2507 BUG_ON(!timer);
2508 ath_dbg(common, ATH_DBG_HWTIMER,
2509 "Gen timer[%d] trigger\n", index);
2510 timer->trigger(timer->arg);
2511 }
2512}
2513EXPORT_SYMBOL(ath_gen_timer_isr);
2514
2515
2516
2517
2518
2519void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2520{
2521 ah->htc_reset_init = true;
2522}
2523EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2524
2525static struct {
2526 u32 version;
2527 const char * name;
2528} ath_mac_bb_names[] = {
2529
2530 { AR_SREV_VERSION_5416_PCI, "5416" },
2531 { AR_SREV_VERSION_5416_PCIE, "5418" },
2532 { AR_SREV_VERSION_9100, "9100" },
2533 { AR_SREV_VERSION_9160, "9160" },
2534
2535 { AR_SREV_VERSION_9280, "9280" },
2536 { AR_SREV_VERSION_9285, "9285" },
2537 { AR_SREV_VERSION_9287, "9287" },
2538 { AR_SREV_VERSION_9271, "9271" },
2539 { AR_SREV_VERSION_9300, "9300" },
2540 { AR_SREV_VERSION_9485, "9485" },
2541};
2542
2543
2544static struct {
2545 u16 version;
2546 const char * name;
2547} ath_rf_names[] = {
2548 { 0, "5133" },
2549 { AR_RAD5133_SREV_MAJOR, "5133" },
2550 { AR_RAD5122_SREV_MAJOR, "5122" },
2551 { AR_RAD2133_SREV_MAJOR, "2133" },
2552 { AR_RAD2122_SREV_MAJOR, "2122" }
2553};
2554
2555
2556
2557
2558static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2559{
2560 int i;
2561
2562 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2563 if (ath_mac_bb_names[i].version == mac_bb_version) {
2564 return ath_mac_bb_names[i].name;
2565 }
2566 }
2567
2568 return "????";
2569}
2570
2571
2572
2573
2574
2575static const char *ath9k_hw_rf_name(u16 rf_version)
2576{
2577 int i;
2578
2579 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2580 if (ath_rf_names[i].version == rf_version) {
2581 return ath_rf_names[i].name;
2582 }
2583 }
2584
2585 return "????";
2586}
2587
2588void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2589{
2590 int used;
2591
2592
2593 if (AR_SREV_9280_20_OR_LATER(ah)) {
2594 used = snprintf(hw_name, len,
2595 "Atheros AR%s Rev:%x",
2596 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2597 ah->hw_version.macRev);
2598 }
2599 else {
2600 used = snprintf(hw_name, len,
2601 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2602 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2603 ah->hw_version.macRev,
2604 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2605 AR_RADIO_SREV_MAJOR)),
2606 ah->hw_version.phyRev);
2607 }
2608
2609 hw_name[used] = '\0';
2610}
2611EXPORT_SYMBOL(ath9k_hw_name);
2612
