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25#include <linux/delay.h>
26#include <linux/slab.h>
27#include <linux/types.h>
28
29#include "b43.h"
30#include "phy_n.h"
31#include "tables_nphy.h"
32#include "radio_2055.h"
33#include "radio_2056.h"
34#include "main.h"
35
36struct nphy_txgains {
37 u16 txgm[2];
38 u16 pga[2];
39 u16 pad[2];
40 u16 ipa[2];
41};
42
43struct nphy_iqcal_params {
44 u16 txgm;
45 u16 pga;
46 u16 pad;
47 u16 ipa;
48 u16 cal_gain;
49 u16 ncorr[5];
50};
51
52struct nphy_iq_est {
53 s32 iq0_prod;
54 u32 i0_pwr;
55 u32 q0_pwr;
56 s32 iq1_prod;
57 u32 i1_pwr;
58 u32 q1_pwr;
59};
60
61enum b43_nphy_rf_sequence {
62 B43_RFSEQ_RX2TX,
63 B43_RFSEQ_TX2RX,
64 B43_RFSEQ_RESET2RX,
65 B43_RFSEQ_UPDATE_GAINH,
66 B43_RFSEQ_UPDATE_GAINL,
67 B43_RFSEQ_UPDATE_GAINU,
68};
69
70enum b43_nphy_rssi_type {
71 B43_NPHY_RSSI_X = 0,
72 B43_NPHY_RSSI_Y,
73 B43_NPHY_RSSI_Z,
74 B43_NPHY_RSSI_PWRDET,
75 B43_NPHY_RSSI_TSSI_I,
76 B43_NPHY_RSSI_TSSI_Q,
77 B43_NPHY_RSSI_TBD,
78};
79
80static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
81 bool enable);
82static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
83 u8 *events, u8 *delays, u8 length);
84static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
85 enum b43_nphy_rf_sequence seq);
86static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
87 u16 value, u8 core, bool off);
88static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
89 u16 value, u8 core);
90
91void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
92{
93}
94
95static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
96{
97}
98
99static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
100 bool ignore_tssi)
101{
102 return B43_TXPWR_RES_DONE;
103}
104
105static void b43_chantab_radio_upload(struct b43_wldev *dev,
106 const struct b43_nphy_channeltab_entry_rev2 *e)
107{
108 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
109 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
110 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
111 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
112 b43_read32(dev, B43_MMIO_MACCTL);
113
114 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
115 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
116 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
117 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
118 b43_read32(dev, B43_MMIO_MACCTL);
119
120 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
121 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
122 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
123 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
124 b43_read32(dev, B43_MMIO_MACCTL);
125
126 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
127 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
128 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
129 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
130 b43_read32(dev, B43_MMIO_MACCTL);
131
132 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
133 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
134 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
135 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
136 b43_read32(dev, B43_MMIO_MACCTL);
137
138 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
139 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
140}
141
142static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
143 const struct b43_nphy_channeltab_entry_rev3 *e)
144{
145 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
146 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
147 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
148 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
149 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
150 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
151 e->radio_syn_pll_loopfilter1);
152 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
153 e->radio_syn_pll_loopfilter2);
154 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
155 e->radio_syn_pll_loopfilter3);
156 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
157 e->radio_syn_pll_loopfilter4);
158 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
159 e->radio_syn_pll_loopfilter5);
160 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
161 e->radio_syn_reserved_addr27);
162 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
163 e->radio_syn_reserved_addr28);
164 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
165 e->radio_syn_reserved_addr29);
166 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
167 e->radio_syn_logen_vcobuf1);
168 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
169 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
170 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
171
172 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
173 e->radio_rx0_lnaa_tune);
174 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
175 e->radio_rx0_lnag_tune);
176
177 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
178 e->radio_tx0_intpaa_boost_tune);
179 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
180 e->radio_tx0_intpag_boost_tune);
181 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
182 e->radio_tx0_pada_boost_tune);
183 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
184 e->radio_tx0_padg_boost_tune);
185 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
186 e->radio_tx0_pgaa_boost_tune);
187 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
188 e->radio_tx0_pgag_boost_tune);
189 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
190 e->radio_tx0_mixa_boost_tune);
191 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
192 e->radio_tx0_mixg_boost_tune);
193
194 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
195 e->radio_rx1_lnaa_tune);
196 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
197 e->radio_rx1_lnag_tune);
198
199 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
200 e->radio_tx1_intpaa_boost_tune);
201 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
202 e->radio_tx1_intpag_boost_tune);
203 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
204 e->radio_tx1_pada_boost_tune);
205 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
206 e->radio_tx1_padg_boost_tune);
207 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
208 e->radio_tx1_pgaa_boost_tune);
209 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
210 e->radio_tx1_pgag_boost_tune);
211 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
212 e->radio_tx1_mixa_boost_tune);
213 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
214 e->radio_tx1_mixg_boost_tune);
215}
216
217
218static void b43_radio_2056_setup(struct b43_wldev *dev,
219 const struct b43_nphy_channeltab_entry_rev3 *e)
220{
221 B43_WARN_ON(dev->phy.rev < 3);
222
223 b43_chantab_radio_2056_upload(dev, e);
224
225 udelay(50);
226
227 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
228 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
229 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
230 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
231 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
232 udelay(300);
233}
234
235static void b43_chantab_phy_upload(struct b43_wldev *dev,
236 const struct b43_phy_n_sfo_cfg *e)
237{
238 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
239 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
240 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
241 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
242 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
243 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
244}
245
246
247static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
248{
249 struct b43_phy_n *nphy = dev->phy.n;
250 u8 i;
251 u16 tmp;
252
253 if (nphy->hang_avoid)
254 b43_nphy_stay_in_carrier_search(dev, 1);
255
256 nphy->txpwrctrl = enable;
257 if (!enable) {
258 if (dev->phy.rev >= 3)
259 ;
260
261 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
262 for (i = 0; i < 84; i++)
263 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
264
265 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
266 for (i = 0; i < 84; i++)
267 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
268
269 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
270 if (dev->phy.rev >= 3)
271 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
272 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
273
274 if (dev->phy.rev >= 3) {
275 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
276 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
277 } else {
278 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
279 }
280
281 if (dev->phy.rev == 2)
282 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
283 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
284 else if (dev->phy.rev < 2)
285 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
286 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
287
288 if (dev->phy.rev < 2 && 0)
289 ;
290 } else {
291 b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n");
292 }
293
294 if (nphy->hang_avoid)
295 b43_nphy_stay_in_carrier_search(dev, 0);
296}
297
298
299static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
300{
301 struct b43_phy_n *nphy = dev->phy.n;
302 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
303
304 u8 txpi[2], bbmult, i;
305 u16 tmp, radio_gain, dac_gain;
306 u16 freq = dev->phy.channel_freq;
307 u32 txgain;
308
309
310 if (nphy->hang_avoid)
311 b43_nphy_stay_in_carrier_search(dev, 1);
312
313 if (dev->phy.rev >= 3) {
314 txpi[0] = 40;
315 txpi[1] = 40;
316 } else if (sprom->revision < 4) {
317 txpi[0] = 72;
318 txpi[1] = 72;
319 } else {
320 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
321 txpi[0] = sprom->txpid2g[0];
322 txpi[1] = sprom->txpid2g[1];
323 } else if (freq >= 4900 && freq < 5100) {
324 txpi[0] = sprom->txpid5gl[0];
325 txpi[1] = sprom->txpid5gl[1];
326 } else if (freq >= 5100 && freq < 5500) {
327 txpi[0] = sprom->txpid5g[0];
328 txpi[1] = sprom->txpid5g[1];
329 } else if (freq >= 5500) {
330 txpi[0] = sprom->txpid5gh[0];
331 txpi[1] = sprom->txpid5gh[1];
332 } else {
333 txpi[0] = 91;
334 txpi[1] = 91;
335 }
336 }
337
338
339
340
341
342
343
344
345 for (i = 0; i < 2; i++) {
346 if (dev->phy.rev >= 3) {
347
348 txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
349 radio_gain = (txgain >> 16) & 0x1FFFF;
350 } else {
351 txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
352 radio_gain = (txgain >> 16) & 0x1FFF;
353 }
354
355 dac_gain = (txgain >> 8) & 0x3F;
356 bbmult = txgain & 0xFF;
357
358 if (dev->phy.rev >= 3) {
359 if (i == 0)
360 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
361 else
362 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
363 } else {
364 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
365 }
366
367 if (i == 0)
368 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
369 else
370 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
371
372 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i);
373 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain);
374
375 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
376 tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
377
378 if (i == 0)
379 tmp = (tmp & 0x00FF) | (bbmult << 8);
380 else
381 tmp = (tmp & 0xFF00) | bbmult;
382
383 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
384 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp);
385
386 if (0)
387 ;
388 }
389
390 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
391
392 if (nphy->hang_avoid)
393 b43_nphy_stay_in_carrier_search(dev, 0);
394}
395
396
397
398static void b43_radio_2055_setup(struct b43_wldev *dev,
399 const struct b43_nphy_channeltab_entry_rev2 *e)
400{
401 B43_WARN_ON(dev->phy.rev >= 3);
402
403 b43_chantab_radio_upload(dev, e);
404 udelay(50);
405 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
406 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
407 b43_read32(dev, B43_MMIO_MACCTL);
408 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
409 udelay(300);
410}
411
412static void b43_radio_init2055_pre(struct b43_wldev *dev)
413{
414 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
415 ~B43_NPHY_RFCTL_CMD_PORFORCE);
416 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
417 B43_NPHY_RFCTL_CMD_CHIP0PU |
418 B43_NPHY_RFCTL_CMD_OEPORFORCE);
419 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
420 B43_NPHY_RFCTL_CMD_PORFORCE);
421}
422
423static void b43_radio_init2055_post(struct b43_wldev *dev)
424{
425 struct b43_phy_n *nphy = dev->phy.n;
426 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
427 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
428 int i;
429 u16 val;
430 bool workaround = false;
431
432 if (sprom->revision < 4)
433 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM &&
434 binfo->type == 0x46D &&
435 binfo->rev >= 0x41);
436 else
437 workaround =
438 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
439
440 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
441 if (workaround) {
442 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
443 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
444 }
445 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
446 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
447 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
448 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
449 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
450 msleep(1);
451 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
452 for (i = 0; i < 200; i++) {
453 val = b43_radio_read(dev, B2055_CAL_COUT2);
454 if (val & 0x80) {
455 i = 0;
456 break;
457 }
458 udelay(10);
459 }
460 if (i)
461 b43err(dev->wl, "radio post init timeout\n");
462 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
463 b43_switch_channel(dev, dev->phy.channel);
464 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
465 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
466 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
467 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
468 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
469 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
470 if (!nphy->gain_boost) {
471 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
472 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
473 } else {
474 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
475 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
476 }
477 udelay(2);
478}
479
480
481
482
483
484static void b43_radio_init2055(struct b43_wldev *dev)
485{
486 b43_radio_init2055_pre(dev);
487 if (b43_status(dev) < B43_STAT_INITIALIZED) {
488
489 b2055_upload_inittab(dev, 0, 0);
490 } else {
491 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
492 b2055_upload_inittab(dev, ghz5, 0);
493 }
494 b43_radio_init2055_post(dev);
495}
496
497static void b43_radio_init2056_pre(struct b43_wldev *dev)
498{
499 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
500 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
501
502 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
503 B43_NPHY_RFCTL_CMD_OEPORFORCE);
504 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
505 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
506 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
507 B43_NPHY_RFCTL_CMD_CHIP0PU);
508}
509
510static void b43_radio_init2056_post(struct b43_wldev *dev)
511{
512 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
513 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
514 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
515 msleep(1);
516 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
517 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
518 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
519
520
521
522
523}
524
525
526
527
528
529static void b43_radio_init2056(struct b43_wldev *dev)
530{
531 b43_radio_init2056_pre(dev);
532 b2056_upload_inittabs(dev, 0, 0);
533 b43_radio_init2056_post(dev);
534}
535
536
537
538
539
540static void b43_nphy_tables_init(struct b43_wldev *dev)
541{
542 if (dev->phy.rev < 3)
543 b43_nphy_rev0_1_2_tables_init(dev);
544 else
545 b43_nphy_rev3plus_tables_init(dev);
546}
547
548
549static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
550{
551 struct b43_phy_n *nphy = dev->phy.n;
552 enum ieee80211_band band;
553 u16 tmp;
554
555 if (!enable) {
556 nphy->rfctrl_intc1_save = b43_phy_read(dev,
557 B43_NPHY_RFCTL_INTC1);
558 nphy->rfctrl_intc2_save = b43_phy_read(dev,
559 B43_NPHY_RFCTL_INTC2);
560 band = b43_current_band(dev->wl);
561 if (dev->phy.rev >= 3) {
562 if (band == IEEE80211_BAND_5GHZ)
563 tmp = 0x600;
564 else
565 tmp = 0x480;
566 } else {
567 if (band == IEEE80211_BAND_5GHZ)
568 tmp = 0x180;
569 else
570 tmp = 0x120;
571 }
572 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
573 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
574 } else {
575 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
576 nphy->rfctrl_intc1_save);
577 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
578 nphy->rfctrl_intc2_save);
579 }
580}
581
582
583static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
584{
585 struct b43_phy_n *nphy = dev->phy.n;
586 u16 tmp;
587 enum ieee80211_band band = b43_current_band(dev->wl);
588 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
589 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
590
591 if (dev->phy.rev >= 3) {
592 if (ipa) {
593 tmp = 4;
594 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
595 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
596 }
597
598 tmp = 1;
599 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
600 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
601 }
602}
603
604
605static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
606{
607 u32 tmslow;
608
609 if (dev->phy.type != B43_PHYTYPE_N)
610 return;
611
612 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
613 if (force)
614 tmslow |= SSB_TMSLOW_FGC;
615 else
616 tmslow &= ~SSB_TMSLOW_FGC;
617 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
618}
619
620
621static void b43_nphy_reset_cca(struct b43_wldev *dev)
622{
623 u16 bbcfg;
624
625 b43_nphy_bmac_clock_fgc(dev, 1);
626 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
627 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
628 udelay(1);
629 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
630 b43_nphy_bmac_clock_fgc(dev, 0);
631 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
632}
633
634
635static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
636{
637 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
638
639 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
640 if (preamble == 1)
641 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
642 else
643 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
644
645 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
646}
647
648
649static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
650{
651 struct b43_phy_n *nphy = dev->phy.n;
652
653 bool override = false;
654 u16 chain = 0x33;
655
656 if (nphy->txrx_chain == 0) {
657 chain = 0x11;
658 override = true;
659 } else if (nphy->txrx_chain == 1) {
660 chain = 0x22;
661 override = true;
662 }
663
664 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
665 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
666 chain);
667
668 if (override)
669 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
670 B43_NPHY_RFSEQMODE_CAOVER);
671 else
672 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
673 ~B43_NPHY_RFSEQMODE_CAOVER);
674}
675
676
677static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
678 u16 samps, u8 time, bool wait)
679{
680 int i;
681 u16 tmp;
682
683 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
684 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
685 if (wait)
686 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
687 else
688 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
689
690 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
691
692 for (i = 1000; i; i--) {
693 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
694 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
695 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
696 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
697 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
698 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
699 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
700 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
701
702 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
703 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
704 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
705 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
706 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
707 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
708 return;
709 }
710 udelay(10);
711 }
712 memset(est, 0, sizeof(*est));
713}
714
715
716static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
717 struct b43_phy_n_iq_comp *pcomp)
718{
719 if (write) {
720 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
721 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
722 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
723 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
724 } else {
725 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
726 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
727 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
728 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
729 }
730}
731
732#if 0
733
734
735static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
736{
737 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
738
739 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
740 if (core == 0) {
741 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
742 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
743 } else {
744 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
745 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
746 }
747 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
748 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
749 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
750 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
751 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
752 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
753 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
754 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
755}
756
757
758static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
759{
760 u8 rxval, txval;
761 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
762
763 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
764 if (core == 0) {
765 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
766 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
767 } else {
768 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
769 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
770 }
771 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
772 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
773 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
774 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
775 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
776 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
777 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
778 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
779
780 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
781 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
782
783 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
784 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
785 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
786 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
787 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
788 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
789 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
790 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
791 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
792
793 if (core == 0) {
794 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
795 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
796 } else {
797 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
798 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
799 }
800
801 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
802 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
803 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
804
805 if (core == 0) {
806 rxval = 1;
807 txval = 8;
808 } else {
809 rxval = 4;
810 txval = 2;
811 }
812 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
813 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
814}
815#endif
816
817
818static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
819{
820 int i;
821 s32 iq;
822 u32 ii;
823 u32 qq;
824 int iq_nbits, qq_nbits;
825 int arsh, brsh;
826 u16 tmp, a, b;
827
828 struct nphy_iq_est est;
829 struct b43_phy_n_iq_comp old;
830 struct b43_phy_n_iq_comp new = { };
831 bool error = false;
832
833 if (mask == 0)
834 return;
835
836 b43_nphy_rx_iq_coeffs(dev, false, &old);
837 b43_nphy_rx_iq_coeffs(dev, true, &new);
838 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
839 new = old;
840
841 for (i = 0; i < 2; i++) {
842 if (i == 0 && (mask & 1)) {
843 iq = est.iq0_prod;
844 ii = est.i0_pwr;
845 qq = est.q0_pwr;
846 } else if (i == 1 && (mask & 2)) {
847 iq = est.iq1_prod;
848 ii = est.i1_pwr;
849 qq = est.q1_pwr;
850 } else {
851 continue;
852 }
853
854 if (ii + qq < 2) {
855 error = true;
856 break;
857 }
858
859 iq_nbits = fls(abs(iq));
860 qq_nbits = fls(qq);
861
862 arsh = iq_nbits - 20;
863 if (arsh >= 0) {
864 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
865 tmp = ii >> arsh;
866 } else {
867 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
868 tmp = ii << -arsh;
869 }
870 if (tmp == 0) {
871 error = true;
872 break;
873 }
874 a /= tmp;
875
876 brsh = qq_nbits - 11;
877 if (brsh >= 0) {
878 b = (qq << (31 - qq_nbits));
879 tmp = ii >> brsh;
880 } else {
881 b = (qq << (31 - qq_nbits));
882 tmp = ii << -brsh;
883 }
884 if (tmp == 0) {
885 error = true;
886 break;
887 }
888 b = int_sqrt(b / tmp - a * a) - (1 << 10);
889
890 if (i == 0 && (mask & 0x1)) {
891 if (dev->phy.rev >= 3) {
892 new.a0 = a & 0x3FF;
893 new.b0 = b & 0x3FF;
894 } else {
895 new.a0 = b & 0x3FF;
896 new.b0 = a & 0x3FF;
897 }
898 } else if (i == 1 && (mask & 0x2)) {
899 if (dev->phy.rev >= 3) {
900 new.a1 = a & 0x3FF;
901 new.b1 = b & 0x3FF;
902 } else {
903 new.a1 = b & 0x3FF;
904 new.b1 = a & 0x3FF;
905 }
906 }
907 }
908
909 if (error)
910 new = old;
911
912 b43_nphy_rx_iq_coeffs(dev, true, &new);
913}
914
915
916static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
917{
918 u16 array[4];
919 int i;
920
921 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
922 for (i = 0; i < 4; i++)
923 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
924
925 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
926 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
927 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
928 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
929}
930
931
932static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
933 const u16 *clip_st)
934{
935 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
936 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
937}
938
939
940static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
941{
942 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
943 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
944}
945
946
947static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
948{
949 if (dev->phy.rev >= 3) {
950 if (!init)
951 return;
952 if (0 ) {
953 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
954 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
955 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
956 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
957 }
958 } else {
959 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
960 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
961
962 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
963 0xFC00);
964 b43_write32(dev, B43_MMIO_MACCTL,
965 b43_read32(dev, B43_MMIO_MACCTL) &
966 ~B43_MACCTL_GPOUTSMSK);
967 b43_write16(dev, B43_MMIO_GPIO_MASK,
968 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
969 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
970 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
971
972 if (init) {
973 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
974 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
975 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
976 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
977 }
978 }
979}
980
981
982static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
983{
984 u16 tmp;
985
986 if (dev->dev->id.revision == 16)
987 b43_mac_suspend(dev);
988
989 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
990 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
991 B43_NPHY_CLASSCTL_WAITEDEN);
992 tmp &= ~mask;
993 tmp |= (val & mask);
994 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
995
996 if (dev->dev->id.revision == 16)
997 b43_mac_enable(dev);
998
999 return tmp;
1000}
1001
1002
1003static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1004{
1005 struct b43_phy *phy = &dev->phy;
1006 struct b43_phy_n *nphy = phy->n;
1007
1008 if (enable) {
1009 static const u16 clip[] = { 0xFFFF, 0xFFFF };
1010 if (nphy->deaf_count++ == 0) {
1011 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1012 b43_nphy_classifier(dev, 0x7, 0);
1013 b43_nphy_read_clip_detection(dev, nphy->clip_state);
1014 b43_nphy_write_clip_detection(dev, clip);
1015 }
1016 b43_nphy_reset_cca(dev);
1017 } else {
1018 if (--nphy->deaf_count == 0) {
1019 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1020 b43_nphy_write_clip_detection(dev, nphy->clip_state);
1021 }
1022 }
1023}
1024
1025
1026static void b43_nphy_stop_playback(struct b43_wldev *dev)
1027{
1028 struct b43_phy_n *nphy = dev->phy.n;
1029 u16 tmp;
1030
1031 if (nphy->hang_avoid)
1032 b43_nphy_stay_in_carrier_search(dev, 1);
1033
1034 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1035 if (tmp & 0x1)
1036 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1037 else if (tmp & 0x2)
1038 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1039
1040 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1041
1042 if (nphy->bb_mult_save & 0x80000000) {
1043 tmp = nphy->bb_mult_save & 0xFFFF;
1044 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1045 nphy->bb_mult_save = 0;
1046 }
1047
1048 if (nphy->hang_avoid)
1049 b43_nphy_stay_in_carrier_search(dev, 0);
1050}
1051
1052
1053static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1054{
1055 struct b43_phy_n *nphy = dev->phy.n;
1056
1057 u8 channel = dev->phy.channel;
1058 int tone[2] = { 57, 58 };
1059 u32 noise[2] = { 0x3FF, 0x3FF };
1060
1061 B43_WARN_ON(dev->phy.rev < 3);
1062
1063 if (nphy->hang_avoid)
1064 b43_nphy_stay_in_carrier_search(dev, 1);
1065
1066 if (nphy->gband_spurwar_en) {
1067
1068 if (channel == 11 && dev->phy.is_40mhz)
1069 ;
1070 else
1071 ;
1072
1073 }
1074
1075 if (nphy->aband_spurwar_en) {
1076 if (channel == 54) {
1077 tone[0] = 0x20;
1078 noise[0] = 0x25F;
1079 } else if (channel == 38 || channel == 102 || channel == 118) {
1080 if (0 ) {
1081 tone[0] = 0x20;
1082 noise[0] = 0x21F;
1083 } else {
1084 tone[0] = 0;
1085 noise[0] = 0;
1086 }
1087 } else if (channel == 134) {
1088 tone[0] = 0x20;
1089 noise[0] = 0x21F;
1090 } else if (channel == 151) {
1091 tone[0] = 0x10;
1092 noise[0] = 0x23F;
1093 } else if (channel == 153 || channel == 161) {
1094 tone[0] = 0x30;
1095 noise[0] = 0x23F;
1096 } else {
1097 tone[0] = 0;
1098 noise[0] = 0;
1099 }
1100
1101 if (!tone[0] && !noise[0])
1102 ;
1103 else
1104 ;
1105 }
1106
1107 if (nphy->hang_avoid)
1108 b43_nphy_stay_in_carrier_search(dev, 0);
1109}
1110
1111
1112static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1113{
1114 struct b43_phy_n *nphy = dev->phy.n;
1115
1116 u8 i;
1117 s16 tmp;
1118 u16 data[4];
1119 s16 gain[2];
1120 u16 minmax[2];
1121 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1122
1123 if (nphy->hang_avoid)
1124 b43_nphy_stay_in_carrier_search(dev, 1);
1125
1126 if (nphy->gain_boost) {
1127 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1128 gain[0] = 6;
1129 gain[1] = 6;
1130 } else {
1131 tmp = 40370 - 315 * dev->phy.channel;
1132 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1133 tmp = 23242 - 224 * dev->phy.channel;
1134 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1135 }
1136 } else {
1137 gain[0] = 0;
1138 gain[1] = 0;
1139 }
1140
1141 for (i = 0; i < 2; i++) {
1142 if (nphy->elna_gain_config) {
1143 data[0] = 19 + gain[i];
1144 data[1] = 25 + gain[i];
1145 data[2] = 25 + gain[i];
1146 data[3] = 25 + gain[i];
1147 } else {
1148 data[0] = lna_gain[0] + gain[i];
1149 data[1] = lna_gain[1] + gain[i];
1150 data[2] = lna_gain[2] + gain[i];
1151 data[3] = lna_gain[3] + gain[i];
1152 }
1153 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1154
1155 minmax[i] = 23 + gain[i];
1156 }
1157
1158 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1159 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1160 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1161 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1162
1163 if (nphy->hang_avoid)
1164 b43_nphy_stay_in_carrier_search(dev, 0);
1165}
1166
1167
1168static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1169{
1170 struct b43_phy_n *nphy = dev->phy.n;
1171 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
1172
1173
1174 u8 i, j;
1175 u8 code;
1176 u16 tmp;
1177 u8 rfseq_events[3] = { 6, 8, 7 };
1178 u8 rfseq_delays[3] = { 10, 30, 1 };
1179
1180
1181 bool ghz5;
1182 bool ext_lna;
1183 u16 rssi_gain;
1184 struct nphy_gain_ctl_workaround_entry *e;
1185 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1186 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1187
1188 if (dev->phy.rev >= 3) {
1189
1190 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1191 & B43_NPHY_BANDCTL_5GHZ;
1192 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1193 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1194 if (ghz5 && dev->phy.rev >= 5)
1195 rssi_gain = 0x90;
1196 else
1197 rssi_gain = 0x50;
1198
1199 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1200
1201
1202 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1203 B43_NPHY_C1_CGAINI_CL2DETECT);
1204 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1205 B43_NPHY_C2_CGAINI_CL2DETECT);
1206
1207 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1208 0x17);
1209 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1210 0x17);
1211 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1212 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1213 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1214 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1215 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1216 rssi_gain);
1217 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1218 rssi_gain);
1219 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1220 0x17);
1221 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1222 0x17);
1223 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1224 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1225
1226 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1227 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1228 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1229 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1230 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1231 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1232 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1233 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1234 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1235 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1236 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1237 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1238
1239 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1240 b43_phy_write(dev, 0x2A7, e->init_gain);
1241 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1242 e->rfseq_init);
1243 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1244
1245
1246 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1247 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1248 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1249 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1250 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1251 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1252
1253 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1254 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1255 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1256 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1257 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1258 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1259 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1260 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1261 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1262 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1263 } else {
1264
1265 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1266 B43_NPHY_C1_CGAINI_CL2DETECT);
1267 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1268 B43_NPHY_C2_CGAINI_CL2DETECT);
1269
1270
1271 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1272 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1273
1274 if (!dev->phy.is_40mhz) {
1275
1276 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1277 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1278 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1279 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1280 }
1281
1282
1283 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1284 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1285 21);
1286 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1287 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1288 21);
1289
1290 if (!dev->phy.is_40mhz) {
1291 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1292 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1293 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1294 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1295 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1296 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1297 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1298 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1299 }
1300
1301 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1302
1303 if (nphy->gain_boost) {
1304 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1305 dev->phy.is_40mhz)
1306 code = 4;
1307 else
1308 code = 5;
1309 } else {
1310 code = dev->phy.is_40mhz ? 6 : 7;
1311 }
1312
1313
1314 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1315 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1316 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1317 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1318 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1319 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1320
1321 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1322
1323 for (i = 0; i < 4; i++)
1324 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1325 (code << 8 | 0x7C));
1326
1327 b43_nphy_adjust_lna_gain_table(dev);
1328
1329 if (nphy->elna_gain_config) {
1330 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1331 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1332 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1333 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1334 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1335
1336 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1337 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1338 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1339 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1340 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1341
1342 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1343
1344 for (i = 0; i < 4; i++)
1345 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1346 (code << 8 | 0x74));
1347 }
1348
1349 if (dev->phy.rev == 2) {
1350 for (i = 0; i < 4; i++) {
1351 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1352 (0x0400 * i) + 0x0020);
1353 for (j = 0; j < 21; j++) {
1354 tmp = j * (i < 2 ? 3 : 1);
1355 b43_phy_write(dev,
1356 B43_NPHY_TABLE_DATALO, tmp);
1357 }
1358 }
1359 }
1360
1361 b43_nphy_set_rf_sequence(dev, 5,
1362 rfseq_events, rfseq_delays, 3);
1363 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1364 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1365 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1366
1367 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1368 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1369 0xFF80, 4);
1370 }
1371}
1372
1373
1374static void b43_nphy_workarounds(struct b43_wldev *dev)
1375{
1376 struct ssb_bus *bus = dev->dev->bus;
1377 struct b43_phy *phy = &dev->phy;
1378 struct b43_phy_n *nphy = phy->n;
1379
1380 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1381 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1382
1383 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1384 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1385
1386 u16 tmp16;
1387 u32 tmp32;
1388
1389 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1390 b43_nphy_classifier(dev, 1, 0);
1391 else
1392 b43_nphy_classifier(dev, 1, 1);
1393
1394 if (nphy->hang_avoid)
1395 b43_nphy_stay_in_carrier_search(dev, 1);
1396
1397 b43_phy_set(dev, B43_NPHY_IQFLIP,
1398 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1399
1400 if (dev->phy.rev >= 3) {
1401 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1402 tmp32 &= 0xffffff;
1403 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1404
1405 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1406 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1407 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1408 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1409 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1410 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1411
1412 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1413 b43_phy_write(dev, 0x2AE, 0x000C);
1414
1415
1416
1417 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1418 0x2 : 0x9C40;
1419 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1420
1421 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1422
1423 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1424 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1425
1426 b43_nphy_gain_ctrl_workarounds(dev);
1427
1428 b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
1429 b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
1430
1431
1432
1433 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1434 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1435 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1436 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1437 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1438 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1439 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1440 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1441 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1442 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1443
1444
1445
1446 if ((bus->sprom.boardflags2_lo & B43_BFL2_APLL_WAR &&
1447 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1448 (bus->sprom.boardflags2_lo & B43_BFL2_GPLL_WAR &&
1449 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1450 tmp32 = 0x00088888;
1451 else
1452 tmp32 = 0x88888888;
1453 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1454 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1455 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1456
1457 if (dev->phy.rev == 4 &&
1458 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1459 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1460 0x70);
1461 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1462 0x70);
1463 }
1464
1465 b43_phy_write(dev, 0x224, 0x039C);
1466 b43_phy_write(dev, 0x225, 0x0357);
1467 b43_phy_write(dev, 0x226, 0x0317);
1468 b43_phy_write(dev, 0x227, 0x02D7);
1469 b43_phy_write(dev, 0x228, 0x039C);
1470 b43_phy_write(dev, 0x229, 0x0357);
1471 b43_phy_write(dev, 0x22A, 0x0317);
1472 b43_phy_write(dev, 0x22B, 0x02D7);
1473 b43_phy_write(dev, 0x22C, 0x039C);
1474 b43_phy_write(dev, 0x22D, 0x0357);
1475 b43_phy_write(dev, 0x22E, 0x0317);
1476 b43_phy_write(dev, 0x22F, 0x02D7);
1477 } else {
1478 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1479 nphy->band5g_pwrgain) {
1480 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1481 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1482 } else {
1483 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1484 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1485 }
1486
1487 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1488 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1489 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1490 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1491
1492 if (dev->phy.rev < 2) {
1493 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1494 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1495 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1496 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1497 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1498 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1499 }
1500
1501 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1502 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1503 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1504 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1505
1506 if (bus->sprom.boardflags2_lo & 0x100 &&
1507 bus->boardinfo.type == 0x8B) {
1508 delays1[0] = 0x1;
1509 delays1[5] = 0x14;
1510 }
1511 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1512 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1513
1514 b43_nphy_gain_ctrl_workarounds(dev);
1515
1516 if (dev->phy.rev < 2) {
1517 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1518 b43_hf_write(dev, b43_hf_read(dev) |
1519 B43_HF_MLADVW);
1520 } else if (dev->phy.rev == 2) {
1521 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1522 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1523 }
1524
1525 if (dev->phy.rev < 2)
1526 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1527 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1528
1529
1530 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1531 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1532 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1533 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1534 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1535 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1536
1537 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1538 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1539 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1540 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1541 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1542
1543 if (dev->phy.rev == 2)
1544 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1545 B43_NPHY_FINERX2_CGC_DECGC);
1546 }
1547
1548 if (nphy->hang_avoid)
1549 b43_nphy_stay_in_carrier_search(dev, 0);
1550}
1551
1552
1553static int b43_nphy_load_samples(struct b43_wldev *dev,
1554 struct b43_c32 *samples, u16 len) {
1555 struct b43_phy_n *nphy = dev->phy.n;
1556 u16 i;
1557 u32 *data;
1558
1559 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1560 if (!data) {
1561 b43err(dev->wl, "allocation for samples loading failed\n");
1562 return -ENOMEM;
1563 }
1564 if (nphy->hang_avoid)
1565 b43_nphy_stay_in_carrier_search(dev, 1);
1566
1567 for (i = 0; i < len; i++) {
1568 data[i] = (samples[i].i & 0x3FF << 10);
1569 data[i] |= samples[i].q & 0x3FF;
1570 }
1571 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1572
1573 kfree(data);
1574 if (nphy->hang_avoid)
1575 b43_nphy_stay_in_carrier_search(dev, 0);
1576 return 0;
1577}
1578
1579
1580static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1581 bool test)
1582{
1583 int i;
1584 u16 bw, len, rot, angle;
1585 struct b43_c32 *samples;
1586
1587
1588 bw = (dev->phy.is_40mhz) ? 40 : 20;
1589 len = bw << 3;
1590
1591 if (test) {
1592 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1593 bw = 82;
1594 else
1595 bw = 80;
1596
1597 if (dev->phy.is_40mhz)
1598 bw <<= 1;
1599
1600 len = bw << 1;
1601 }
1602
1603 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1604 if (!samples) {
1605 b43err(dev->wl, "allocation for samples generation failed\n");
1606 return 0;
1607 }
1608 rot = (((freq * 36) / bw) << 16) / 100;
1609 angle = 0;
1610
1611 for (i = 0; i < len; i++) {
1612 samples[i] = b43_cordic(angle);
1613 angle += rot;
1614 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1615 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1616 }
1617
1618 i = b43_nphy_load_samples(dev, samples, len);
1619 kfree(samples);
1620 return (i < 0) ? 0 : len;
1621}
1622
1623
1624static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1625 u16 wait, bool iqmode, bool dac_test)
1626{
1627 struct b43_phy_n *nphy = dev->phy.n;
1628 int i;
1629 u16 seq_mode;
1630 u32 tmp;
1631
1632 if (nphy->hang_avoid)
1633 b43_nphy_stay_in_carrier_search(dev, true);
1634
1635 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1636 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1637 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1638 }
1639
1640 if (!dev->phy.is_40mhz)
1641 tmp = 0x6464;
1642 else
1643 tmp = 0x4747;
1644 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1645
1646 if (nphy->hang_avoid)
1647 b43_nphy_stay_in_carrier_search(dev, false);
1648
1649 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1650
1651 if (loops != 0xFFFF)
1652 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1653 else
1654 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1655
1656 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1657
1658 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1659
1660 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1661 if (iqmode) {
1662 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1663 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1664 } else {
1665 if (dac_test)
1666 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1667 else
1668 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1669 }
1670 for (i = 0; i < 100; i++) {
1671 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1672 i = 0;
1673 break;
1674 }
1675 udelay(10);
1676 }
1677 if (i)
1678 b43err(dev->wl, "run samples timeout\n");
1679
1680 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1681}
1682
1683
1684
1685
1686
1687static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1688 bool iqmode, bool dac_test)
1689{
1690 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1691 if (samp == 0)
1692 return -1;
1693 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1694 return 0;
1695}
1696
1697
1698static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1699{
1700 struct b43_phy_n *nphy = dev->phy.n;
1701 int i, j;
1702 u32 tmp;
1703 u32 cur_real, cur_imag, real_part, imag_part;
1704
1705 u16 buffer[7];
1706
1707 if (nphy->hang_avoid)
1708 b43_nphy_stay_in_carrier_search(dev, true);
1709
1710 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1711
1712 for (i = 0; i < 2; i++) {
1713 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1714 (buffer[i * 2 + 1] & 0x3FF);
1715 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1716 (((i + 26) << 10) | 320));
1717 for (j = 0; j < 128; j++) {
1718 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1719 ((tmp >> 16) & 0xFFFF));
1720 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1721 (tmp & 0xFFFF));
1722 }
1723 }
1724
1725 for (i = 0; i < 2; i++) {
1726 tmp = buffer[5 + i];
1727 real_part = (tmp >> 8) & 0xFF;
1728 imag_part = (tmp & 0xFF);
1729 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1730 (((i + 26) << 10) | 448));
1731
1732 if (dev->phy.rev >= 3) {
1733 cur_real = real_part;
1734 cur_imag = imag_part;
1735 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1736 }
1737
1738 for (j = 0; j < 128; j++) {
1739 if (dev->phy.rev < 3) {
1740 cur_real = (real_part * loscale[j] + 128) >> 8;
1741 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1742 tmp = ((cur_real & 0xFF) << 8) |
1743 (cur_imag & 0xFF);
1744 }
1745 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1746 ((tmp >> 16) & 0xFFFF));
1747 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1748 (tmp & 0xFFFF));
1749 }
1750 }
1751
1752 if (dev->phy.rev >= 3) {
1753 b43_shm_write16(dev, B43_SHM_SHARED,
1754 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1755 b43_shm_write16(dev, B43_SHM_SHARED,
1756 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1757 }
1758
1759 if (nphy->hang_avoid)
1760 b43_nphy_stay_in_carrier_search(dev, false);
1761}
1762
1763
1764static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1765 u8 *events, u8 *delays, u8 length)
1766{
1767 struct b43_phy_n *nphy = dev->phy.n;
1768 u8 i;
1769 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1770 u16 offset1 = cmd << 4;
1771 u16 offset2 = offset1 + 0x80;
1772
1773 if (nphy->hang_avoid)
1774 b43_nphy_stay_in_carrier_search(dev, true);
1775
1776 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1777 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1778
1779 for (i = length; i < 16; i++) {
1780 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1781 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1782 }
1783
1784 if (nphy->hang_avoid)
1785 b43_nphy_stay_in_carrier_search(dev, false);
1786}
1787
1788
1789static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1790 enum b43_nphy_rf_sequence seq)
1791{
1792 static const u16 trigger[] = {
1793 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1794 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1795 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1796 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1797 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1798 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1799 };
1800 int i;
1801 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1802
1803 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1804
1805 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1806 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1807 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1808 for (i = 0; i < 200; i++) {
1809 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1810 goto ok;
1811 msleep(1);
1812 }
1813 b43err(dev->wl, "RF sequence status timeout\n");
1814ok:
1815 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1816}
1817
1818
1819static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1820 u16 value, u8 core, bool off)
1821{
1822 int i;
1823 u8 index = fls(field);
1824 u8 addr, en_addr, val_addr;
1825
1826 B43_WARN_ON(field & (~(1 << (index - 1))));
1827
1828 if (dev->phy.rev >= 3) {
1829 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1830 for (i = 0; i < 2; i++) {
1831 if (index == 0 || index == 16) {
1832 b43err(dev->wl,
1833 "Unsupported RF Ctrl Override call\n");
1834 return;
1835 }
1836
1837 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1838 en_addr = B43_PHY_N((i == 0) ?
1839 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1840 val_addr = B43_PHY_N((i == 0) ?
1841 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1842
1843 if (off) {
1844 b43_phy_mask(dev, en_addr, ~(field));
1845 b43_phy_mask(dev, val_addr,
1846 ~(rf_ctrl->val_mask));
1847 } else {
1848 if (core == 0 || ((1 << core) & i) != 0) {
1849 b43_phy_set(dev, en_addr, field);
1850 b43_phy_maskset(dev, val_addr,
1851 ~(rf_ctrl->val_mask),
1852 (value << rf_ctrl->val_shift));
1853 }
1854 }
1855 }
1856 } else {
1857 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1858 if (off) {
1859 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1860 value = 0;
1861 } else {
1862 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1863 }
1864
1865 for (i = 0; i < 2; i++) {
1866 if (index <= 1 || index == 16) {
1867 b43err(dev->wl,
1868 "Unsupported RF Ctrl Override call\n");
1869 return;
1870 }
1871
1872 if (index == 2 || index == 10 ||
1873 (index >= 13 && index <= 15)) {
1874 core = 1;
1875 }
1876
1877 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1878 addr = B43_PHY_N((i == 0) ?
1879 rf_ctrl->addr0 : rf_ctrl->addr1);
1880
1881 if ((core & (1 << i)) != 0)
1882 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1883 (value << rf_ctrl->shift));
1884
1885 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1886 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1887 B43_NPHY_RFCTL_CMD_START);
1888 udelay(1);
1889 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1890 }
1891 }
1892}
1893
1894
1895static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1896 u16 value, u8 core)
1897{
1898 u8 i, j;
1899 u16 reg, tmp, val;
1900
1901 B43_WARN_ON(dev->phy.rev < 3);
1902 B43_WARN_ON(field > 4);
1903
1904 for (i = 0; i < 2; i++) {
1905 if ((core == 1 && i == 1) || (core == 2 && !i))
1906 continue;
1907
1908 reg = (i == 0) ?
1909 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1910 b43_phy_mask(dev, reg, 0xFBFF);
1911
1912 switch (field) {
1913 case 0:
1914 b43_phy_write(dev, reg, 0);
1915 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1916 break;
1917 case 1:
1918 if (!i) {
1919 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1920 0xFC3F, (value << 6));
1921 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1922 0xFFFE, 1);
1923 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1924 B43_NPHY_RFCTL_CMD_START);
1925 for (j = 0; j < 100; j++) {
1926 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1927 j = 0;
1928 break;
1929 }
1930 udelay(10);
1931 }
1932 if (j)
1933 b43err(dev->wl,
1934 "intc override timeout\n");
1935 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1936 0xFFFE);
1937 } else {
1938 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1939 0xFC3F, (value << 6));
1940 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1941 0xFFFE, 1);
1942 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1943 B43_NPHY_RFCTL_CMD_RXTX);
1944 for (j = 0; j < 100; j++) {
1945 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1946 j = 0;
1947 break;
1948 }
1949 udelay(10);
1950 }
1951 if (j)
1952 b43err(dev->wl,
1953 "intc override timeout\n");
1954 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1955 0xFFFE);
1956 }
1957 break;
1958 case 2:
1959 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1960 tmp = 0x0020;
1961 val = value << 5;
1962 } else {
1963 tmp = 0x0010;
1964 val = value << 4;
1965 }
1966 b43_phy_maskset(dev, reg, ~tmp, val);
1967 break;
1968 case 3:
1969 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1970 tmp = 0x0001;
1971 val = value;
1972 } else {
1973 tmp = 0x0004;
1974 val = value << 2;
1975 }
1976 b43_phy_maskset(dev, reg, ~tmp, val);
1977 break;
1978 case 4:
1979 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1980 tmp = 0x0002;
1981 val = value << 1;
1982 } else {
1983 tmp = 0x0008;
1984 val = value << 3;
1985 }
1986 b43_phy_maskset(dev, reg, ~tmp, val);
1987 break;
1988 }
1989 }
1990}
1991
1992
1993static void b43_nphy_bphy_init(struct b43_wldev *dev)
1994{
1995 unsigned int i;
1996 u16 val;
1997
1998 val = 0x1E1F;
1999 for (i = 0; i < 16; i++) {
2000 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2001 val -= 0x202;
2002 }
2003 val = 0x3E3F;
2004 for (i = 0; i < 16; i++) {
2005 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
2006 val -= 0x202;
2007 }
2008 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2009}
2010
2011
2012static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
2013 s8 offset, u8 core, u8 rail,
2014 enum b43_nphy_rssi_type type)
2015{
2016 u16 tmp;
2017 bool core1or5 = (core == 1) || (core == 5);
2018 bool core2or5 = (core == 2) || (core == 5);
2019
2020 offset = clamp_val(offset, -32, 31);
2021 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2022
2023 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2024 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
2025 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2026 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
2027 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2028 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
2029 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2030 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
2031
2032 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2033 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
2034 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2035 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
2036 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2037 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
2038 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2039 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
2040
2041 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2042 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
2043 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2044 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
2045 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2046 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
2047 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2048 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
2049
2050 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2051 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
2052 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2053 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
2054 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2055 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
2056 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2057 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
2058
2059 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2060 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
2061 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2062 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
2063 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2064 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
2065 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2066 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
2067
2068 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
2069 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
2070 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
2071 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
2072
2073 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2074 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
2075 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2076 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2077}
2078
2079static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2080{
2081 u16 val;
2082
2083 if (type < 3)
2084 val = 0;
2085 else if (type == 6)
2086 val = 1;
2087 else if (type == 3)
2088 val = 2;
2089 else
2090 val = 3;
2091
2092 val = (val << 12) | (val << 14);
2093 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2094 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
2095
2096 if (type < 3) {
2097 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2098 (type + 1) << 4);
2099 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2100 (type + 1) << 4);
2101 }
2102
2103 if (code == 0) {
2104 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
2105 if (type < 3) {
2106 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2107 ~(B43_NPHY_RFCTL_CMD_RXEN |
2108 B43_NPHY_RFCTL_CMD_CORESEL));
2109 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2110 ~(0x1 << 12 |
2111 0x1 << 5 |
2112 0x1 << 1 |
2113 0x1));
2114 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2115 ~B43_NPHY_RFCTL_CMD_START);
2116 udelay(20);
2117 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2118 }
2119 } else {
2120 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
2121 if (type < 3) {
2122 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
2123 ~(B43_NPHY_RFCTL_CMD_RXEN |
2124 B43_NPHY_RFCTL_CMD_CORESEL),
2125 (B43_NPHY_RFCTL_CMD_RXEN |
2126 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2127 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2128 (0x1 << 12 |
2129 0x1 << 5 |
2130 0x1 << 1 |
2131 0x1));
2132 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2133 B43_NPHY_RFCTL_CMD_START);
2134 udelay(20);
2135 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2136 }
2137 }
2138}
2139
2140static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2141{
2142 struct b43_phy_n *nphy = dev->phy.n;
2143 u8 i;
2144 u16 reg, val;
2145
2146 if (code == 0) {
2147 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2148 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2149 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2150 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2151 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2152 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2153 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2154 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2155 } else {
2156 for (i = 0; i < 2; i++) {
2157 if ((code == 1 && i == 1) || (code == 2 && !i))
2158 continue;
2159
2160 reg = (i == 0) ?
2161 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2162 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2163
2164 if (type < 3) {
2165 reg = (i == 0) ?
2166 B43_NPHY_AFECTL_C1 :
2167 B43_NPHY_AFECTL_C2;
2168 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2169
2170 reg = (i == 0) ?
2171 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2172 B43_NPHY_RFCTL_LUT_TRSW_UP2;
2173 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2174
2175 if (type == 0)
2176 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2177 else if (type == 1)
2178 val = 16;
2179 else
2180 val = 32;
2181 b43_phy_set(dev, reg, val);
2182
2183 reg = (i == 0) ?
2184 B43_NPHY_TXF_40CO_B1S0 :
2185 B43_NPHY_TXF_40CO_B32S1;
2186 b43_phy_set(dev, reg, 0x0020);
2187 } else {
2188 if (type == 6)
2189 val = 0x0100;
2190 else if (type == 3)
2191 val = 0x0200;
2192 else
2193 val = 0x0300;
2194
2195 reg = (i == 0) ?
2196 B43_NPHY_AFECTL_C1 :
2197 B43_NPHY_AFECTL_C2;
2198
2199 b43_phy_maskset(dev, reg, 0xFCFF, val);
2200 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2201
2202 if (type != 3 && type != 6) {
2203 enum ieee80211_band band =
2204 b43_current_band(dev->wl);
2205
2206 if ((nphy->ipa2g_on &&
2207 band == IEEE80211_BAND_2GHZ) ||
2208 (nphy->ipa5g_on &&
2209 band == IEEE80211_BAND_5GHZ))
2210 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2211 else
2212 val = 0x11;
2213 reg = (i == 0) ? 0x2000 : 0x3000;
2214 reg |= B2055_PADDRV;
2215 b43_radio_write16(dev, reg, val);
2216
2217 reg = (i == 0) ?
2218 B43_NPHY_AFECTL_OVER1 :
2219 B43_NPHY_AFECTL_OVER;
2220 b43_phy_set(dev, reg, 0x0200);
2221 }
2222 }
2223 }
2224 }
2225}
2226
2227
2228static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2229{
2230 if (dev->phy.rev >= 3)
2231 b43_nphy_rev3_rssi_select(dev, code, type);
2232 else
2233 b43_nphy_rev2_rssi_select(dev, code, type);
2234}
2235
2236
2237static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2238{
2239 int i;
2240 for (i = 0; i < 2; i++) {
2241 if (type == 2) {
2242 if (i == 0) {
2243 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2244 0xFC, buf[0]);
2245 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2246 0xFC, buf[1]);
2247 } else {
2248 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2249 0xFC, buf[2 * i]);
2250 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2251 0xFC, buf[2 * i + 1]);
2252 }
2253 } else {
2254 if (i == 0)
2255 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2256 0xF3, buf[0] << 2);
2257 else
2258 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2259 0xF3, buf[2 * i + 1] << 2);
2260 }
2261 }
2262}
2263
2264
2265static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2266 u8 nsamp)
2267{
2268 int i;
2269 int out;
2270 u16 save_regs_phy[9];
2271 u16 s[2];
2272
2273 if (dev->phy.rev >= 3) {
2274 save_regs_phy[0] = b43_phy_read(dev,
2275 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2276 save_regs_phy[1] = b43_phy_read(dev,
2277 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2278 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2279 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2280 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2281 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2282 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2283 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2284 } else {
2285 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2286 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2287 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2288 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2289 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2290 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2291 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2292 }
2293
2294 b43_nphy_rssi_select(dev, 5, type);
2295
2296 if (dev->phy.rev < 2) {
2297 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2298 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2299 }
2300
2301 for (i = 0; i < 4; i++)
2302 buf[i] = 0;
2303
2304 for (i = 0; i < nsamp; i++) {
2305 if (dev->phy.rev < 2) {
2306 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2307 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2308 } else {
2309 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2310 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2311 }
2312
2313 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2314 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2315 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2316 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2317 }
2318 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2319 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2320
2321 if (dev->phy.rev < 2)
2322 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2323
2324 if (dev->phy.rev >= 3) {
2325 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2326 save_regs_phy[0]);
2327 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2328 save_regs_phy[1]);
2329 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2330 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2331 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2332 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2333 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2334 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2335 } else {
2336 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2337 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2338 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2339 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2340 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2341 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2342 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2343 }
2344
2345 return out;
2346}
2347
2348
2349static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2350{
2351 int i, j;
2352 u8 state[4];
2353 u8 code, val;
2354 u16 class, override;
2355 u8 regs_save_radio[2];
2356 u16 regs_save_phy[2];
2357
2358 s8 offset[4];
2359 u8 core;
2360 u8 rail;
2361
2362 u16 clip_state[2];
2363 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2364 s32 results_min[4] = { };
2365 u8 vcm_final[4] = { };
2366 s32 results[4][4] = { };
2367 s32 miniq[4][2] = { };
2368
2369 if (type == 2) {
2370 code = 0;
2371 val = 6;
2372 } else if (type < 2) {
2373 code = 25;
2374 val = 4;
2375 } else {
2376 B43_WARN_ON(1);
2377 return;
2378 }
2379
2380 class = b43_nphy_classifier(dev, 0, 0);
2381 b43_nphy_classifier(dev, 7, 4);
2382 b43_nphy_read_clip_detection(dev, clip_state);
2383 b43_nphy_write_clip_detection(dev, clip_off);
2384
2385 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2386 override = 0x140;
2387 else
2388 override = 0x110;
2389
2390 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2391 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2392 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2393 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2394
2395 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2396 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2397 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2398 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2399
2400 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2401 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2402 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2403 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2404 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2405 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2406
2407 b43_nphy_rssi_select(dev, 5, type);
2408 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2409 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2410
2411 for (i = 0; i < 4; i++) {
2412 u8 tmp[4];
2413 for (j = 0; j < 4; j++)
2414 tmp[j] = i;
2415 if (type != 1)
2416 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2417 b43_nphy_poll_rssi(dev, type, results[i], 8);
2418 if (type < 2)
2419 for (j = 0; j < 2; j++)
2420 miniq[i][j] = min(results[i][2 * j],
2421 results[i][2 * j + 1]);
2422 }
2423
2424 for (i = 0; i < 4; i++) {
2425 s32 mind = 40;
2426 u8 minvcm = 0;
2427 s32 minpoll = 249;
2428 s32 curr;
2429 for (j = 0; j < 4; j++) {
2430 if (type == 2)
2431 curr = abs(results[j][i]);
2432 else
2433 curr = abs(miniq[j][i / 2] - code * 8);
2434
2435 if (curr < mind) {
2436 mind = curr;
2437 minvcm = j;
2438 }
2439
2440 if (results[j][i] < minpoll)
2441 minpoll = results[j][i];
2442 }
2443 results_min[i] = minpoll;
2444 vcm_final[i] = minvcm;
2445 }
2446
2447 if (type != 1)
2448 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2449
2450 for (i = 0; i < 4; i++) {
2451 offset[i] = (code * 8) - results[vcm_final[i]][i];
2452
2453 if (offset[i] < 0)
2454 offset[i] = -((abs(offset[i]) + 4) / 8);
2455 else
2456 offset[i] = (offset[i] + 4) / 8;
2457
2458 if (results_min[i] == 248)
2459 offset[i] = code - 32;
2460
2461 core = (i / 2) ? 2 : 1;
2462 rail = (i % 2) ? 1 : 0;
2463
2464 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2465 type);
2466 }
2467
2468 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2469 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2470
2471 switch (state[2]) {
2472 case 1:
2473 b43_nphy_rssi_select(dev, 1, 2);
2474 break;
2475 case 4:
2476 b43_nphy_rssi_select(dev, 1, 0);
2477 break;
2478 case 2:
2479 b43_nphy_rssi_select(dev, 1, 1);
2480 break;
2481 default:
2482 b43_nphy_rssi_select(dev, 1, 1);
2483 break;
2484 }
2485
2486 switch (state[3]) {
2487 case 1:
2488 b43_nphy_rssi_select(dev, 2, 2);
2489 break;
2490 case 4:
2491 b43_nphy_rssi_select(dev, 2, 0);
2492 break;
2493 default:
2494 b43_nphy_rssi_select(dev, 2, 1);
2495 break;
2496 }
2497
2498 b43_nphy_rssi_select(dev, 0, type);
2499
2500 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2501 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2502 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2503 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2504
2505 b43_nphy_classifier(dev, 7, class);
2506 b43_nphy_write_clip_detection(dev, clip_state);
2507
2508
2509 b43_nphy_reset_cca(dev);
2510}
2511
2512
2513static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2514{
2515
2516}
2517
2518
2519
2520
2521
2522static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2523{
2524 if (dev->phy.rev >= 3) {
2525 b43_nphy_rev3_rssi_cal(dev);
2526 } else {
2527 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2528 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2529 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2530 }
2531}
2532
2533
2534
2535
2536
2537static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2538{
2539 struct b43_phy_n *nphy = dev->phy.n;
2540
2541 u16 *rssical_radio_regs = NULL;
2542 u16 *rssical_phy_regs = NULL;
2543
2544 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2545 if (!nphy->rssical_chanspec_2G.center_freq)
2546 return;
2547 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2548 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2549 } else {
2550 if (!nphy->rssical_chanspec_5G.center_freq)
2551 return;
2552 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2553 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2554 }
2555
2556
2557 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2558 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2559
2560 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2561 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2562 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2563 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2564
2565 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2566 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2567 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2568 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2569
2570 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2571 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2572 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2573 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2574}
2575
2576
2577static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2578{
2579 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2580 if (dev->phy.rev >= 6) {
2581
2582
2583 return txpwrctrl_tx_gain_ipa_rev6;
2584 } else if (dev->phy.rev >= 5) {
2585 return txpwrctrl_tx_gain_ipa_rev5;
2586 } else {
2587 return txpwrctrl_tx_gain_ipa;
2588 }
2589 } else {
2590 return txpwrctrl_tx_gain_ipa_5g;
2591 }
2592}
2593
2594
2595static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2596{
2597 struct b43_phy_n *nphy = dev->phy.n;
2598 u16 *save = nphy->tx_rx_cal_radio_saveregs;
2599 u16 tmp;
2600 u8 offset, i;
2601
2602 if (dev->phy.rev >= 3) {
2603 for (i = 0; i < 2; i++) {
2604 tmp = (i == 0) ? 0x2000 : 0x3000;
2605 offset = i * 11;
2606
2607 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2608 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2609 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2610 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2611 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2612 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2613 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2614 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2615 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2616 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2617 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2618
2619 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2620 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2621 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2622 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2623 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2624 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2625 if (nphy->ipa5g_on) {
2626 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2627 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2628 } else {
2629 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2630 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2631 }
2632 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2633 } else {
2634 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2635 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2636 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2637 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2638 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2639 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2640 if (nphy->ipa2g_on) {
2641 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2642 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2643 (dev->phy.rev < 5) ? 0x11 : 0x01);
2644 } else {
2645 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2646 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2647 }
2648 }
2649 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2650 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2651 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2652 }
2653 } else {
2654 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2655 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2656
2657 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2658 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2659
2660 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2661 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2662
2663 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2664 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2665
2666 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2667 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2668
2669 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2670 B43_NPHY_BANDCTL_5GHZ)) {
2671 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2672 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2673 } else {
2674 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2675 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2676 }
2677
2678 if (dev->phy.rev < 2) {
2679 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2680 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2681 } else {
2682 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2683 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2684 }
2685 }
2686}
2687
2688
2689static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2690 struct nphy_txgains target,
2691 struct nphy_iqcal_params *params)
2692{
2693 int i, j, indx;
2694 u16 gain;
2695
2696 if (dev->phy.rev >= 3) {
2697 params->txgm = target.txgm[core];
2698 params->pga = target.pga[core];
2699 params->pad = target.pad[core];
2700 params->ipa = target.ipa[core];
2701 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2702 (params->pad << 4) | (params->ipa);
2703 for (j = 0; j < 5; j++)
2704 params->ncorr[j] = 0x79;
2705 } else {
2706 gain = (target.pad[core]) | (target.pga[core] << 4) |
2707 (target.txgm[core] << 8);
2708
2709 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2710 1 : 0;
2711 for (i = 0; i < 9; i++)
2712 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2713 break;
2714 i = min(i, 8);
2715
2716 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2717 params->pga = tbl_iqcal_gainparams[indx][i][2];
2718 params->pad = tbl_iqcal_gainparams[indx][i][3];
2719 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2720 (params->pad << 2);
2721 for (j = 0; j < 4; j++)
2722 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2723 }
2724}
2725
2726
2727static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2728{
2729 struct b43_phy_n *nphy = dev->phy.n;
2730 int i;
2731 u16 scale, entry;
2732
2733 u16 tmp = nphy->txcal_bbmult;
2734 if (core == 0)
2735 tmp >>= 8;
2736 tmp &= 0xff;
2737
2738 for (i = 0; i < 18; i++) {
2739 scale = (ladder_lo[i].percent * tmp) / 100;
2740 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2741 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2742
2743 scale = (ladder_iq[i].percent * tmp) / 100;
2744 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2745 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2746 }
2747}
2748
2749
2750static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2751{
2752 int i;
2753 for (i = 0; i < 15; i++)
2754 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2755 tbl_tx_filter_coef_rev4[2][i]);
2756}
2757
2758
2759static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2760{
2761 int i, j;
2762
2763 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
2764
2765 for (i = 0; i < 3; i++)
2766 for (j = 0; j < 15; j++)
2767 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2768 tbl_tx_filter_coef_rev4[i][j]);
2769
2770 if (dev->phy.is_40mhz) {
2771 for (j = 0; j < 15; j++)
2772 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2773 tbl_tx_filter_coef_rev4[3][j]);
2774 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2775 for (j = 0; j < 15; j++)
2776 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2777 tbl_tx_filter_coef_rev4[5][j]);
2778 }
2779
2780 if (dev->phy.channel == 14)
2781 for (j = 0; j < 15; j++)
2782 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2783 tbl_tx_filter_coef_rev4[6][j]);
2784}
2785
2786
2787static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2788{
2789 struct b43_phy_n *nphy = dev->phy.n;
2790
2791 u16 curr_gain[2];
2792 struct nphy_txgains target;
2793 const u32 *table = NULL;
2794
2795 if (!nphy->txpwrctrl) {
2796 int i;
2797
2798 if (nphy->hang_avoid)
2799 b43_nphy_stay_in_carrier_search(dev, true);
2800 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2801 if (nphy->hang_avoid)
2802 b43_nphy_stay_in_carrier_search(dev, false);
2803
2804 for (i = 0; i < 2; ++i) {
2805 if (dev->phy.rev >= 3) {
2806 target.ipa[i] = curr_gain[i] & 0x000F;
2807 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2808 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2809 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2810 } else {
2811 target.ipa[i] = curr_gain[i] & 0x0003;
2812 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2813 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2814 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2815 }
2816 }
2817 } else {
2818 int i;
2819 u16 index[2];
2820 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2821 B43_NPHY_TXPCTL_STAT_BIDX) >>
2822 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2823 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2824 B43_NPHY_TXPCTL_STAT_BIDX) >>
2825 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2826
2827 for (i = 0; i < 2; ++i) {
2828 if (dev->phy.rev >= 3) {
2829 enum ieee80211_band band =
2830 b43_current_band(dev->wl);
2831
2832 if ((nphy->ipa2g_on &&
2833 band == IEEE80211_BAND_2GHZ) ||
2834 (nphy->ipa5g_on &&
2835 band == IEEE80211_BAND_5GHZ)) {
2836 table = b43_nphy_get_ipa_gain_table(dev);
2837 } else {
2838 if (band == IEEE80211_BAND_5GHZ) {
2839 if (dev->phy.rev == 3)
2840 table = b43_ntab_tx_gain_rev3_5ghz;
2841 else if (dev->phy.rev == 4)
2842 table = b43_ntab_tx_gain_rev4_5ghz;
2843 else
2844 table = b43_ntab_tx_gain_rev5plus_5ghz;
2845 } else {
2846 table = b43_ntab_tx_gain_rev3plus_2ghz;
2847 }
2848 }
2849
2850 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2851 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2852 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2853 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2854 } else {
2855 table = b43_ntab_tx_gain_rev0_1_2;
2856
2857 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2858 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2859 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2860 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2861 }
2862 }
2863 }
2864
2865 return target;
2866}
2867
2868
2869static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2870{
2871 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2872
2873 if (dev->phy.rev >= 3) {
2874 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2875 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2876 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2877 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2878 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2879 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2880 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2881 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2882 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2883 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2884 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2885 b43_nphy_reset_cca(dev);
2886 } else {
2887 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2888 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2889 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2890 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2891 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2892 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2893 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2894 }
2895}
2896
2897
2898static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2899{
2900 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2901 u16 tmp;
2902
2903 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2904 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2905 if (dev->phy.rev >= 3) {
2906 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2907 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2908
2909 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2910 regs[2] = tmp;
2911 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2912
2913 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2914 regs[3] = tmp;
2915 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2916
2917 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2918 b43_phy_mask(dev, B43_NPHY_BBCFG,
2919 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2920
2921 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2922 regs[5] = tmp;
2923 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2924
2925 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2926 regs[6] = tmp;
2927 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2928 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2929 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2930
2931 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2932 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2933 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2934
2935 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2936 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2937 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2938 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2939 } else {
2940 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2941 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2942 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2943 regs[2] = tmp;
2944 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2945 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2946 regs[3] = tmp;
2947 tmp |= 0x2000;
2948 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2949 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2950 regs[4] = tmp;
2951 tmp |= 0x2000;
2952 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2953 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2954 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2955 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2956 tmp = 0x0180;
2957 else
2958 tmp = 0x0120;
2959 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2960 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2961 }
2962}
2963
2964
2965static void b43_nphy_save_cal(struct b43_wldev *dev)
2966{
2967 struct b43_phy_n *nphy = dev->phy.n;
2968
2969 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2970 u16 *txcal_radio_regs = NULL;
2971 struct b43_chanspec *iqcal_chanspec;
2972 u16 *table = NULL;
2973
2974 if (nphy->hang_avoid)
2975 b43_nphy_stay_in_carrier_search(dev, 1);
2976
2977 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2978 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2979 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2980 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2981 table = nphy->cal_cache.txcal_coeffs_2G;
2982 } else {
2983 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2984 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2985 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2986 table = nphy->cal_cache.txcal_coeffs_5G;
2987 }
2988
2989 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2990
2991 if (dev->phy.rev >= 3) {
2992 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2993 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2994 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2995 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2996 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2997 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2998 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2999 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3000 } else {
3001 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3002 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3003 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3004 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3005 }
3006 iqcal_chanspec->center_freq = dev->phy.channel_freq;
3007 iqcal_chanspec->channel_type = dev->phy.channel_type;
3008 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3009
3010 if (nphy->hang_avoid)
3011 b43_nphy_stay_in_carrier_search(dev, 0);
3012}
3013
3014
3015static void b43_nphy_restore_cal(struct b43_wldev *dev)
3016{
3017 struct b43_phy_n *nphy = dev->phy.n;
3018
3019 u16 coef[4];
3020 u16 *loft = NULL;
3021 u16 *table = NULL;
3022
3023 int i;
3024 u16 *txcal_radio_regs = NULL;
3025 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3026
3027 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3028 if (!nphy->iqcal_chanspec_2G.center_freq)
3029 return;
3030 table = nphy->cal_cache.txcal_coeffs_2G;
3031 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3032 } else {
3033 if (!nphy->iqcal_chanspec_5G.center_freq)
3034 return;
3035 table = nphy->cal_cache.txcal_coeffs_5G;
3036 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3037 }
3038
3039 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3040
3041 for (i = 0; i < 4; i++) {
3042 if (dev->phy.rev >= 3)
3043 table[i] = coef[i];
3044 else
3045 coef[i] = 0;
3046 }
3047
3048 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3049 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3050 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3051
3052 if (dev->phy.rev < 2)
3053 b43_nphy_tx_iq_workaround(dev);
3054
3055 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3056 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3057 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3058 } else {
3059 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3060 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3061 }
3062
3063
3064 if (dev->phy.rev >= 3) {
3065 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3066 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3067 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3068 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3069 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3070 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3071 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3072 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3073 } else {
3074 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3075 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3076 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3077 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3078 }
3079 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3080}
3081
3082
3083static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3084 struct nphy_txgains target,
3085 bool full, bool mphase)
3086{
3087 struct b43_phy_n *nphy = dev->phy.n;
3088 int i;
3089 int error = 0;
3090 int freq;
3091 bool avoid = false;
3092 u8 length;
3093 u16 tmp, core, type, count, max, numb, last, cmd;
3094 const u16 *table;
3095 bool phy6or5x;
3096
3097 u16 buffer[11];
3098 u16 diq_start = 0;
3099 u16 save[2];
3100 u16 gain[2];
3101 struct nphy_iqcal_params params[2];
3102 bool updated[2] = { };
3103
3104 b43_nphy_stay_in_carrier_search(dev, true);
3105
3106 if (dev->phy.rev >= 4) {
3107 avoid = nphy->hang_avoid;
3108 nphy->hang_avoid = 0;
3109 }
3110
3111 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3112
3113 for (i = 0; i < 2; i++) {
3114 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]);
3115 gain[i] = params[i].cal_gain;
3116 }
3117
3118 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3119
3120 b43_nphy_tx_cal_radio_setup(dev);
3121 b43_nphy_tx_cal_phy_setup(dev);
3122
3123 phy6or5x = dev->phy.rev >= 6 ||
3124 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3125 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3126 if (phy6or5x) {
3127 if (dev->phy.is_40mhz) {
3128 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3129 tbl_tx_iqlo_cal_loft_ladder_40);
3130 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3131 tbl_tx_iqlo_cal_iqimb_ladder_40);
3132 } else {
3133 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3134 tbl_tx_iqlo_cal_loft_ladder_20);
3135 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3136 tbl_tx_iqlo_cal_iqimb_ladder_20);
3137 }
3138 }
3139
3140 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3141
3142 if (!dev->phy.is_40mhz)
3143 freq = 2500;
3144 else
3145 freq = 5000;
3146
3147 if (nphy->mphase_cal_phase_id > 2)
3148 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3149 0xFFFF, 0, true, false);
3150 else
3151 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3152
3153 if (error == 0) {
3154 if (nphy->mphase_cal_phase_id > 2) {
3155 table = nphy->mphase_txcal_bestcoeffs;
3156 length = 11;
3157 if (dev->phy.rev < 3)
3158 length -= 2;
3159 } else {
3160 if (!full && nphy->txiqlocal_coeffsvalid) {
3161 table = nphy->txiqlocal_bestc;
3162 length = 11;
3163 if (dev->phy.rev < 3)
3164 length -= 2;
3165 } else {
3166 full = true;
3167 if (dev->phy.rev >= 3) {
3168 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3169 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3170 } else {
3171 table = tbl_tx_iqlo_cal_startcoefs;
3172 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3173 }
3174 }
3175 }
3176
3177 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3178
3179 if (full) {
3180 if (dev->phy.rev >= 3)
3181 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3182 else
3183 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3184 } else {
3185 if (dev->phy.rev >= 3)
3186 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3187 else
3188 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3189 }
3190
3191 if (mphase) {
3192 count = nphy->mphase_txcal_cmdidx;
3193 numb = min(max,
3194 (u16)(count + nphy->mphase_txcal_numcmds));
3195 } else {
3196 count = 0;
3197 numb = max;
3198 }
3199
3200 for (; count < numb; count++) {
3201 if (full) {
3202 if (dev->phy.rev >= 3)
3203 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3204 else
3205 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3206 } else {
3207 if (dev->phy.rev >= 3)
3208 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3209 else
3210 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3211 }
3212
3213 core = (cmd & 0x3000) >> 12;
3214 type = (cmd & 0x0F00) >> 8;
3215
3216 if (phy6or5x && updated[core] == 0) {
3217 b43_nphy_update_tx_cal_ladder(dev, core);
3218 updated[core] = 1;
3219 }
3220
3221 tmp = (params[core].ncorr[type] << 8) | 0x66;
3222 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3223
3224 if (type == 1 || type == 3 || type == 4) {
3225 buffer[0] = b43_ntab_read(dev,
3226 B43_NTAB16(15, 69 + core));
3227 diq_start = buffer[0];
3228 buffer[0] = 0;
3229 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3230 0);
3231 }
3232
3233 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3234 for (i = 0; i < 2000; i++) {
3235 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3236 if (tmp & 0xC000)
3237 break;
3238 udelay(10);
3239 }
3240
3241 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3242 buffer);
3243 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3244 buffer);
3245
3246 if (type == 1 || type == 3 || type == 4)
3247 buffer[0] = diq_start;
3248 }
3249
3250 if (mphase)
3251 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3252
3253 last = (dev->phy.rev < 3) ? 6 : 7;
3254
3255 if (!mphase || nphy->mphase_cal_phase_id == last) {
3256 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3257 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3258 if (dev->phy.rev < 3) {
3259 buffer[0] = 0;
3260 buffer[1] = 0;
3261 buffer[2] = 0;
3262 buffer[3] = 0;
3263 }
3264 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3265 buffer);
3266 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3267 buffer);
3268 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3269 buffer);
3270 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3271 buffer);
3272 length = 11;
3273 if (dev->phy.rev < 3)
3274 length -= 2;
3275 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3276 nphy->txiqlocal_bestc);
3277 nphy->txiqlocal_coeffsvalid = true;
3278 nphy->txiqlocal_chanspec.center_freq =
3279 dev->phy.channel_freq;
3280 nphy->txiqlocal_chanspec.channel_type =
3281 dev->phy.channel_type;
3282 } else {
3283 length = 11;
3284 if (dev->phy.rev < 3)
3285 length -= 2;
3286 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3287 nphy->mphase_txcal_bestcoeffs);
3288 }
3289
3290 b43_nphy_stop_playback(dev);
3291 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3292 }
3293
3294 b43_nphy_tx_cal_phy_cleanup(dev);
3295 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3296
3297 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3298 b43_nphy_tx_iq_workaround(dev);
3299
3300 if (dev->phy.rev >= 4)
3301 nphy->hang_avoid = avoid;
3302
3303 b43_nphy_stay_in_carrier_search(dev, false);
3304
3305 return error;
3306}
3307
3308
3309static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3310{
3311 struct b43_phy_n *nphy = dev->phy.n;
3312 u8 i;
3313 u16 buffer[7];
3314 bool equal = true;
3315
3316 if (!nphy->txiqlocal_coeffsvalid ||
3317 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3318 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3319 return;
3320
3321 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3322 for (i = 0; i < 4; i++) {
3323 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3324 equal = false;
3325 break;
3326 }
3327 }
3328
3329 if (!equal) {
3330 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3331 nphy->txiqlocal_bestc);
3332 for (i = 0; i < 4; i++)
3333 buffer[i] = 0;
3334 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3335 buffer);
3336 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3337 &nphy->txiqlocal_bestc[5]);
3338 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3339 &nphy->txiqlocal_bestc[5]);
3340 }
3341}
3342
3343
3344static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3345 struct nphy_txgains target, u8 type, bool debug)
3346{
3347 struct b43_phy_n *nphy = dev->phy.n;
3348 int i, j, index;
3349 u8 rfctl[2];
3350 u8 afectl_core;
3351 u16 tmp[6];
3352 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3353 u32 real, imag;
3354 enum ieee80211_band band;
3355
3356 u8 use;
3357 u16 cur_hpf;
3358 u16 lna[3] = { 3, 3, 1 };
3359 u16 hpf1[3] = { 7, 2, 0 };
3360 u16 hpf2[3] = { 2, 0, 0 };
3361 u32 power[3] = { };
3362 u16 gain_save[2];
3363 u16 cal_gain[2];
3364 struct nphy_iqcal_params cal_params[2];
3365 struct nphy_iq_est est;
3366 int ret = 0;
3367 bool playtone = true;
3368 int desired = 13;
3369
3370 b43_nphy_stay_in_carrier_search(dev, 1);
3371
3372 if (dev->phy.rev < 2)
3373 b43_nphy_reapply_tx_cal_coeffs(dev);
3374 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3375 for (i = 0; i < 2; i++) {
3376 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3377 cal_gain[i] = cal_params[i].cal_gain;
3378 }
3379 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3380
3381 for (i = 0; i < 2; i++) {
3382 if (i == 0) {
3383 rfctl[0] = B43_NPHY_RFCTL_INTC1;
3384 rfctl[1] = B43_NPHY_RFCTL_INTC2;
3385 afectl_core = B43_NPHY_AFECTL_C1;
3386 } else {
3387 rfctl[0] = B43_NPHY_RFCTL_INTC2;
3388 rfctl[1] = B43_NPHY_RFCTL_INTC1;
3389 afectl_core = B43_NPHY_AFECTL_C2;
3390 }
3391
3392 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3393 tmp[2] = b43_phy_read(dev, afectl_core);
3394 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3395 tmp[4] = b43_phy_read(dev, rfctl[0]);
3396 tmp[5] = b43_phy_read(dev, rfctl[1]);
3397
3398 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3399 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3400 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3401 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3402 (1 - i));
3403 b43_phy_set(dev, afectl_core, 0x0006);
3404 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3405
3406 band = b43_current_band(dev->wl);
3407
3408 if (nphy->rxcalparams & 0xFF000000) {
3409 if (band == IEEE80211_BAND_5GHZ)
3410 b43_phy_write(dev, rfctl[0], 0x140);
3411 else
3412 b43_phy_write(dev, rfctl[0], 0x110);
3413 } else {
3414 if (band == IEEE80211_BAND_5GHZ)
3415 b43_phy_write(dev, rfctl[0], 0x180);
3416 else
3417 b43_phy_write(dev, rfctl[0], 0x120);
3418 }
3419
3420 if (band == IEEE80211_BAND_5GHZ)
3421 b43_phy_write(dev, rfctl[1], 0x148);
3422 else
3423 b43_phy_write(dev, rfctl[1], 0x114);
3424
3425 if (nphy->rxcalparams & 0x10000) {
3426 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3427 (i + 1));
3428 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3429 (2 - i));
3430 }
3431
3432 for (j = 0; j < 4; j++) {
3433 if (j < 3) {
3434 cur_lna = lna[j];
3435 cur_hpf1 = hpf1[j];
3436 cur_hpf2 = hpf2[j];
3437 } else {
3438 if (power[1] > 10000) {
3439 use = 1;
3440 cur_hpf = cur_hpf1;
3441 index = 2;
3442 } else {
3443 if (power[0] > 10000) {
3444 use = 1;
3445 cur_hpf = cur_hpf1;
3446 index = 1;
3447 } else {
3448 index = 0;
3449 use = 2;
3450 cur_hpf = cur_hpf2;
3451 }
3452 }
3453 cur_lna = lna[index];
3454 cur_hpf1 = hpf1[index];
3455 cur_hpf2 = hpf2[index];
3456 cur_hpf += desired - hweight32(power[index]);
3457 cur_hpf = clamp_val(cur_hpf, 0, 10);
3458 if (use == 1)
3459 cur_hpf1 = cur_hpf;
3460 else
3461 cur_hpf2 = cur_hpf;
3462 }
3463
3464 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3465 (cur_lna << 2));
3466 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3467 false);
3468 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3469 b43_nphy_stop_playback(dev);
3470
3471 if (playtone) {
3472 ret = b43_nphy_tx_tone(dev, 4000,
3473 (nphy->rxcalparams & 0xFFFF),
3474 false, false);
3475 playtone = false;
3476 } else {
3477 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3478 false, false);
3479 }
3480
3481 if (ret == 0) {
3482 if (j < 3) {
3483 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3484 false);
3485 if (i == 0) {
3486 real = est.i0_pwr;
3487 imag = est.q0_pwr;
3488 } else {
3489 real = est.i1_pwr;
3490 imag = est.q1_pwr;
3491 }
3492 power[i] = ((real + imag) / 1024) + 1;
3493 } else {
3494 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3495 }
3496 b43_nphy_stop_playback(dev);
3497 }
3498
3499 if (ret != 0)
3500 break;
3501 }
3502
3503 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3504 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3505 b43_phy_write(dev, rfctl[1], tmp[5]);
3506 b43_phy_write(dev, rfctl[0], tmp[4]);
3507 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3508 b43_phy_write(dev, afectl_core, tmp[2]);
3509 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3510
3511 if (ret != 0)
3512 break;
3513 }
3514
3515 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3516 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3517 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3518
3519 b43_nphy_stay_in_carrier_search(dev, 0);
3520
3521 return ret;
3522}
3523
3524static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3525 struct nphy_txgains target, u8 type, bool debug)
3526{
3527 return -1;
3528}
3529
3530
3531static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3532 struct nphy_txgains target, u8 type, bool debug)
3533{
3534 if (dev->phy.rev >= 3)
3535 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3536 else
3537 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3538}
3539
3540
3541static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3542{
3543 u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
3544 if (on)
3545 tmslow |= B43_TMSLOW_MACPHYCLKEN;
3546 else
3547 tmslow &= ~B43_TMSLOW_MACPHYCLKEN;
3548 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
3549}
3550
3551
3552static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3553{
3554 struct b43_phy *phy = &dev->phy;
3555 struct b43_phy_n *nphy = phy->n;
3556
3557
3558 nphy->phyrxchain = mask;
3559
3560 if (0 )
3561 return;
3562
3563 b43_mac_suspend(dev);
3564
3565 if (nphy->hang_avoid)
3566 b43_nphy_stay_in_carrier_search(dev, true);
3567
3568 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3569 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3570
3571 if ((mask & 0x3) != 0x3) {
3572 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3573 if (dev->phy.rev >= 3) {
3574
3575 }
3576 } else {
3577 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3578 if (dev->phy.rev >= 3) {
3579
3580 }
3581 }
3582
3583 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3584
3585 if (nphy->hang_avoid)
3586 b43_nphy_stay_in_carrier_search(dev, false);
3587
3588 b43_mac_enable(dev);
3589}
3590
3591
3592
3593
3594
3595int b43_phy_initn(struct b43_wldev *dev)
3596{
3597 struct ssb_bus *bus = dev->dev->bus;
3598 struct b43_phy *phy = &dev->phy;
3599 struct b43_phy_n *nphy = phy->n;
3600 u8 tx_pwr_state;
3601 struct nphy_txgains target;
3602 u16 tmp;
3603 enum ieee80211_band tmp2;
3604 bool do_rssi_cal;
3605
3606 u16 clip[2];
3607 bool do_cal = false;
3608
3609 if ((dev->phy.rev >= 3) &&
3610 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3611 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3612 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3613 }
3614 nphy->deaf_count = 0;
3615 b43_nphy_tables_init(dev);
3616 nphy->crsminpwr_adjusted = false;
3617 nphy->noisevars_adjusted = false;
3618
3619
3620 if (dev->phy.rev >= 3) {
3621 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3622 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3623 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3624 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3625 } else {
3626 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3627 }
3628 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3629 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3630 if (dev->phy.rev < 6) {
3631 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3632 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3633 }
3634 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3635 ~(B43_NPHY_RFSEQMODE_CAOVER |
3636 B43_NPHY_RFSEQMODE_TROVER));
3637 if (dev->phy.rev >= 3)
3638 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3639 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3640
3641 if (dev->phy.rev <= 2) {
3642 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3643 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3644 ~B43_NPHY_BPHY_CTL3_SCALE,
3645 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3646 }
3647 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3648 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3649
3650 if (bus->sprom.boardflags2_lo & 0x100 ||
3651 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3652 bus->boardinfo.type == 0x8B))
3653 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3654 else
3655 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3656 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3657 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3658 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3659
3660 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3661 b43_nphy_update_txrx_chain(dev);
3662
3663 if (phy->rev < 2) {
3664 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3665 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3666 }
3667
3668 tmp2 = b43_current_band(dev->wl);
3669 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3670 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3671 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3672 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3673 nphy->papd_epsilon_offset[0] << 7);
3674 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3675 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3676 nphy->papd_epsilon_offset[1] << 7);
3677 b43_nphy_int_pa_set_tx_dig_filters(dev);
3678 } else if (phy->rev >= 5) {
3679 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3680 }
3681
3682 b43_nphy_workarounds(dev);
3683
3684
3685 b43_nphy_bmac_clock_fgc(dev, 1);
3686 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3687 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3688 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3689 b43_nphy_bmac_clock_fgc(dev, 0);
3690
3691 b43_nphy_mac_phy_clock_set(dev, true);
3692
3693 b43_nphy_pa_override(dev, false);
3694 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3695 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3696 b43_nphy_pa_override(dev, true);
3697
3698 b43_nphy_classifier(dev, 0, 0);
3699 b43_nphy_read_clip_detection(dev, clip);
3700 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3701 b43_nphy_bphy_init(dev);
3702
3703 tx_pwr_state = nphy->txpwrctrl;
3704 b43_nphy_tx_power_ctrl(dev, false);
3705 b43_nphy_tx_power_fix(dev);
3706
3707
3708
3709 if (phy->rev >= 3) {
3710
3711 } else {
3712 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3713 b43_ntab_tx_gain_rev0_1_2);
3714 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3715 b43_ntab_tx_gain_rev0_1_2);
3716 }
3717
3718 if (nphy->phyrxchain != 3)
3719 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3720 if (nphy->mphase_cal_phase_id > 0)
3721 ;
3722
3723 do_rssi_cal = false;
3724 if (phy->rev >= 3) {
3725 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3726 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3727 else
3728 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3729
3730 if (do_rssi_cal)
3731 b43_nphy_rssi_cal(dev);
3732 else
3733 b43_nphy_restore_rssi_cal(dev);
3734 } else {
3735 b43_nphy_rssi_cal(dev);
3736 }
3737
3738 if (!((nphy->measure_hold & 0x6) != 0)) {
3739 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3740 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3741 else
3742 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3743
3744 if (nphy->mute)
3745 do_cal = false;
3746
3747 if (do_cal) {
3748 target = b43_nphy_get_tx_gains(dev);
3749
3750 if (nphy->antsel_type == 2)
3751 b43_nphy_superswitch_init(dev, true);
3752 if (nphy->perical != 2) {
3753 b43_nphy_rssi_cal(dev);
3754 if (phy->rev >= 3) {
3755 nphy->cal_orig_pwr_idx[0] =
3756 nphy->txpwrindex[0].index_internal;
3757 nphy->cal_orig_pwr_idx[1] =
3758 nphy->txpwrindex[1].index_internal;
3759
3760 target = b43_nphy_get_tx_gains(dev);
3761 }
3762 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3763 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3764 b43_nphy_save_cal(dev);
3765 } else if (nphy->mphase_cal_phase_id == 0)
3766 ;
3767 } else {
3768 b43_nphy_restore_cal(dev);
3769 }
3770 }
3771
3772 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3773 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
3774 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3775 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3776 if (phy->rev >= 3 && phy->rev <= 6)
3777 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3778 b43_nphy_tx_lp_fbw(dev);
3779 if (phy->rev >= 3)
3780 b43_nphy_spur_workaround(dev);
3781
3782 return 0;
3783}
3784
3785
3786static void b43_nphy_channel_setup(struct b43_wldev *dev,
3787 const struct b43_phy_n_sfo_cfg *e,
3788 struct ieee80211_channel *new_channel)
3789{
3790 struct b43_phy *phy = &dev->phy;
3791 struct b43_phy_n *nphy = dev->phy.n;
3792
3793 u16 old_band_5ghz;
3794 u32 tmp32;
3795
3796 old_band_5ghz =
3797 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3798 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3799 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3800 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3801 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3802 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3803 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3804 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3805 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3806 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3807 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3808 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3809 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3810 }
3811
3812 b43_chantab_phy_upload(dev, e);
3813
3814 if (new_channel->hw_value == 14) {
3815 b43_nphy_classifier(dev, 2, 0);
3816 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3817 } else {
3818 b43_nphy_classifier(dev, 2, 2);
3819 if (new_channel->band == IEEE80211_BAND_2GHZ)
3820 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3821 }
3822
3823 if (!nphy->txpwrctrl)
3824 b43_nphy_tx_power_fix(dev);
3825
3826 if (dev->phy.rev < 3)
3827 b43_nphy_adjust_lna_gain_table(dev);
3828
3829 b43_nphy_tx_lp_fbw(dev);
3830
3831 if (dev->phy.rev >= 3 && 0) {
3832
3833 }
3834
3835 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3836
3837 if (phy->rev >= 3)
3838 b43_nphy_spur_workaround(dev);
3839}
3840
3841
3842static int b43_nphy_set_channel(struct b43_wldev *dev,
3843 struct ieee80211_channel *channel,
3844 enum nl80211_channel_type channel_type)
3845{
3846 struct b43_phy *phy = &dev->phy;
3847
3848 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
3849 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
3850
3851 u8 tmp;
3852
3853 if (dev->phy.rev >= 3) {
3854 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3855 channel->center_freq);
3856 if (!tabent_r3)
3857 return -ESRCH;
3858 } else {
3859 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3860 channel->hw_value);
3861 if (!tabent_r2)
3862 return -ESRCH;
3863 }
3864
3865
3866
3867 phy->channel = channel->hw_value;
3868 phy->channel_freq = channel->center_freq;
3869
3870 if (b43_channel_type_is_40mhz(phy->channel_type) !=
3871 b43_channel_type_is_40mhz(channel_type))
3872 ;
3873
3874 if (channel_type == NL80211_CHAN_HT40PLUS)
3875 b43_phy_set(dev, B43_NPHY_RXCTL,
3876 B43_NPHY_RXCTL_BSELU20);
3877 else if (channel_type == NL80211_CHAN_HT40MINUS)
3878 b43_phy_mask(dev, B43_NPHY_RXCTL,
3879 ~B43_NPHY_RXCTL_BSELU20);
3880
3881 if (dev->phy.rev >= 3) {
3882 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3883 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3884 b43_radio_2056_setup(dev, tabent_r3);
3885 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3886 } else {
3887 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3888 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3889 b43_radio_2055_setup(dev, tabent_r2);
3890 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3891 }
3892
3893 return 0;
3894}
3895
3896static int b43_nphy_op_allocate(struct b43_wldev *dev)
3897{
3898 struct b43_phy_n *nphy;
3899
3900 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3901 if (!nphy)
3902 return -ENOMEM;
3903 dev->phy.n = nphy;
3904
3905 return 0;
3906}
3907
3908static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3909{
3910 struct b43_phy *phy = &dev->phy;
3911 struct b43_phy_n *nphy = phy->n;
3912
3913 memset(nphy, 0, sizeof(*nphy));
3914
3915 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
3916 nphy->gain_boost = true;
3917 nphy->txrx_chain = 2;
3918 nphy->phyrxchain = 3;
3919 nphy->perical = 2;
3920}
3921
3922static void b43_nphy_op_free(struct b43_wldev *dev)
3923{
3924 struct b43_phy *phy = &dev->phy;
3925 struct b43_phy_n *nphy = phy->n;
3926
3927 kfree(nphy);
3928 phy->n = NULL;
3929}
3930
3931static int b43_nphy_op_init(struct b43_wldev *dev)
3932{
3933 return b43_phy_initn(dev);
3934}
3935
3936static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3937{
3938#if B43_DEBUG
3939 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3940
3941 b43err(dev->wl, "Invalid OFDM PHY access at "
3942 "0x%04X on N-PHY\n", offset);
3943 dump_stack();
3944 }
3945 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3946
3947 b43err(dev->wl, "Invalid EXT-G PHY access at "
3948 "0x%04X on N-PHY\n", offset);
3949 dump_stack();
3950 }
3951#endif
3952}
3953
3954static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3955{
3956 check_phyreg(dev, reg);
3957 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3958 return b43_read16(dev, B43_MMIO_PHY_DATA);
3959}
3960
3961static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3962{
3963 check_phyreg(dev, reg);
3964 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3965 b43_write16(dev, B43_MMIO_PHY_DATA, value);
3966}
3967
3968static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
3969 u16 set)
3970{
3971 check_phyreg(dev, reg);
3972 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3973 b43_write16(dev, B43_MMIO_PHY_DATA,
3974 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
3975}
3976
3977static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3978{
3979
3980 B43_WARN_ON(reg == 1);
3981
3982 reg |= 0x100;
3983
3984 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3985 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3986}
3987
3988static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3989{
3990
3991 B43_WARN_ON(reg == 1);
3992
3993 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3994 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3995}
3996
3997
3998static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3999 bool blocked)
4000{
4001 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4002 b43err(dev->wl, "MAC not suspended\n");
4003
4004 if (blocked) {
4005 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4006 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4007 if (dev->phy.rev >= 3) {
4008 b43_radio_mask(dev, 0x09, ~0x2);
4009
4010 b43_radio_write(dev, 0x204D, 0);
4011 b43_radio_write(dev, 0x2053, 0);
4012 b43_radio_write(dev, 0x2058, 0);
4013 b43_radio_write(dev, 0x205E, 0);
4014 b43_radio_mask(dev, 0x2062, ~0xF0);
4015 b43_radio_write(dev, 0x2064, 0);
4016
4017 b43_radio_write(dev, 0x304D, 0);
4018 b43_radio_write(dev, 0x3053, 0);
4019 b43_radio_write(dev, 0x3058, 0);
4020 b43_radio_write(dev, 0x305E, 0);
4021 b43_radio_mask(dev, 0x3062, ~0xF0);
4022 b43_radio_write(dev, 0x3064, 0);
4023 }
4024 } else {
4025 if (dev->phy.rev >= 3) {
4026 b43_radio_init2056(dev);
4027 b43_switch_channel(dev, dev->phy.channel);
4028 } else {
4029 b43_radio_init2055(dev);
4030 }
4031 }
4032}
4033
4034
4035static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4036{
4037 u16 val = on ? 0 : 0x7FFF;
4038
4039 if (dev->phy.rev >= 3)
4040 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, val);
4041 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, val);
4042}
4043
4044static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4045 unsigned int new_channel)
4046{
4047 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4048 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4049
4050 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4051 if ((new_channel < 1) || (new_channel > 14))
4052 return -EINVAL;
4053 } else {
4054 if (new_channel > 200)
4055 return -EINVAL;
4056 }
4057
4058 return b43_nphy_set_channel(dev, channel, channel_type);
4059}
4060
4061static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4062{
4063 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4064 return 1;
4065 return 36;
4066}
4067
4068const struct b43_phy_operations b43_phyops_n = {
4069 .allocate = b43_nphy_op_allocate,
4070 .free = b43_nphy_op_free,
4071 .prepare_structs = b43_nphy_op_prepare_structs,
4072 .init = b43_nphy_op_init,
4073 .phy_read = b43_nphy_op_read,
4074 .phy_write = b43_nphy_op_write,
4075 .phy_maskset = b43_nphy_op_maskset,
4076 .radio_read = b43_nphy_op_radio_read,
4077 .radio_write = b43_nphy_op_radio_write,
4078 .software_rfkill = b43_nphy_op_software_rfkill,
4079 .switch_analog = b43_nphy_op_switch_analog,
4080 .switch_channel = b43_nphy_op_switch_channel,
4081 .get_default_chan = b43_nphy_op_get_default_chan,
4082 .recalc_txpower = b43_nphy_op_recalc_txpower,
4083 .adjust_txpower = b43_nphy_op_adjust_txpower,
4084};
4085
