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30#include <linux/etherdevice.h>
31#include <linux/sched.h>
32#include <linux/slab.h>
33#include <net/mac80211.h>
34#include "iwl-eeprom.h"
35#include "iwl-dev.h"
36#include "iwl-core.h"
37#include "iwl-sta.h"
38#include "iwl-io.h"
39#include "iwl-helpers.h"
40
41
42
43
44void
45iwl_legacy_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
46{
47 u32 reg = 0;
48 int txq_id = txq->q.id;
49
50 if (txq->need_update == 0)
51 return;
52
53
54 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
55
56
57
58 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
59
60 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
61 IWL_DEBUG_INFO(priv,
62 "Tx queue %d requesting wakeup,"
63 " GP1 = 0x%x\n", txq_id, reg);
64 iwl_legacy_set_bit(priv, CSR_GP_CNTRL,
65 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
66 return;
67 }
68
69 iwl_legacy_write_direct32(priv, HBUS_TARG_WRPTR,
70 txq->q.write_ptr | (txq_id << 8));
71
72
73
74
75
76
77 } else
78 iwl_write32(priv, HBUS_TARG_WRPTR,
79 txq->q.write_ptr | (txq_id << 8));
80 txq->need_update = 0;
81}
82EXPORT_SYMBOL(iwl_legacy_txq_update_write_ptr);
83
84
85
86
87void iwl_legacy_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
88{
89 struct iwl_tx_queue *txq = &priv->txq[txq_id];
90 struct iwl_queue *q = &txq->q;
91
92 if (q->n_bd == 0)
93 return;
94
95 while (q->write_ptr != q->read_ptr) {
96 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
97 q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd);
98 }
99}
100EXPORT_SYMBOL(iwl_legacy_tx_queue_unmap);
101
102
103
104
105
106
107
108
109
110void iwl_legacy_tx_queue_free(struct iwl_priv *priv, int txq_id)
111{
112 struct iwl_tx_queue *txq = &priv->txq[txq_id];
113 struct device *dev = &priv->pci_dev->dev;
114 int i;
115
116 iwl_legacy_tx_queue_unmap(priv, txq_id);
117
118
119 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
120 kfree(txq->cmd[i]);
121
122
123 if (txq->q.n_bd)
124 dma_free_coherent(dev, priv->hw_params.tfd_size *
125 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
126
127
128 kfree(txq->txb);
129 txq->txb = NULL;
130
131
132 kfree(txq->cmd);
133 kfree(txq->meta);
134 txq->cmd = NULL;
135 txq->meta = NULL;
136
137
138 memset(txq, 0, sizeof(*txq));
139}
140EXPORT_SYMBOL(iwl_legacy_tx_queue_free);
141
142
143
144
145void iwl_legacy_cmd_queue_unmap(struct iwl_priv *priv)
146{
147 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
148 struct iwl_queue *q = &txq->q;
149 bool huge = false;
150 int i;
151
152 if (q->n_bd == 0)
153 return;
154
155 while (q->read_ptr != q->write_ptr) {
156
157 i = iwl_legacy_get_cmd_index(q, q->read_ptr, 0);
158
159 if (txq->meta[i].flags & CMD_SIZE_HUGE)
160 huge = true;
161 else
162 pci_unmap_single(priv->pci_dev,
163 dma_unmap_addr(&txq->meta[i], mapping),
164 dma_unmap_len(&txq->meta[i], len),
165 PCI_DMA_BIDIRECTIONAL);
166
167 q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd);
168 }
169
170 if (huge) {
171 i = q->n_window;
172 pci_unmap_single(priv->pci_dev,
173 dma_unmap_addr(&txq->meta[i], mapping),
174 dma_unmap_len(&txq->meta[i], len),
175 PCI_DMA_BIDIRECTIONAL);
176 }
177}
178EXPORT_SYMBOL(iwl_legacy_cmd_queue_unmap);
179
180
181
182
183
184
185
186
187
188void iwl_legacy_cmd_queue_free(struct iwl_priv *priv)
189{
190 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
191 struct device *dev = &priv->pci_dev->dev;
192 int i;
193
194 iwl_legacy_cmd_queue_unmap(priv);
195
196
197 for (i = 0; i <= TFD_CMD_SLOTS; i++)
198 kfree(txq->cmd[i]);
199
200
201 if (txq->q.n_bd)
202 dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
203 txq->tfds, txq->q.dma_addr);
204
205
206 kfree(txq->cmd);
207 kfree(txq->meta);
208 txq->cmd = NULL;
209 txq->meta = NULL;
210
211
212 memset(txq, 0, sizeof(*txq));
213}
214EXPORT_SYMBOL(iwl_legacy_cmd_queue_free);
215
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238
239int iwl_legacy_queue_space(const struct iwl_queue *q)
240{
241 int s = q->read_ptr - q->write_ptr;
242
243 if (q->read_ptr > q->write_ptr)
244 s -= q->n_bd;
245
246 if (s <= 0)
247 s += q->n_window;
248
249 s -= 2;
250 if (s < 0)
251 s = 0;
252 return s;
253}
254EXPORT_SYMBOL(iwl_legacy_queue_space);
255
256
257
258
259
260static int iwl_legacy_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
261 int count, int slots_num, u32 id)
262{
263 q->n_bd = count;
264 q->n_window = slots_num;
265 q->id = id;
266
267
268
269 BUG_ON(!is_power_of_2(count));
270
271
272
273 BUG_ON(!is_power_of_2(slots_num));
274
275 q->low_mark = q->n_window / 4;
276 if (q->low_mark < 4)
277 q->low_mark = 4;
278
279 q->high_mark = q->n_window / 8;
280 if (q->high_mark < 2)
281 q->high_mark = 2;
282
283 q->write_ptr = q->read_ptr = 0;
284
285 return 0;
286}
287
288
289
290
291static int iwl_legacy_tx_queue_alloc(struct iwl_priv *priv,
292 struct iwl_tx_queue *txq, u32 id)
293{
294 struct device *dev = &priv->pci_dev->dev;
295 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
296
297
298
299 if (id != priv->cmd_queue) {
300 txq->txb = kzalloc(sizeof(txq->txb[0]) *
301 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
302 if (!txq->txb) {
303 IWL_ERR(priv, "kmalloc for auxiliary BD "
304 "structures failed\n");
305 goto error;
306 }
307 } else {
308 txq->txb = NULL;
309 }
310
311
312
313 txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
314 GFP_KERNEL);
315 if (!txq->tfds) {
316 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
317 goto error;
318 }
319 txq->q.id = id;
320
321 return 0;
322
323 error:
324 kfree(txq->txb);
325 txq->txb = NULL;
326
327 return -ENOMEM;
328}
329
330
331
332
333int iwl_legacy_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
334 int slots_num, u32 txq_id)
335{
336 int i, len;
337 int ret;
338 int actual_slots = slots_num;
339
340
341
342
343
344
345
346
347
348 if (txq_id == priv->cmd_queue)
349 actual_slots++;
350
351 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
352 GFP_KERNEL);
353 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
354 GFP_KERNEL);
355
356 if (!txq->meta || !txq->cmd)
357 goto out_free_arrays;
358
359 len = sizeof(struct iwl_device_cmd);
360 for (i = 0; i < actual_slots; i++) {
361
362 if (i == slots_num)
363 len = IWL_MAX_CMD_SIZE;
364
365 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
366 if (!txq->cmd[i])
367 goto err;
368 }
369
370
371 ret = iwl_legacy_tx_queue_alloc(priv, txq, txq_id);
372 if (ret)
373 goto err;
374
375 txq->need_update = 0;
376
377
378
379
380
381
382 if (txq_id < 4)
383 iwl_legacy_set_swq_id(txq, txq_id, txq_id);
384
385
386
387 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
388
389
390 iwl_legacy_queue_init(priv, &txq->q,
391 TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
392
393
394 priv->cfg->ops->lib->txq_init(priv, txq);
395
396 return 0;
397err:
398 for (i = 0; i < actual_slots; i++)
399 kfree(txq->cmd[i]);
400out_free_arrays:
401 kfree(txq->meta);
402 kfree(txq->cmd);
403
404 return -ENOMEM;
405}
406EXPORT_SYMBOL(iwl_legacy_tx_queue_init);
407
408void iwl_legacy_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
409 int slots_num, u32 txq_id)
410{
411 int actual_slots = slots_num;
412
413 if (txq_id == priv->cmd_queue)
414 actual_slots++;
415
416 memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots);
417
418 txq->need_update = 0;
419
420
421 iwl_legacy_queue_init(priv, &txq->q,
422 TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
423
424
425 priv->cfg->ops->lib->txq_init(priv, txq);
426}
427EXPORT_SYMBOL(iwl_legacy_tx_queue_reset);
428
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434
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437
438
439
440int iwl_legacy_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
441{
442 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
443 struct iwl_queue *q = &txq->q;
444 struct iwl_device_cmd *out_cmd;
445 struct iwl_cmd_meta *out_meta;
446 dma_addr_t phys_addr;
447 unsigned long flags;
448 int len;
449 u32 idx;
450 u16 fix_size;
451
452 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
453 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
454
455
456
457
458
459
460 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
461 !(cmd->flags & CMD_SIZE_HUGE));
462 BUG_ON(fix_size > IWL_MAX_CMD_SIZE);
463
464 if (iwl_legacy_is_rfkill(priv) || iwl_legacy_is_ctkill(priv)) {
465 IWL_WARN(priv, "Not sending command - %s KILL\n",
466 iwl_legacy_is_rfkill(priv) ? "RF" : "CT");
467 return -EIO;
468 }
469
470 if (iwl_legacy_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
471 IWL_ERR(priv, "No space in command queue\n");
472 IWL_ERR(priv, "Restarting adapter due to queue full\n");
473 queue_work(priv->workqueue, &priv->restart);
474 return -ENOSPC;
475 }
476
477 spin_lock_irqsave(&priv->hcmd_lock, flags);
478
479
480
481
482 if (cmd->flags & CMD_SIZE_HUGE) {
483 idx = iwl_legacy_get_cmd_index(q, q->write_ptr, 0);
484 txq->meta[idx].flags = CMD_SIZE_HUGE;
485 }
486
487 idx = iwl_legacy_get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
488 out_cmd = txq->cmd[idx];
489 out_meta = &txq->meta[idx];
490
491 memset(out_meta, 0, sizeof(*out_meta));
492 out_meta->flags = cmd->flags;
493 if (cmd->flags & CMD_WANT_SKB)
494 out_meta->source = cmd;
495 if (cmd->flags & CMD_ASYNC)
496 out_meta->callback = cmd->callback;
497
498 out_cmd->hdr.cmd = cmd->id;
499 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
500
501
502
503
504 out_cmd->hdr.flags = 0;
505 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) |
506 INDEX_TO_SEQ(q->write_ptr));
507 if (cmd->flags & CMD_SIZE_HUGE)
508 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
509 len = sizeof(struct iwl_device_cmd);
510 if (idx == TFD_CMD_SLOTS)
511 len = IWL_MAX_CMD_SIZE;
512
513#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
514 switch (out_cmd->hdr.cmd) {
515 case REPLY_TX_LINK_QUALITY_CMD:
516 case SENSITIVITY_CMD:
517 IWL_DEBUG_HC_DUMP(priv,
518 "Sending command %s (#%x), seq: 0x%04X, "
519 "%d bytes at %d[%d]:%d\n",
520 iwl_legacy_get_cmd_string(out_cmd->hdr.cmd),
521 out_cmd->hdr.cmd,
522 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
523 q->write_ptr, idx, priv->cmd_queue);
524 break;
525 default:
526 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
527 "%d bytes at %d[%d]:%d\n",
528 iwl_legacy_get_cmd_string(out_cmd->hdr.cmd),
529 out_cmd->hdr.cmd,
530 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
531 q->write_ptr, idx, priv->cmd_queue);
532 }
533#endif
534 txq->need_update = 1;
535
536 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
537
538 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
539
540 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
541 fix_size, PCI_DMA_BIDIRECTIONAL);
542 dma_unmap_addr_set(out_meta, mapping, phys_addr);
543 dma_unmap_len_set(out_meta, len, fix_size);
544
545 trace_iwlwifi_legacy_dev_hcmd(priv, &out_cmd->hdr,
546 fix_size, cmd->flags);
547
548 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
549 phys_addr, fix_size, 1,
550 U32_PAD(cmd->len));
551
552
553 q->write_ptr = iwl_legacy_queue_inc_wrap(q->write_ptr, q->n_bd);
554 iwl_legacy_txq_update_write_ptr(priv, txq);
555
556 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
557 return idx;
558}
559
560
561
562
563
564
565
566
567static void iwl_legacy_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
568 int idx, int cmd_idx)
569{
570 struct iwl_tx_queue *txq = &priv->txq[txq_id];
571 struct iwl_queue *q = &txq->q;
572 int nfreed = 0;
573
574 if ((idx >= q->n_bd) || (iwl_legacy_queue_used(q, idx) == 0)) {
575 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
576 "is out of range [0-%d] %d %d.\n", txq_id,
577 idx, q->n_bd, q->write_ptr, q->read_ptr);
578 return;
579 }
580
581 for (idx = iwl_legacy_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
582 q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd)) {
583
584 if (nfreed++ > 0) {
585 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
586 q->write_ptr, q->read_ptr);
587 queue_work(priv->workqueue, &priv->restart);
588 }
589
590 }
591}
592
593
594
595
596
597
598
599
600
601void
602iwl_legacy_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
603{
604 struct iwl_rx_packet *pkt = rxb_addr(rxb);
605 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
606 int txq_id = SEQ_TO_QUEUE(sequence);
607 int index = SEQ_TO_INDEX(sequence);
608 int cmd_index;
609 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
610 struct iwl_device_cmd *cmd;
611 struct iwl_cmd_meta *meta;
612 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
613
614
615
616
617 if (WARN(txq_id != priv->cmd_queue,
618 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
619 txq_id, priv->cmd_queue, sequence,
620 priv->txq[priv->cmd_queue].q.read_ptr,
621 priv->txq[priv->cmd_queue].q.write_ptr)) {
622 iwl_print_hex_error(priv, pkt, 32);
623 return;
624 }
625
626
627
628
629
630 if (huge) {
631 cmd_index = iwl_legacy_get_cmd_index(&txq->q, index, 0);
632 txq->meta[cmd_index].flags = 0;
633 }
634 cmd_index = iwl_legacy_get_cmd_index(&txq->q, index, huge);
635 cmd = txq->cmd[cmd_index];
636 meta = &txq->meta[cmd_index];
637
638 pci_unmap_single(priv->pci_dev,
639 dma_unmap_addr(meta, mapping),
640 dma_unmap_len(meta, len),
641 PCI_DMA_BIDIRECTIONAL);
642
643
644 if (meta->flags & CMD_WANT_SKB) {
645 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
646 rxb->page = NULL;
647 } else if (meta->callback)
648 meta->callback(priv, cmd, pkt);
649
650 iwl_legacy_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
651
652 if (!(meta->flags & CMD_ASYNC)) {
653 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
654 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
655 iwl_legacy_get_cmd_string(cmd->hdr.cmd));
656 wake_up_interruptible(&priv->wait_command_queue);
657 }
658 meta->flags = 0;
659}
660EXPORT_SYMBOL(iwl_legacy_tx_cmd_complete);
661