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10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12#include <linux/errno.h>
13#include <linux/kernel.h>
14#include <linux/list.h>
15#include <linux/module.h>
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/bitops.h>
21#include <linux/gpio.h>
22
23static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
24{
25 if (enum_id < r->begin)
26 return 0;
27
28 if (enum_id > r->end)
29 return 0;
30
31 return 1;
32}
33
34static unsigned long gpio_read_raw_reg(unsigned long reg,
35 unsigned long reg_width)
36{
37 switch (reg_width) {
38 case 8:
39 return __raw_readb(reg);
40 case 16:
41 return __raw_readw(reg);
42 case 32:
43 return __raw_readl(reg);
44 }
45
46 BUG();
47 return 0;
48}
49
50static void gpio_write_raw_reg(unsigned long reg,
51 unsigned long reg_width,
52 unsigned long data)
53{
54 switch (reg_width) {
55 case 8:
56 __raw_writeb(data, reg);
57 return;
58 case 16:
59 __raw_writew(data, reg);
60 return;
61 case 32:
62 __raw_writel(data, reg);
63 return;
64 }
65
66 BUG();
67}
68
69static void gpio_write_bit(struct pinmux_data_reg *dr,
70 unsigned long in_pos, unsigned long value)
71{
72 unsigned long pos;
73
74 pos = dr->reg_width - (in_pos + 1);
75
76 pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
77 "r_width = %ld\n",
78 dr->reg, !!value, pos, dr->reg_width);
79
80 if (value)
81 set_bit(pos, &dr->reg_shadow);
82 else
83 clear_bit(pos, &dr->reg_shadow);
84
85 gpio_write_raw_reg(dr->reg, dr->reg_width, dr->reg_shadow);
86}
87
88static int gpio_read_reg(unsigned long reg, unsigned long reg_width,
89 unsigned long field_width, unsigned long in_pos)
90{
91 unsigned long data, mask, pos;
92
93 data = 0;
94 mask = (1 << field_width) - 1;
95 pos = reg_width - ((in_pos + 1) * field_width);
96
97 pr_debug("read_reg: addr = %lx, pos = %ld, "
98 "r_width = %ld, f_width = %ld\n",
99 reg, pos, reg_width, field_width);
100
101 data = gpio_read_raw_reg(reg, reg_width);
102 return (data >> pos) & mask;
103}
104
105static void gpio_write_reg(unsigned long reg, unsigned long reg_width,
106 unsigned long field_width, unsigned long in_pos,
107 unsigned long value)
108{
109 unsigned long mask, pos;
110
111 mask = (1 << field_width) - 1;
112 pos = reg_width - ((in_pos + 1) * field_width);
113
114 pr_debug("write_reg addr = %lx, value = %ld, pos = %ld, "
115 "r_width = %ld, f_width = %ld\n",
116 reg, value, pos, reg_width, field_width);
117
118 mask = ~(mask << pos);
119 value = value << pos;
120
121 switch (reg_width) {
122 case 8:
123 __raw_writeb((__raw_readb(reg) & mask) | value, reg);
124 break;
125 case 16:
126 __raw_writew((__raw_readw(reg) & mask) | value, reg);
127 break;
128 case 32:
129 __raw_writel((__raw_readl(reg) & mask) | value, reg);
130 break;
131 }
132}
133
134static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
135{
136 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
137 struct pinmux_data_reg *data_reg;
138 int k, n;
139
140 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
141 return -1;
142
143 k = 0;
144 while (1) {
145 data_reg = gpioc->data_regs + k;
146
147 if (!data_reg->reg_width)
148 break;
149
150 for (n = 0; n < data_reg->reg_width; n++) {
151 if (data_reg->enum_ids[n] == gpiop->enum_id) {
152 gpiop->flags &= ~PINMUX_FLAG_DREG;
153 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
154 gpiop->flags &= ~PINMUX_FLAG_DBIT;
155 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
156 return 0;
157 }
158 }
159 k++;
160 }
161
162 BUG();
163
164 return -1;
165}
166
167static void setup_data_regs(struct pinmux_info *gpioc)
168{
169 struct pinmux_data_reg *drp;
170 int k;
171
172 for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
173 setup_data_reg(gpioc, k);
174
175 k = 0;
176 while (1) {
177 drp = gpioc->data_regs + k;
178
179 if (!drp->reg_width)
180 break;
181
182 drp->reg_shadow = gpio_read_raw_reg(drp->reg, drp->reg_width);
183 k++;
184 }
185}
186
187static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
188 struct pinmux_data_reg **drp, int *bitp)
189{
190 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
191 int k, n;
192
193 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
194 return -1;
195
196 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
197 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
198 *drp = gpioc->data_regs + k;
199 *bitp = n;
200 return 0;
201}
202
203static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
204 struct pinmux_cfg_reg **crp, int *indexp,
205 unsigned long **cntp)
206{
207 struct pinmux_cfg_reg *config_reg;
208 unsigned long r_width, f_width;
209 int k, n;
210
211 k = 0;
212 while (1) {
213 config_reg = gpioc->cfg_regs + k;
214
215 r_width = config_reg->reg_width;
216 f_width = config_reg->field_width;
217
218 if (!r_width)
219 break;
220 for (n = 0; n < (r_width / f_width) * 1 << f_width; n++) {
221 if (config_reg->enum_ids[n] == enum_id) {
222 *crp = config_reg;
223 *indexp = n;
224 *cntp = &config_reg->cnt[n / (1 << f_width)];
225 return 0;
226 }
227 }
228 k++;
229 }
230
231 return -1;
232}
233
234static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
235 int pos, pinmux_enum_t *enum_idp)
236{
237 pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
238 pinmux_enum_t *data = gpioc->gpio_data;
239 int k;
240
241 if (!enum_in_range(enum_id, &gpioc->data)) {
242 if (!enum_in_range(enum_id, &gpioc->mark)) {
243 pr_err("non data/mark enum_id for gpio %d\n", gpio);
244 return -1;
245 }
246 }
247
248 if (pos) {
249 *enum_idp = data[pos + 1];
250 return pos + 1;
251 }
252
253 for (k = 0; k < gpioc->gpio_data_size; k++) {
254 if (data[k] == enum_id) {
255 *enum_idp = data[k + 1];
256 return k + 1;
257 }
258 }
259
260 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
261 return -1;
262}
263
264static void write_config_reg(struct pinmux_info *gpioc,
265 struct pinmux_cfg_reg *crp,
266 int index)
267{
268 unsigned long ncomb, pos, value;
269
270 ncomb = 1 << crp->field_width;
271 pos = index / ncomb;
272 value = index % ncomb;
273
274 gpio_write_reg(crp->reg, crp->reg_width, crp->field_width, pos, value);
275}
276
277static int check_config_reg(struct pinmux_info *gpioc,
278 struct pinmux_cfg_reg *crp,
279 int index)
280{
281 unsigned long ncomb, pos, value;
282
283 ncomb = 1 << crp->field_width;
284 pos = index / ncomb;
285 value = index % ncomb;
286
287 if (gpio_read_reg(crp->reg, crp->reg_width,
288 crp->field_width, pos) == value)
289 return 0;
290
291 return -1;
292}
293
294enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
295
296static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
297 int pinmux_type, int cfg_mode)
298{
299 struct pinmux_cfg_reg *cr = NULL;
300 pinmux_enum_t enum_id;
301 struct pinmux_range *range;
302 int in_range, pos, index;
303 unsigned long *cntp;
304
305 switch (pinmux_type) {
306
307 case PINMUX_TYPE_FUNCTION:
308 range = NULL;
309 break;
310
311 case PINMUX_TYPE_OUTPUT:
312 range = &gpioc->output;
313 break;
314
315 case PINMUX_TYPE_INPUT:
316 range = &gpioc->input;
317 break;
318
319 case PINMUX_TYPE_INPUT_PULLUP:
320 range = &gpioc->input_pu;
321 break;
322
323 case PINMUX_TYPE_INPUT_PULLDOWN:
324 range = &gpioc->input_pd;
325 break;
326
327 default:
328 goto out_err;
329 }
330
331 pos = 0;
332 enum_id = 0;
333 index = 0;
334 while (1) {
335 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
336 if (pos <= 0)
337 goto out_err;
338
339 if (!enum_id)
340 break;
341
342
343 in_range = enum_in_range(enum_id, &gpioc->function);
344 if (!in_range) {
345
346 if (range) {
347
348
349
350
351
352
353
354
355 in_range = enum_in_range(enum_id, range);
356
357
358
359
360
361
362 if (in_range && enum_id == range->force)
363 continue;
364 } else {
365
366
367
368
369
370
371
372
373 in_range = 1;
374 }
375 }
376
377 if (!in_range)
378 continue;
379
380 if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
381 goto out_err;
382
383 switch (cfg_mode) {
384 case GPIO_CFG_DRYRUN:
385 if (!*cntp || !check_config_reg(gpioc, cr, index))
386 continue;
387 break;
388
389 case GPIO_CFG_REQ:
390 write_config_reg(gpioc, cr, index);
391 *cntp = *cntp + 1;
392 break;
393
394 case GPIO_CFG_FREE:
395 *cntp = *cntp - 1;
396 break;
397 }
398 }
399
400 return 0;
401 out_err:
402 return -1;
403}
404
405static DEFINE_SPINLOCK(gpio_lock);
406
407static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
408{
409 return container_of(chip, struct pinmux_info, chip);
410}
411
412static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
413{
414 struct pinmux_info *gpioc = chip_to_pinmux(chip);
415 struct pinmux_data_reg *dummy;
416 unsigned long flags;
417 int i, ret, pinmux_type;
418
419 ret = -EINVAL;
420
421 if (!gpioc)
422 goto err_out;
423
424 spin_lock_irqsave(&gpio_lock, flags);
425
426 if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
427 goto err_unlock;
428
429
430
431 if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
432 pinmux_type = PINMUX_TYPE_FUNCTION;
433 else
434 pinmux_type = PINMUX_TYPE_GPIO;
435
436 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
437 if (pinmux_config_gpio(gpioc, offset,
438 pinmux_type,
439 GPIO_CFG_DRYRUN) != 0)
440 goto err_unlock;
441
442 if (pinmux_config_gpio(gpioc, offset,
443 pinmux_type,
444 GPIO_CFG_REQ) != 0)
445 BUG();
446 }
447
448 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
449 gpioc->gpios[offset].flags |= pinmux_type;
450
451 ret = 0;
452 err_unlock:
453 spin_unlock_irqrestore(&gpio_lock, flags);
454 err_out:
455 return ret;
456}
457
458static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
459{
460 struct pinmux_info *gpioc = chip_to_pinmux(chip);
461 unsigned long flags;
462 int pinmux_type;
463
464 if (!gpioc)
465 return;
466
467 spin_lock_irqsave(&gpio_lock, flags);
468
469 pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
470 pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
471 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
472 gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
473
474 spin_unlock_irqrestore(&gpio_lock, flags);
475}
476
477static int pinmux_direction(struct pinmux_info *gpioc,
478 unsigned gpio, int new_pinmux_type)
479{
480 int pinmux_type;
481 int ret = -EINVAL;
482
483 if (!gpioc)
484 goto err_out;
485
486 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
487
488 switch (pinmux_type) {
489 case PINMUX_TYPE_GPIO:
490 break;
491 case PINMUX_TYPE_OUTPUT:
492 case PINMUX_TYPE_INPUT:
493 case PINMUX_TYPE_INPUT_PULLUP:
494 case PINMUX_TYPE_INPUT_PULLDOWN:
495 pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
496 break;
497 default:
498 goto err_out;
499 }
500
501 if (pinmux_config_gpio(gpioc, gpio,
502 new_pinmux_type,
503 GPIO_CFG_DRYRUN) != 0)
504 goto err_out;
505
506 if (pinmux_config_gpio(gpioc, gpio,
507 new_pinmux_type,
508 GPIO_CFG_REQ) != 0)
509 BUG();
510
511 gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
512 gpioc->gpios[gpio].flags |= new_pinmux_type;
513
514 ret = 0;
515 err_out:
516 return ret;
517}
518
519static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
520{
521 struct pinmux_info *gpioc = chip_to_pinmux(chip);
522 unsigned long flags;
523 int ret;
524
525 spin_lock_irqsave(&gpio_lock, flags);
526 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
527 spin_unlock_irqrestore(&gpio_lock, flags);
528
529 return ret;
530}
531
532static void sh_gpio_set_value(struct pinmux_info *gpioc,
533 unsigned gpio, int value)
534{
535 struct pinmux_data_reg *dr = NULL;
536 int bit = 0;
537
538 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
539 BUG();
540 else
541 gpio_write_bit(dr, bit, value);
542}
543
544static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
545 int value)
546{
547 struct pinmux_info *gpioc = chip_to_pinmux(chip);
548 unsigned long flags;
549 int ret;
550
551 sh_gpio_set_value(gpioc, offset, value);
552 spin_lock_irqsave(&gpio_lock, flags);
553 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
554 spin_unlock_irqrestore(&gpio_lock, flags);
555
556 return ret;
557}
558
559static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
560{
561 struct pinmux_data_reg *dr = NULL;
562 int bit = 0;
563
564 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
565 return -EINVAL;
566
567 return gpio_read_reg(dr->reg, dr->reg_width, 1, bit);
568}
569
570static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
571{
572 return sh_gpio_get_value(chip_to_pinmux(chip), offset);
573}
574
575static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
576{
577 sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
578}
579
580int register_pinmux(struct pinmux_info *pip)
581{
582 struct gpio_chip *chip = &pip->chip;
583
584 pr_info("%s handling gpio %d -> %d\n",
585 pip->name, pip->first_gpio, pip->last_gpio);
586
587 setup_data_regs(pip);
588
589 chip->request = sh_gpio_request;
590 chip->free = sh_gpio_free;
591 chip->direction_input = sh_gpio_direction_input;
592 chip->get = sh_gpio_get;
593 chip->direction_output = sh_gpio_direction_output;
594 chip->set = sh_gpio_set;
595
596 WARN_ON(pip->first_gpio != 0);
597
598 chip->label = pip->name;
599 chip->owner = THIS_MODULE;
600 chip->base = pip->first_gpio;
601 chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
602
603 return gpiochip_add(chip);
604}
605
606int unregister_pinmux(struct pinmux_info *pip)
607{
608 pr_info("%s deregistering\n", pip->name);
609
610 return gpiochip_remove(&pip->chip);
611}
612
