1#ifndef _RTC_REG_REG_H_ 2#define _RTC_REG_REG_H_ 3 4#define RESET_CONTROL_ADDRESS 0x00000000 5#define RESET_CONTROL_OFFSET 0x00000000 6#define RESET_CONTROL_CPU_INIT_RESET_MSB 11 7#define RESET_CONTROL_CPU_INIT_RESET_LSB 11 8#define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 9#define RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB) 10#define RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK) 11#define RESET_CONTROL_VMC_REMAP_RESET_MSB 10 12#define RESET_CONTROL_VMC_REMAP_RESET_LSB 10 13#define RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400 14#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB) 15#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK) 16#define RESET_CONTROL_RST_OUT_MSB 9 17#define RESET_CONTROL_RST_OUT_LSB 9 18#define RESET_CONTROL_RST_OUT_MASK 0x00000200 19#define RESET_CONTROL_RST_OUT_GET(x) (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB) 20#define RESET_CONTROL_RST_OUT_SET(x) (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK) 21#define RESET_CONTROL_COLD_RST_MSB 8 22#define RESET_CONTROL_COLD_RST_LSB 8 23#define RESET_CONTROL_COLD_RST_MASK 0x00000100 24#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB) 25#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK) 26#define RESET_CONTROL_WARM_RST_MSB 7 27#define RESET_CONTROL_WARM_RST_LSB 7 28#define RESET_CONTROL_WARM_RST_MASK 0x00000080 29#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB) 30#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK) 31#define RESET_CONTROL_CPU_WARM_RST_MSB 6 32#define RESET_CONTROL_CPU_WARM_RST_LSB 6 33#define RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 34#define RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB) 35#define RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK) 36#define RESET_CONTROL_MAC_COLD_RST_MSB 5 37#define RESET_CONTROL_MAC_COLD_RST_LSB 5 38#define RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020 39#define RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB) 40#define RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK) 41#define RESET_CONTROL_MAC_WARM_RST_MSB 4 42#define RESET_CONTROL_MAC_WARM_RST_LSB 4 43#define RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010 44#define RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB) 45#define RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK) 46#define RESET_CONTROL_MBOX_RST_MSB 2 47#define RESET_CONTROL_MBOX_RST_LSB 2 48#define RESET_CONTROL_MBOX_RST_MASK 0x00000004 49#define RESET_CONTROL_MBOX_RST_GET(x) (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB) 50#define RESET_CONTROL_MBOX_RST_SET(x) (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK) 51#define RESET_CONTROL_UART_RST_MSB 1 52#define RESET_CONTROL_UART_RST_LSB 1 53#define RESET_CONTROL_UART_RST_MASK 0x00000002 54#define RESET_CONTROL_UART_RST_GET(x) (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB) 55#define RESET_CONTROL_UART_RST_SET(x) (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK) 56#define RESET_CONTROL_SI0_RST_MSB 0 57#define RESET_CONTROL_SI0_RST_LSB 0 58#define RESET_CONTROL_SI0_RST_MASK 0x00000001 59#define RESET_CONTROL_SI0_RST_GET(x) (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB) 60#define RESET_CONTROL_SI0_RST_SET(x) (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK) 61 62#define XTAL_CONTROL_ADDRESS 0x00000004 63#define XTAL_CONTROL_OFFSET 0x00000004 64#define XTAL_CONTROL_TCXO_MSB 0 65#define XTAL_CONTROL_TCXO_LSB 0 66#define XTAL_CONTROL_TCXO_MASK 0x00000001 67#define XTAL_CONTROL_TCXO_GET(x) (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB) 68#define XTAL_CONTROL_TCXO_SET(x) (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK) 69 70#define TCXO_DETECT_ADDRESS 0x00000008 71#define TCXO_DETECT_OFFSET 0x00000008 72#define TCXO_DETECT_PRESENT_MSB 0 73#define TCXO_DETECT_PRESENT_LSB 0 74#define TCXO_DETECT_PRESENT_MASK 0x00000001 75#define TCXO_DETECT_PRESENT_GET(x) (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB) 76#define TCXO_DETECT_PRESENT_SET(x) (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK) 77 78#define XTAL_TEST_ADDRESS 0x0000000c 79#define XTAL_TEST_OFFSET 0x0000000c 80#define XTAL_TEST_NOTCXODET_MSB 0 81#define XTAL_TEST_NOTCXODET_LSB 0 82#define XTAL_TEST_NOTCXODET_MASK 0x00000001 83#define XTAL_TEST_NOTCXODET_GET(x) (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB) 84#define XTAL_TEST_NOTCXODET_SET(x) (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK) 85 86#define QUADRATURE_ADDRESS 0x00000010 87#define QUADRATURE_OFFSET 0x00000010 88#define QUADRATURE_ADC_MSB 5 89#define QUADRATURE_ADC_LSB 4 90#define QUADRATURE_ADC_MASK 0x00000030 91#define QUADRATURE_ADC_GET(x) (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB) 92#define QUADRATURE_ADC_SET(x) (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK) 93#define QUADRATURE_SEL_MSB 2 94#define QUADRATURE_SEL_LSB 2 95#define QUADRATURE_SEL_MASK 0x00000004 96#define QUADRATURE_SEL_GET(x) (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB) 97#define QUADRATURE_SEL_SET(x) (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK) 98#define QUADRATURE_DAC_MSB 1 99#define QUADRATURE_DAC_LSB 0 100#define QUADRATURE_DAC_MASK 0x00000003 101#define QUADRATURE_DAC_GET(x) (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB) 102#define QUADRATURE_DAC_SET(x) (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK) 103 104#define PLL_CONTROL_ADDRESS 0x00000014 105#define PLL_CONTROL_OFFSET 0x00000014 106#define PLL_CONTROL_DIG_TEST_CLK_MSB 20 107#define PLL_CONTROL_DIG_TEST_CLK_LSB 20 108#define PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000 109#define PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB) 110#define PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK) 111#define PLL_CONTROL_MAC_OVERRIDE_MSB 19 112#define PLL_CONTROL_MAC_OVERRIDE_LSB 19 113#define PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000 114#define PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB) 115#define PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK) 116#define PLL_CONTROL_NOPWD_MSB 18 117#define PLL_CONTROL_NOPWD_LSB 18 118#define PLL_CONTROL_NOPWD_MASK 0x00040000 119#define PLL_CONTROL_NOPWD_GET(x) (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB) 120#define PLL_CONTROL_NOPWD_SET(x) (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK) 121#define PLL_CONTROL_UPDATING_MSB 17 122#define PLL_CONTROL_UPDATING_LSB 17 123#define PLL_CONTROL_UPDATING_MASK 0x00020000 124#define PLL_CONTROL_UPDATING_GET(x) (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB) 125#define PLL_CONTROL_UPDATING_SET(x) (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK) 126#define PLL_CONTROL_BYPASS_MSB 16 127#define PLL_CONTROL_BYPASS_LSB 16 128#define PLL_CONTROL_BYPASS_MASK 0x00010000 129#define PLL_CONTROL_BYPASS_GET(x) (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB) 130#define PLL_CONTROL_BYPASS_SET(x) (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK) 131#define PLL_CONTROL_REFDIV_MSB 15 132#define PLL_CONTROL_REFDIV_LSB 12 133#define PLL_CONTROL_REFDIV_MASK 0x0000f000 134#define PLL_CONTROL_REFDIV_GET(x) (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB) 135#define PLL_CONTROL_REFDIV_SET(x) (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK) 136#define PLL_CONTROL_DIV_MSB 9 137#define PLL_CONTROL_DIV_LSB 0 138#define PLL_CONTROL_DIV_MASK 0x000003ff 139#define PLL_CONTROL_DIV_GET(x) (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB) 140#define PLL_CONTROL_DIV_SET(x) (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK) 141 142#define PLL_SETTLE_ADDRESS 0x00000018 143#define PLL_SETTLE_OFFSET 0x00000018 144#define PLL_SETTLE_TIME_MSB 11 145#define PLL_SETTLE_TIME_LSB 0 146#define PLL_SETTLE_TIME_MASK 0x00000fff 147#define PLL_SETTLE_TIME_GET(x) (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB) 148#define PLL_SETTLE_TIME_SET(x) (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK) 149 150#define XTAL_SETTLE_ADDRESS 0x0000001c 151#define XTAL_SETTLE_OFFSET 0x0000001c 152#define XTAL_SETTLE_TIME_MSB 7 153#define XTAL_SETTLE_TIME_LSB 0 154#define XTAL_SETTLE_TIME_MASK 0x000000ff 155#define XTAL_SETTLE_TIME_GET(x) (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB) 156#define XTAL_SETTLE_TIME_SET(x) (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK) 157 158#define CPU_CLOCK_ADDRESS 0x00000020 159#define CPU_CLOCK_OFFSET 0x00000020 160#define CPU_CLOCK_STANDARD_MSB 1 161#define CPU_CLOCK_STANDARD_LSB 0 162#define CPU_CLOCK_STANDARD_MASK 0x00000003 163#define CPU_CLOCK_STANDARD_GET(x) (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB) 164#define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) 165 166#define CLOCK_OUT_ADDRESS 0x00000024 167#define CLOCK_OUT_OFFSET 0x00000024 168#define CLOCK_OUT_SELECT_MSB 3 169#define CLOCK_OUT_SELECT_LSB 0 170#define CLOCK_OUT_SELECT_MASK 0x0000000f 171#define CLOCK_OUT_SELECT_GET(x) (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB) 172#define CLOCK_OUT_SELECT_SET(x) (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK) 173 174#define CLOCK_CONTROL_ADDRESS 0x00000028 175#define CLOCK_CONTROL_OFFSET 0x00000028 176#define CLOCK_CONTROL_LF_CLK32_MSB 2 177#define CLOCK_CONTROL_LF_CLK32_LSB 2 178#define CLOCK_CONTROL_LF_CLK32_MASK 0x00000004 179#define CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB) 180#define CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK) 181#define CLOCK_CONTROL_UART_CLK_MSB 1 182#define CLOCK_CONTROL_UART_CLK_LSB 1 183#define CLOCK_CONTROL_UART_CLK_MASK 0x00000002 184#define CLOCK_CONTROL_UART_CLK_GET(x) (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB) 185#define CLOCK_CONTROL_UART_CLK_SET(x) (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK) 186#define CLOCK_CONTROL_SI0_CLK_MSB 0 187#define CLOCK_CONTROL_SI0_CLK_LSB 0 188#define CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 189#define CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB) 190#define CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK) 191 192#define BIAS_OVERRIDE_ADDRESS 0x0000002c 193#define BIAS_OVERRIDE_OFFSET 0x0000002c 194#define BIAS_OVERRIDE_ON_MSB 0 195#define BIAS_OVERRIDE_ON_LSB 0 196#define BIAS_OVERRIDE_ON_MASK 0x00000001 197#define BIAS_OVERRIDE_ON_GET(x) (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB) 198#define BIAS_OVERRIDE_ON_SET(x) (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK) 199 200#define WDT_CONTROL_ADDRESS 0x00000030 201#define WDT_CONTROL_OFFSET 0x00000030 202#define WDT_CONTROL_ACTION_MSB 2 203#define WDT_CONTROL_ACTION_LSB 0 204#define WDT_CONTROL_ACTION_MASK 0x00000007 205#define WDT_CONTROL_ACTION_GET(x) (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB) 206#define WDT_CONTROL_ACTION_SET(x) (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK) 207 208#define WDT_STATUS_ADDRESS 0x00000034 209#define WDT_STATUS_OFFSET 0x00000034 210#define WDT_STATUS_INTERRUPT_MSB 0 211#define WDT_STATUS_INTERRUPT_LSB 0 212#define WDT_STATUS_INTERRUPT_MASK 0x00000001 213#define WDT_STATUS_INTERRUPT_GET(x) (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB) 214#define WDT_STATUS_INTERRUPT_SET(x) (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK) 215 216#define WDT_ADDRESS 0x00000038 217#define WDT_OFFSET 0x00000038 218#define WDT_TARGET_MSB 21 219#define WDT_TARGET_LSB 0 220#define WDT_TARGET_MASK 0x003fffff 221#define WDT_TARGET_GET(x) (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB) 222#define WDT_TARGET_SET(x) (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK) 223 224#define WDT_COUNT_ADDRESS 0x0000003c 225#define WDT_COUNT_OFFSET 0x0000003c 226#define WDT_COUNT_VALUE_MSB 21 227#define WDT_COUNT_VALUE_LSB 0 228#define WDT_COUNT_VALUE_MASK 0x003fffff 229#define WDT_COUNT_VALUE_GET(x) (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB) 230#define WDT_COUNT_VALUE_SET(x) (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK) 231 232#define WDT_RESET_ADDRESS 0x00000040 233#define WDT_RESET_OFFSET 0x00000040 234#define WDT_RESET_VALUE_MSB 0 235#define WDT_RESET_VALUE_LSB 0 236#define WDT_RESET_VALUE_MASK 0x00000001 237#define WDT_RESET_VALUE_GET(x) (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB) 238#define WDT_RESET_VALUE_SET(x) (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK) 239 240#define INT_STATUS_ADDRESS 0x00000044 241#define INT_STATUS_OFFSET 0x00000044 242#define INT_STATUS_RTC_POWER_MSB 14 243#define INT_STATUS_RTC_POWER_LSB 14 244#define INT_STATUS_RTC_POWER_MASK 0x00004000 245#define INT_STATUS_RTC_POWER_GET(x) (((x) & INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB) 246#define INT_STATUS_RTC_POWER_SET(x) (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK) 247#define INT_STATUS_MAC_MSB 13 248#define INT_STATUS_MAC_LSB 13 249#define INT_STATUS_MAC_MASK 0x00002000 250#define INT_STATUS_MAC_GET(x) (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB) 251#define INT_STATUS_MAC_SET(x) (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK) 252#define INT_STATUS_MAILBOX_MSB 12 253#define INT_STATUS_MAILBOX_LSB 12 254#define INT_STATUS_MAILBOX_MASK 0x00001000 255#define INT_STATUS_MAILBOX_GET(x) (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB) 256#define INT_STATUS_MAILBOX_SET(x) (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK) 257#define INT_STATUS_RTC_ALARM_MSB 11 258#define INT_STATUS_RTC_ALARM_LSB 11 259#define INT_STATUS_RTC_ALARM_MASK 0x00000800 260#define INT_STATUS_RTC_ALARM_GET(x) (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB) 261#define INT_STATUS_RTC_ALARM_SET(x) (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK) 262#define INT_STATUS_HF_TIMER_MSB 10 263#define INT_STATUS_HF_TIMER_LSB 10 264#define INT_STATUS_HF_TIMER_MASK 0x00000400 265#define INT_STATUS_HF_TIMER_GET(x) (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB) 266#define INT_STATUS_HF_TIMER_SET(x) (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK) 267#define INT_STATUS_LF_TIMER3_MSB 9 268#define INT_STATUS_LF_TIMER3_LSB 9 269#define INT_STATUS_LF_TIMER3_MASK 0x00000200 270#define INT_STATUS_LF_TIMER3_GET(x) (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB) 271#define INT_STATUS_LF_TIMER3_SET(x) (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK) 272#define INT_STATUS_LF_TIMER2_MSB 8 273#define INT_STATUS_LF_TIMER2_LSB 8 274#define INT_STATUS_LF_TIMER2_MASK 0x00000100 275#define INT_STATUS_LF_TIMER2_GET(x) (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB) 276#define INT_STATUS_LF_TIMER2_SET(x) (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK) 277#define INT_STATUS_LF_TIMER1_MSB 7 278#define INT_STATUS_LF_TIMER1_LSB 7 279#define INT_STATUS_LF_TIMER1_MASK 0x00000080 280#define INT_STATUS_LF_TIMER1_GET(x) (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB) 281#define INT_STATUS_LF_TIMER1_SET(x) (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK) 282#define INT_STATUS_LF_TIMER0_MSB 6 283#define INT_STATUS_LF_TIMER0_LSB 6 284#define INT_STATUS_LF_TIMER0_MASK 0x00000040 285#define INT_STATUS_LF_TIMER0_GET(x) (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB) 286#define INT_STATUS_LF_TIMER0_SET(x) (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK) 287#define INT_STATUS_KEYPAD_MSB 5 288#define INT_STATUS_KEYPAD_LSB 5 289#define INT_STATUS_KEYPAD_MASK 0x00000020 290#define INT_STATUS_KEYPAD_GET(x) (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB) 291#define INT_STATUS_KEYPAD_SET(x) (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK) 292#define INT_STATUS_SI_MSB 4 293#define INT_STATUS_SI_LSB 4 294#define INT_STATUS_SI_MASK 0x00000010 295#define INT_STATUS_SI_GET(x) (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB) 296#define INT_STATUS_SI_SET(x) (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK) 297#define INT_STATUS_GPIO_MSB 3 298#define INT_STATUS_GPIO_LSB 3 299#define INT_STATUS_GPIO_MASK 0x00000008 300#define INT_STATUS_GPIO_GET(x) (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB) 301#define INT_STATUS_GPIO_SET(x) (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK) 302#define INT_STATUS_UART_MSB 2 303#define INT_STATUS_UART_LSB 2 304#define INT_STATUS_UART_MASK 0x00000004 305#define INT_STATUS_UART_GET(x) (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB) 306#define INT_STATUS_UART_SET(x) (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK) 307#define INT_STATUS_ERROR_MSB 1 308#define INT_STATUS_ERROR_LSB 1 309#define INT_STATUS_ERROR_MASK 0x00000002 310#define INT_STATUS_ERROR_GET(x) (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB) 311#define INT_STATUS_ERROR_SET(x) (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK) 312#define INT_STATUS_WDT_INT_MSB 0 313#define INT_STATUS_WDT_INT_LSB 0 314#define INT_STATUS_WDT_INT_MASK 0x00000001 315#define INT_STATUS_WDT_INT_GET(x) (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB) 316#define INT_STATUS_WDT_INT_SET(x) (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK) 317 318#define LF_TIMER0_ADDRESS 0x00000048 319#define LF_TIMER0_OFFSET 0x00000048 320#define LF_TIMER0_TARGET_MSB 31 321#define LF_TIMER0_TARGET_LSB 0 322#define LF_TIMER0_TARGET_MASK 0xffffffff 323#define LF_TIMER0_TARGET_GET(x) (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB) 324#define LF_TIMER0_TARGET_SET(x) (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK) 325 326#define LF_TIMER_COUNT0_ADDRESS 0x0000004c 327#define LF_TIMER_COUNT0_OFFSET 0x0000004c 328#define LF_TIMER_COUNT0_VALUE_MSB 31 329#define LF_TIMER_COUNT0_VALUE_LSB 0 330#define LF_TIMER_COUNT0_VALUE_MASK 0xffffffff 331#define LF_TIMER_COUNT0_VALUE_GET(x) (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB) 332#define LF_TIMER_COUNT0_VALUE_SET(x) (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK) 333 334#define LF_TIMER_CONTROL0_ADDRESS 0x00000050 335#define LF_TIMER_CONTROL0_OFFSET 0x00000050 336#define LF_TIMER_CONTROL0_ENABLE_MSB 2 337#define LF_TIMER_CONTROL0_ENABLE_LSB 2 338#define LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 339#define LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB) 340#define LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK) 341#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1 342#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1 343#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002 344#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB) 345#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) 346#define LF_TIMER_CONTROL0_RESET_MSB 0 347#define LF_TIMER_CONTROL0_RESET_LSB 0 348#define LF_TIMER_CONTROL0_RESET_MASK 0x00000001 349#define LF_TIMER_CONTROL0_RESET_GET(x) (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB) 350#define LF_TIMER_CONTROL0_RESET_SET(x) (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK) 351 352#define LF_TIMER_STATUS0_ADDRESS 0x00000054 353#define LF_TIMER_STATUS0_OFFSET 0x00000054 354#define LF_TIMER_STATUS0_INTERRUPT_MSB 0 355#define LF_TIMER_STATUS0_INTERRUPT_LSB 0 356#define LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001 357#define LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB) 358#define LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK) 359 360#define LF_TIMER1_ADDRESS 0x00000058 361#define LF_TIMER1_OFFSET 0x00000058 362#define LF_TIMER1_TARGET_MSB 31 363#define LF_TIMER1_TARGET_LSB 0 364#define LF_TIMER1_TARGET_MASK 0xffffffff 365#define LF_TIMER1_TARGET_GET(x) (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB) 366#define LF_TIMER1_TARGET_SET(x) (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK) 367 368#define LF_TIMER_COUNT1_ADDRESS 0x0000005c 369#define LF_TIMER_COUNT1_OFFSET 0x0000005c 370#define LF_TIMER_COUNT1_VALUE_MSB 31 371#define LF_TIMER_COUNT1_VALUE_LSB 0 372#define LF_TIMER_COUNT1_VALUE_MASK 0xffffffff 373#define LF_TIMER_COUNT1_VALUE_GET(x) (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB) 374#define LF_TIMER_COUNT1_VALUE_SET(x) (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK) 375 376#define LF_TIMER_CONTROL1_ADDRESS 0x00000060 377#define LF_TIMER_CONTROL1_OFFSET 0x00000060 378#define LF_TIMER_CONTROL1_ENABLE_MSB 2 379#define LF_TIMER_CONTROL1_ENABLE_LSB 2 380#define LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004 381#define LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB) 382#define LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK) 383#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1 384#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1 385#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002 386#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB) 387#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) 388#define LF_TIMER_CONTROL1_RESET_MSB 0 389#define LF_TIMER_CONTROL1_RESET_LSB 0 390#define LF_TIMER_CONTROL1_RESET_MASK 0x00000001 391#define LF_TIMER_CONTROL1_RESET_GET(x) (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB) 392#define LF_TIMER_CONTROL1_RESET_SET(x) (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK) 393 394#define LF_TIMER_STATUS1_ADDRESS 0x00000064 395#define LF_TIMER_STATUS1_OFFSET 0x00000064 396#define LF_TIMER_STATUS1_INTERRUPT_MSB 0 397#define LF_TIMER_STATUS1_INTERRUPT_LSB 0 398#define LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001 399#define LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB) 400#define LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK) 401 402#define LF_TIMER2_ADDRESS 0x00000068 403#define LF_TIMER2_OFFSET 0x00000068 404#define LF_TIMER2_TARGET_MSB 31 405#define LF_TIMER2_TARGET_LSB 0 406#define LF_TIMER2_TARGET_MASK 0xffffffff 407#define LF_TIMER2_TARGET_GET(x) (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB) 408#define LF_TIMER2_TARGET_SET(x) (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK) 409 410#define LF_TIMER_COUNT2_ADDRESS 0x0000006c 411#define LF_TIMER_COUNT2_OFFSET 0x0000006c 412#define LF_TIMER_COUNT2_VALUE_MSB 31 413#define LF_TIMER_COUNT2_VALUE_LSB 0 414#define LF_TIMER_COUNT2_VALUE_MASK 0xffffffff 415#define LF_TIMER_COUNT2_VALUE_GET(x) (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB) 416#define LF_TIMER_COUNT2_VALUE_SET(x) (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK) 417 418#define LF_TIMER_CONTROL2_ADDRESS 0x00000070 419#define LF_TIMER_CONTROL2_OFFSET 0x00000070 420#define LF_TIMER_CONTROL2_ENABLE_MSB 2 421#define LF_TIMER_CONTROL2_ENABLE_LSB 2 422#define LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004 423#define LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB) 424#define LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK) 425#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1 426#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1 427#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002 428#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB) 429#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) 430#define LF_TIMER_CONTROL2_RESET_MSB 0 431#define LF_TIMER_CONTROL2_RESET_LSB 0 432#define LF_TIMER_CONTROL2_RESET_MASK 0x00000001 433#define LF_TIMER_CONTROL2_RESET_GET(x) (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB) 434#define LF_TIMER_CONTROL2_RESET_SET(x) (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK) 435 436#define LF_TIMER_STATUS2_ADDRESS 0x00000074 437#define LF_TIMER_STATUS2_OFFSET 0x00000074 438#define LF_TIMER_STATUS2_INTERRUPT_MSB 0 439#define LF_TIMER_STATUS2_INTERRUPT_LSB 0 440#define LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001 441#define LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB) 442#define LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK) 443 444#define LF_TIMER3_ADDRESS 0x00000078 445#define LF_TIMER3_OFFSET 0x00000078 446#define LF_TIMER3_TARGET_MSB 31 447#define LF_TIMER3_TARGET_LSB 0 448#define LF_TIMER3_TARGET_MASK 0xffffffff 449#define LF_TIMER3_TARGET_GET(x) (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB) 450#define LF_TIMER3_TARGET_SET(x) (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK) 451 452#define LF_TIMER_COUNT3_ADDRESS 0x0000007c 453#define LF_TIMER_COUNT3_OFFSET 0x0000007c 454#define LF_TIMER_COUNT3_VALUE_MSB 31 455#define LF_TIMER_COUNT3_VALUE_LSB 0 456#define LF_TIMER_COUNT3_VALUE_MASK 0xffffffff 457#define LF_TIMER_COUNT3_VALUE_GET(x) (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB) 458#define LF_TIMER_COUNT3_VALUE_SET(x) (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK) 459 460#define LF_TIMER_CONTROL3_ADDRESS 0x00000080 461#define LF_TIMER_CONTROL3_OFFSET 0x00000080 462#define LF_TIMER_CONTROL3_ENABLE_MSB 2 463#define LF_TIMER_CONTROL3_ENABLE_LSB 2 464#define LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004 465#define LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB) 466#define LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK) 467#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1 468#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1 469#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002 470#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB) 471#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) 472#define LF_TIMER_CONTROL3_RESET_MSB 0 473#define LF_TIMER_CONTROL3_RESET_LSB 0 474#define LF_TIMER_CONTROL3_RESET_MASK 0x00000001 475#define LF_TIMER_CONTROL3_RESET_GET(x) (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB) 476#define LF_TIMER_CONTROL3_RESET_SET(x) (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK) 477 478#define LF_TIMER_STATUS3_ADDRESS 0x00000084 479#define LF_TIMER_STATUS3_OFFSET 0x00000084 480#define LF_TIMER_STATUS3_INTERRUPT_MSB 0 481#define LF_TIMER_STATUS3_INTERRUPT_LSB 0 482#define LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001 483#define LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB) 484#define LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK) 485 486#define HF_TIMER_ADDRESS 0x00000088 487#define HF_TIMER_OFFSET 0x00000088 488#define HF_TIMER_TARGET_MSB 31 489#define HF_TIMER_TARGET_LSB 12 490#define HF_TIMER_TARGET_MASK 0xfffff000 491#define HF_TIMER_TARGET_GET(x) (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB) 492#define HF_TIMER_TARGET_SET(x) (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK) 493 494#define HF_TIMER_COUNT_ADDRESS 0x0000008c 495#define HF_TIMER_COUNT_OFFSET 0x0000008c 496#define HF_TIMER_COUNT_VALUE_MSB 31 497#define HF_TIMER_COUNT_VALUE_LSB 12 498#define HF_TIMER_COUNT_VALUE_MASK 0xfffff000 499#define HF_TIMER_COUNT_VALUE_GET(x) (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB) 500#define HF_TIMER_COUNT_VALUE_SET(x) (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK) 501 502#define HF_LF_COUNT_ADDRESS 0x00000090 503#define HF_LF_COUNT_OFFSET 0x00000090 504#define HF_LF_COUNT_VALUE_MSB 31 505#define HF_LF_COUNT_VALUE_LSB 0 506#define HF_LF_COUNT_VALUE_MASK 0xffffffff 507#define HF_LF_COUNT_VALUE_GET(x) (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB) 508#define HF_LF_COUNT_VALUE_SET(x) (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK) 509 510#define HF_TIMER_CONTROL_ADDRESS 0x00000094 511#define HF_TIMER_CONTROL_OFFSET 0x00000094 512#define HF_TIMER_CONTROL_ENABLE_MSB 3 513#define HF_TIMER_CONTROL_ENABLE_LSB 3 514#define HF_TIMER_CONTROL_ENABLE_MASK 0x00000008 515#define HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB) 516#define HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK) 517#define HF_TIMER_CONTROL_ON_MSB 2 518#define HF_TIMER_CONTROL_ON_LSB 2 519#define HF_TIMER_CONTROL_ON_MASK 0x00000004 520#define HF_TIMER_CONTROL_ON_GET(x) (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB) 521#define HF_TIMER_CONTROL_ON_SET(x) (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK) 522#define HF_TIMER_CONTROL_AUTO_RESTART_MSB 1 523#define HF_TIMER_CONTROL_AUTO_RESTART_LSB 1 524#define HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002 525#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB) 526#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) 527#define HF_TIMER_CONTROL_RESET_MSB 0 528#define HF_TIMER_CONTROL_RESET_LSB 0 529#define HF_TIMER_CONTROL_RESET_MASK 0x00000001 530#define HF_TIMER_CONTROL_RESET_GET(x) (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB) 531#define HF_TIMER_CONTROL_RESET_SET(x) (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK) 532 533#define HF_TIMER_STATUS_ADDRESS 0x00000098 534#define HF_TIMER_STATUS_OFFSET 0x00000098 535#define HF_TIMER_STATUS_INTERRUPT_MSB 0 536#define HF_TIMER_STATUS_INTERRUPT_LSB 0 537#define HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001 538#define HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB) 539#define HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK) 540 541#define RTC_CONTROL_ADDRESS 0x0000009c 542#define RTC_CONTROL_OFFSET 0x0000009c 543#define RTC_CONTROL_ENABLE_MSB 2 544#define RTC_CONTROL_ENABLE_LSB 2 545#define RTC_CONTROL_ENABLE_MASK 0x00000004 546#define RTC_CONTROL_ENABLE_GET(x) (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB) 547#define RTC_CONTROL_ENABLE_SET(x) (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK) 548#define RTC_CONTROL_LOAD_RTC_MSB 1 549#define RTC_CONTROL_LOAD_RTC_LSB 1 550#define RTC_CONTROL_LOAD_RTC_MASK 0x00000002 551#define RTC_CONTROL_LOAD_RTC_GET(x) (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB) 552#define RTC_CONTROL_LOAD_RTC_SET(x) (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK) 553#define RTC_CONTROL_LOAD_ALARM_MSB 0 554#define RTC_CONTROL_LOAD_ALARM_LSB 0 555#define RTC_CONTROL_LOAD_ALARM_MASK 0x00000001 556#define RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB) 557#define RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK) 558 559#define RTC_TIME_ADDRESS 0x000000a0 560#define RTC_TIME_OFFSET 0x000000a0 561#define RTC_TIME_WEEK_DAY_MSB 26 562#define RTC_TIME_WEEK_DAY_LSB 24 563#define RTC_TIME_WEEK_DAY_MASK 0x07000000 564#define RTC_TIME_WEEK_DAY_GET(x) (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB) 565#define RTC_TIME_WEEK_DAY_SET(x) (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK) 566#define RTC_TIME_HOUR_MSB 21 567#define RTC_TIME_HOUR_LSB 16 568#define RTC_TIME_HOUR_MASK 0x003f0000 569#define RTC_TIME_HOUR_GET(x) (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB) 570#define RTC_TIME_HOUR_SET(x) (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK) 571#define RTC_TIME_MINUTE_MSB 14 572#define RTC_TIME_MINUTE_LSB 8 573#define RTC_TIME_MINUTE_MASK 0x00007f00 574#define RTC_TIME_MINUTE_GET(x) (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB) 575#define RTC_TIME_MINUTE_SET(x) (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK) 576#define RTC_TIME_SECOND_MSB 6 577#define RTC_TIME_SECOND_LSB 0 578#define RTC_TIME_SECOND_MASK 0x0000007f 579#define RTC_TIME_SECOND_GET(x) (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB) 580#define RTC_TIME_SECOND_SET(x) (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK) 581 582#define RTC_DATE_ADDRESS 0x000000a4 583#define RTC_DATE_OFFSET 0x000000a4 584#define RTC_DATE_YEAR_MSB 23 585#define RTC_DATE_YEAR_LSB 16 586#define RTC_DATE_YEAR_MASK 0x00ff0000 587#define RTC_DATE_YEAR_GET(x) (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB) 588#define RTC_DATE_YEAR_SET(x) (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK) 589#define RTC_DATE_MONTH_MSB 12 590#define RTC_DATE_MONTH_LSB 8 591#define RTC_DATE_MONTH_MASK 0x00001f00 592#define RTC_DATE_MONTH_GET(x) (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB) 593#define RTC_DATE_MONTH_SET(x) (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK) 594#define RTC_DATE_MONTH_DAY_MSB 5 595#define RTC_DATE_MONTH_DAY_LSB 0 596#define RTC_DATE_MONTH_DAY_MASK 0x0000003f 597#define RTC_DATE_MONTH_DAY_GET(x) (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB) 598#define RTC_DATE_MONTH_DAY_SET(x) (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK) 599 600#define RTC_SET_TIME_ADDRESS 0x000000a8 601#define RTC_SET_TIME_OFFSET 0x000000a8 602#define RTC_SET_TIME_WEEK_DAY_MSB 26 603#define RTC_SET_TIME_WEEK_DAY_LSB 24 604#define RTC_SET_TIME_WEEK_DAY_MASK 0x07000000 605#define RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB) 606#define RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK) 607#define RTC_SET_TIME_HOUR_MSB 21 608#define RTC_SET_TIME_HOUR_LSB 16 609#define RTC_SET_TIME_HOUR_MASK 0x003f0000 610#define RTC_SET_TIME_HOUR_GET(x) (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB) 611#define RTC_SET_TIME_HOUR_SET(x) (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK) 612#define RTC_SET_TIME_MINUTE_MSB 14 613#define RTC_SET_TIME_MINUTE_LSB 8 614#define RTC_SET_TIME_MINUTE_MASK 0x00007f00 615#define RTC_SET_TIME_MINUTE_GET(x) (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB) 616#define RTC_SET_TIME_MINUTE_SET(x) (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK) 617#define RTC_SET_TIME_SECOND_MSB 6 618#define RTC_SET_TIME_SECOND_LSB 0 619#define RTC_SET_TIME_SECOND_MASK 0x0000007f 620#define RTC_SET_TIME_SECOND_GET(x) (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB) 621#define RTC_SET_TIME_SECOND_SET(x) (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK) 622 623#define RTC_SET_DATE_ADDRESS 0x000000ac 624#define RTC_SET_DATE_OFFSET 0x000000ac 625#define RTC_SET_DATE_YEAR_MSB 23 626#define RTC_SET_DATE_YEAR_LSB 16 627#define RTC_SET_DATE_YEAR_MASK 0x00ff0000 628#define RTC_SET_DATE_YEAR_GET(x) (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB) 629#define RTC_SET_DATE_YEAR_SET(x) (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK) 630#define RTC_SET_DATE_MONTH_MSB 12 631#define RTC_SET_DATE_MONTH_LSB 8 632#define RTC_SET_DATE_MONTH_MASK 0x00001f00 633#define RTC_SET_DATE_MONTH_GET(x) (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB) 634#define RTC_SET_DATE_MONTH_SET(x) (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK) 635#define RTC_SET_DATE_MONTH_DAY_MSB 5 636#define RTC_SET_DATE_MONTH_DAY_LSB 0 637#define RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f 638#define RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB) 639#define RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK) 640 641#define RTC_SET_ALARM_ADDRESS 0x000000b0 642#define RTC_SET_ALARM_OFFSET 0x000000b0 643#define RTC_SET_ALARM_HOUR_MSB 21 644#define RTC_SET_ALARM_HOUR_LSB 16 645#define RTC_SET_ALARM_HOUR_MASK 0x003f0000 646#define RTC_SET_ALARM_HOUR_GET(x) (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB) 647#define RTC_SET_ALARM_HOUR_SET(x) (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK) 648#define RTC_SET_ALARM_MINUTE_MSB 14 649#define RTC_SET_ALARM_MINUTE_LSB 8 650#define RTC_SET_ALARM_MINUTE_MASK 0x00007f00 651#define RTC_SET_ALARM_MINUTE_GET(x) (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB) 652#define RTC_SET_ALARM_MINUTE_SET(x) (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK) 653#define RTC_SET_ALARM_SECOND_MSB 6 654#define RTC_SET_ALARM_SECOND_LSB 0 655#define RTC_SET_ALARM_SECOND_MASK 0x0000007f 656#define RTC_SET_ALARM_SECOND_GET(x) (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB) 657#define RTC_SET_ALARM_SECOND_SET(x) (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK) 658 659#define RTC_CONFIG_ADDRESS 0x000000b4 660#define RTC_CONFIG_OFFSET 0x000000b4 661#define RTC_CONFIG_BCD_MSB 2 662#define RTC_CONFIG_BCD_LSB 2 663#define RTC_CONFIG_BCD_MASK 0x00000004 664#define RTC_CONFIG_BCD_GET(x) (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB) 665#define RTC_CONFIG_BCD_SET(x) (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK) 666#define RTC_CONFIG_TWELVE_HOUR_MSB 1 667#define RTC_CONFIG_TWELVE_HOUR_LSB 1 668#define RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002 669#define RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB) 670#define RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK) 671#define RTC_CONFIG_DSE_MSB 0 672#define RTC_CONFIG_DSE_LSB 0 673#define RTC_CONFIG_DSE_MASK 0x00000001 674#define RTC_CONFIG_DSE_GET(x) (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB) 675#define RTC_CONFIG_DSE_SET(x) (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK) 676 677#define RTC_ALARM_STATUS_ADDRESS 0x000000b8 678#define RTC_ALARM_STATUS_OFFSET 0x000000b8 679#define RTC_ALARM_STATUS_ENABLE_MSB 1 680#define RTC_ALARM_STATUS_ENABLE_LSB 1 681#define RTC_ALARM_STATUS_ENABLE_MASK 0x00000002 682#define RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB) 683#define RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK) 684#define RTC_ALARM_STATUS_INTERRUPT_MSB 0 685#define RTC_ALARM_STATUS_INTERRUPT_LSB 0 686#define RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001 687#define RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB) 688#define RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK) 689 690#define UART_WAKEUP_ADDRESS 0x000000bc 691#define UART_WAKEUP_OFFSET 0x000000bc 692#define UART_WAKEUP_ENABLE_MSB 0 693#define UART_WAKEUP_ENABLE_LSB 0 694#define UART_WAKEUP_ENABLE_MASK 0x00000001 695#define UART_WAKEUP_ENABLE_GET(x) (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB) 696#define UART_WAKEUP_ENABLE_SET(x) (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK) 697 698#define RESET_CAUSE_ADDRESS 0x000000c0 699#define RESET_CAUSE_OFFSET 0x000000c0 700#define RESET_CAUSE_LAST_MSB 2 701#define RESET_CAUSE_LAST_LSB 0 702#define RESET_CAUSE_LAST_MASK 0x00000007 703#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB) 704#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK) 705 706#define SYSTEM_SLEEP_ADDRESS 0x000000c4 707#define SYSTEM_SLEEP_OFFSET 0x000000c4 708#define SYSTEM_SLEEP_HOST_IF_MSB 4 709#define SYSTEM_SLEEP_HOST_IF_LSB 4 710#define SYSTEM_SLEEP_HOST_IF_MASK 0x00000010 711#define SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB) 712#define SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK) 713#define SYSTEM_SLEEP_MBOX_MSB 3 714#define SYSTEM_SLEEP_MBOX_LSB 3 715#define SYSTEM_SLEEP_MBOX_MASK 0x00000008 716#define SYSTEM_SLEEP_MBOX_GET(x) (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB) 717#define SYSTEM_SLEEP_MBOX_SET(x) (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK) 718#define SYSTEM_SLEEP_MAC_IF_MSB 2 719#define SYSTEM_SLEEP_MAC_IF_LSB 2 720#define SYSTEM_SLEEP_MAC_IF_MASK 0x00000004 721#define SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB) 722#define SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK) 723#define SYSTEM_SLEEP_LIGHT_MSB 1 724#define SYSTEM_SLEEP_LIGHT_LSB 1 725#define SYSTEM_SLEEP_LIGHT_MASK 0x00000002 726#define SYSTEM_SLEEP_LIGHT_GET(x) (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB) 727#define SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK) 728#define SYSTEM_SLEEP_DISABLE_MSB 0 729#define SYSTEM_SLEEP_DISABLE_LSB 0 730#define SYSTEM_SLEEP_DISABLE_MASK 0x00000001 731#define SYSTEM_SLEEP_DISABLE_GET(x) (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB) 732#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK) 733 734#define SDIO_WRAPPER_ADDRESS 0x000000c8 735#define SDIO_WRAPPER_OFFSET 0x000000c8 736#define SDIO_WRAPPER_SLEEP_MSB 3 737#define SDIO_WRAPPER_SLEEP_LSB 3 738#define SDIO_WRAPPER_SLEEP_MASK 0x00000008 739#define SDIO_WRAPPER_SLEEP_GET(x) (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB) 740#define SDIO_WRAPPER_SLEEP_SET(x) (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK) 741#define SDIO_WRAPPER_WAKEUP_MSB 2 742#define SDIO_WRAPPER_WAKEUP_LSB 2 743#define SDIO_WRAPPER_WAKEUP_MASK 0x00000004 744#define SDIO_WRAPPER_WAKEUP_GET(x) (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB) 745#define SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK) 746#define SDIO_WRAPPER_SOC_ON_MSB 1 747#define SDIO_WRAPPER_SOC_ON_LSB 1 748#define SDIO_WRAPPER_SOC_ON_MASK 0x00000002 749#define SDIO_WRAPPER_SOC_ON_GET(x) (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB) 750#define SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK) 751#define SDIO_WRAPPER_ON_MSB 0 752#define SDIO_WRAPPER_ON_LSB 0 753#define SDIO_WRAPPER_ON_MASK 0x00000001 754#define SDIO_WRAPPER_ON_GET(x) (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB) 755#define SDIO_WRAPPER_ON_SET(x) (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK) 756 757#define MAC_SLEEP_CONTROL_ADDRESS 0x000000cc 758#define MAC_SLEEP_CONTROL_OFFSET 0x000000cc 759#define MAC_SLEEP_CONTROL_ENABLE_MSB 1 760#define MAC_SLEEP_CONTROL_ENABLE_LSB 0 761#define MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003 762#define MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB) 763#define MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK) 764 765#define KEEP_AWAKE_ADDRESS 0x000000d0 766#define KEEP_AWAKE_OFFSET 0x000000d0 767#define KEEP_AWAKE_COUNT_MSB 7 768#define KEEP_AWAKE_COUNT_LSB 0 769#define KEEP_AWAKE_COUNT_MASK 0x000000ff 770#define KEEP_AWAKE_COUNT_GET(x) (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB) 771#define KEEP_AWAKE_COUNT_SET(x) (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK) 772 773#define LPO_CAL_TIME_ADDRESS 0x000000d4 774#define LPO_CAL_TIME_OFFSET 0x000000d4 775#define LPO_CAL_TIME_LENGTH_MSB 13 776#define LPO_CAL_TIME_LENGTH_LSB 0 777#define LPO_CAL_TIME_LENGTH_MASK 0x00003fff 778#define LPO_CAL_TIME_LENGTH_GET(x) (((x) & LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB) 779#define LPO_CAL_TIME_LENGTH_SET(x) (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK) 780 781#define LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8 782#define LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8 783#define LPO_INIT_DIVIDEND_INT_VALUE_MSB 23 784#define LPO_INIT_DIVIDEND_INT_VALUE_LSB 0 785#define LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff 786#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB) 787#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) 788 789#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc 790#define LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc 791#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10 792#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0 793#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff 794#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) 795#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) 796 797#define LPO_CAL_ADDRESS 0x000000e0 798#define LPO_CAL_OFFSET 0x000000e0 799#define LPO_CAL_ENABLE_MSB 20 800#define LPO_CAL_ENABLE_LSB 20 801#define LPO_CAL_ENABLE_MASK 0x00100000 802#define LPO_CAL_ENABLE_GET(x) (((x) & LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB) 803#define LPO_CAL_ENABLE_SET(x) (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) 804#define LPO_CAL_COUNT_MSB 19 805#define LPO_CAL_COUNT_LSB 0 806#define LPO_CAL_COUNT_MASK 0x000fffff 807#define LPO_CAL_COUNT_GET(x) (((x) & LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB) 808#define LPO_CAL_COUNT_SET(x) (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK) 809 810#define LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4 811#define LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4 812#define LPO_CAL_TEST_CONTROL_ENABLE_MSB 5 813#define LPO_CAL_TEST_CONTROL_ENABLE_LSB 5 814#define LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020 815#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB) 816#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) 817#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4 818#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0 819#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f 820#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) 821#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) 822 823#define LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8 824#define LPO_CAL_TEST_STATUS_OFFSET 0x000000e8 825#define LPO_CAL_TEST_STATUS_READY_MSB 16 826#define LPO_CAL_TEST_STATUS_READY_LSB 16 827#define LPO_CAL_TEST_STATUS_READY_MASK 0x00010000 828#define LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB) 829#define LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK) 830#define LPO_CAL_TEST_STATUS_COUNT_MSB 15 831#define LPO_CAL_TEST_STATUS_COUNT_LSB 0 832#define LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff 833#define LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB) 834#define LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK) 835 836#define CHIP_ID_ADDRESS 0x000000ec 837#define CHIP_ID_OFFSET 0x000000ec 838#define CHIP_ID_DEVICE_ID_MSB 31 839#define CHIP_ID_DEVICE_ID_LSB 16 840#define CHIP_ID_DEVICE_ID_MASK 0xffff0000 841#define CHIP_ID_DEVICE_ID_GET(x) (((x) & CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB) 842#define CHIP_ID_DEVICE_ID_SET(x) (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK) 843#define CHIP_ID_CONFIG_ID_MSB 15 844#define CHIP_ID_CONFIG_ID_LSB 4 845#define CHIP_ID_CONFIG_ID_MASK 0x0000fff0 846#define CHIP_ID_CONFIG_ID_GET(x) (((x) & CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB) 847#define CHIP_ID_CONFIG_ID_SET(x) (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK) 848#define CHIP_ID_VERSION_ID_MSB 3 849#define CHIP_ID_VERSION_ID_LSB 0 850#define CHIP_ID_VERSION_ID_MASK 0x0000000f 851#define CHIP_ID_VERSION_ID_GET(x) (((x) & CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB) 852#define CHIP_ID_VERSION_ID_SET(x) (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK) 853 854#define DERIVED_RTC_CLK_ADDRESS 0x000000f0 855#define DERIVED_RTC_CLK_OFFSET 0x000000f0 856#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20 857#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20 858#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000 859#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) 860#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) 861#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18 862#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18 863#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000 864#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) 865#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) 866#define DERIVED_RTC_CLK_FORCE_MSB 17 867#define DERIVED_RTC_CLK_FORCE_LSB 16 868#define DERIVED_RTC_CLK_FORCE_MASK 0x00030000 869#define DERIVED_RTC_CLK_FORCE_GET(x) (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB) 870#define DERIVED_RTC_CLK_FORCE_SET(x) (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK) 871#define DERIVED_RTC_CLK_PERIOD_MSB 15 872#define DERIVED_RTC_CLK_PERIOD_LSB 1 873#define DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe 874#define DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB) 875#define DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK) 876 877#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4 878#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4 879#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21 880#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21 881#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000 882#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) 883#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) 884#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19 885#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0 886#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff 887#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) 888#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) 889 890#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8 891#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8 892#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15 893#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0 894#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff 895#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) 896#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) 897 898#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc 899#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc 900#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19 901#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0 902#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff 903#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB) 904#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK) 905 906#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100 907#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100 908#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31 909#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0 910#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff 911#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) 912#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) 913 914#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104 915#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104 916#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31 917#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0 918#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff 919#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) 920#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) 921 922#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108 923#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108 924#define MAC_PCU_SLP_MIB3_PENDING_MSB 1 925#define MAC_PCU_SLP_MIB3_PENDING_LSB 1 926#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002 927#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB) 928#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK) 929#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0 930#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0 931#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001 932#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB) 933#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) 934 935#define MAC_PCU_SLP_BEACON_ADDRESS 0x0000010c 936#define MAC_PCU_SLP_BEACON_OFFSET 0x0000010c 937#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24 938#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24 939#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000 940#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) 941#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) 942#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB 23 943#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB 0 944#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK 0x00ffffff 945#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) 946#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) 947 948#define POWER_REG_ADDRESS 0x00000110 949#define POWER_REG_OFFSET 0x00000110 950#define POWER_REG_VLVL_MSB 11 951#define POWER_REG_VLVL_LSB 8 952#define POWER_REG_VLVL_MASK 0x00000f00 953#define POWER_REG_VLVL_GET(x) (((x) & POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB) 954#define POWER_REG_VLVL_SET(x) (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK) 955#define POWER_REG_CPU_INT_ENABLE_MSB 7 956#define POWER_REG_CPU_INT_ENABLE_LSB 7 957#define POWER_REG_CPU_INT_ENABLE_MASK 0x00000080 958#define POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB) 959#define POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK) 960#define POWER_REG_WLAN_ISO_DIS_MSB 6 961#define POWER_REG_WLAN_ISO_DIS_LSB 6 962#define POWER_REG_WLAN_ISO_DIS_MASK 0x00000040 963#define POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB) 964#define POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK) 965#define POWER_REG_WLAN_ISO_CNTL_MSB 5 966#define POWER_REG_WLAN_ISO_CNTL_LSB 5 967#define POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020 968#define POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB) 969#define POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK) 970#define POWER_REG_RADIO_PWD_EN_MSB 4 971#define POWER_REG_RADIO_PWD_EN_LSB 4 972#define POWER_REG_RADIO_PWD_EN_MASK 0x00000010 973#define POWER_REG_RADIO_PWD_EN_GET(x) (((x) & POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB) 974#define POWER_REG_RADIO_PWD_EN_SET(x) (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK) 975#define POWER_REG_SOC_SCALE_EN_MSB 3 976#define POWER_REG_SOC_SCALE_EN_LSB 3 977#define POWER_REG_SOC_SCALE_EN_MASK 0x00000008 978#define POWER_REG_SOC_SCALE_EN_GET(x) (((x) & POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB) 979#define POWER_REG_SOC_SCALE_EN_SET(x) (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK) 980#define POWER_REG_WLAN_SCALE_EN_MSB 2 981#define POWER_REG_WLAN_SCALE_EN_LSB 2 982#define POWER_REG_WLAN_SCALE_EN_MASK 0x00000004 983#define POWER_REG_WLAN_SCALE_EN_GET(x) (((x) & POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB) 984#define POWER_REG_WLAN_SCALE_EN_SET(x) (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK) 985#define POWER_REG_WLAN_PWD_EN_MSB 1 986#define POWER_REG_WLAN_PWD_EN_LSB 1 987#define POWER_REG_WLAN_PWD_EN_MASK 0x00000002 988#define POWER_REG_WLAN_PWD_EN_GET(x) (((x) & POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB) 989#define POWER_REG_WLAN_PWD_EN_SET(x) (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK) 990#define POWER_REG_POWER_EN_MSB 0 991#define POWER_REG_POWER_EN_LSB 0 992#define POWER_REG_POWER_EN_MASK 0x00000001 993#define POWER_REG_POWER_EN_GET(x) (((x) & POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB) 994#define POWER_REG_POWER_EN_SET(x) (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK) 995 996#define CORE_CLK_CTRL_ADDRESS 0x00000114 997#define CORE_CLK_CTRL_OFFSET 0x00000114 998#define CORE_CLK_CTRL_DIV_MSB 2 999#define CORE_CLK_CTRL_DIV_LSB 0 1000#define CORE_CLK_CTRL_DIV_MASK 0x00000007
1001#define CORE_CLK_CTRL_DIV_GET(x) (((x) & CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB) 1002#define CORE_CLK_CTRL_DIV_SET(x) (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK) 1003 1004#define SDIO_SETUP_CIRCUIT_ADDRESS 0x00000120 1005#define SDIO_SETUP_CIRCUIT_OFFSET 0x00000120 1006#define SDIO_SETUP_CIRCUIT_VECTOR_MSB 7 1007#define SDIO_SETUP_CIRCUIT_VECTOR_LSB 0 1008#define SDIO_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff 1009#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB) 1010#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) 1011 1012#define SDIO_SETUP_CONFIG_ADDRESS 0x00000140 1013#define SDIO_SETUP_CONFIG_OFFSET 0x00000140 1014#define SDIO_SETUP_CONFIG_ENABLE_MSB 1 1015#define SDIO_SETUP_CONFIG_ENABLE_LSB 1 1016#define SDIO_SETUP_CONFIG_ENABLE_MASK 0x00000002 1017#define SDIO_SETUP_CONFIG_ENABLE_GET(x) (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB) 1018#define SDIO_SETUP_CONFIG_ENABLE_SET(x) (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK) 1019#define SDIO_SETUP_CONFIG_CLEAR_MSB 0 1020#define SDIO_SETUP_CONFIG_CLEAR_LSB 0 1021#define SDIO_SETUP_CONFIG_CLEAR_MASK 0x00000001 1022#define SDIO_SETUP_CONFIG_CLEAR_GET(x) (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB) 1023#define SDIO_SETUP_CONFIG_CLEAR_SET(x) (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK) 1024 1025#define CPU_SETUP_CONFIG_ADDRESS 0x00000144 1026#define CPU_SETUP_CONFIG_OFFSET 0x00000144 1027#define CPU_SETUP_CONFIG_ENABLE_MSB 1 1028#define CPU_SETUP_CONFIG_ENABLE_LSB 1 1029#define CPU_SETUP_CONFIG_ENABLE_MASK 0x00000002 1030#define CPU_SETUP_CONFIG_ENABLE_GET(x) (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB) 1031#define CPU_SETUP_CONFIG_ENABLE_SET(x) (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK) 1032#define CPU_SETUP_CONFIG_CLEAR_MSB 0 1033#define CPU_SETUP_CONFIG_CLEAR_LSB 0 1034#define CPU_SETUP_CONFIG_CLEAR_MASK 0x00000001 1035#define CPU_SETUP_CONFIG_CLEAR_GET(x) (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB) 1036#define CPU_SETUP_CONFIG_CLEAR_SET(x) (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK) 1037 1038#define CPU_SETUP_CIRCUIT_ADDRESS 0x00000160 1039#define CPU_SETUP_CIRCUIT_OFFSET 0x00000160 1040#define CPU_SETUP_CIRCUIT_VECTOR_MSB 7 1041#define CPU_SETUP_CIRCUIT_VECTOR_LSB 0 1042#define CPU_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff 1043#define CPU_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB) 1044#define CPU_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK) 1045 1046#define BB_SETUP_CONFIG_ADDRESS 0x00000180 1047#define BB_SETUP_CONFIG_OFFSET 0x00000180 1048#define BB_SETUP_CONFIG_ENABLE_MSB 1 1049#define BB_SETUP_CONFIG_ENABLE_LSB 1 1050#define BB_SETUP_CONFIG_ENABLE_MASK 0x00000002 1051#define BB_SETUP_CONFIG_ENABLE_GET(x) (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB) 1052#define BB_SETUP_CONFIG_ENABLE_SET(x) (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK) 1053#define BB_SETUP_CONFIG_CLEAR_MSB 0 1054#define BB_SETUP_CONFIG_CLEAR_LSB 0 1055#define BB_SETUP_CONFIG_CLEAR_MASK 0x00000001 1056#define BB_SETUP_CONFIG_CLEAR_GET(x) (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB) 1057#define BB_SETUP_CONFIG_CLEAR_SET(x) (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK) 1058 1059#define BB_SETUP_CIRCUIT_ADDRESS 0x000001a0 1060#define BB_SETUP_CIRCUIT_OFFSET 0x000001a0 1061#define BB_SETUP_CIRCUIT_VECTOR_MSB 7 1062#define BB_SETUP_CIRCUIT_VECTOR_LSB 0 1063#define BB_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff 1064#define BB_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB) 1065#define BB_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK) 1066 1067#define GPIO_WAKEUP_CONTROL_ADDRESS 0x000001c0 1068#define GPIO_WAKEUP_CONTROL_OFFSET 0x000001c0 1069#define GPIO_WAKEUP_CONTROL_ENABLE_MSB 0 1070#define GPIO_WAKEUP_CONTROL_ENABLE_LSB 0 1071#define GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001 1072#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB) 1073#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) 1074 1075 1076#ifndef __ASSEMBLER__ 1077 1078typedef struct rtc_reg_reg_s { 1079 volatile unsigned int reset_control; 1080 volatile unsigned int xtal_control; 1081 volatile unsigned int tcxo_detect; 1082 volatile unsigned int xtal_test; 1083 volatile unsigned int quadrature; 1084 volatile unsigned int pll_control; 1085 volatile unsigned int pll_settle; 1086 volatile unsigned int xtal_settle; 1087 volatile unsigned int cpu_clock; 1088 volatile unsigned int clock_out; 1089 volatile unsigned int clock_control; 1090 volatile unsigned int bias_override; 1091 volatile unsigned int wdt_control; 1092 volatile unsigned int wdt_status; 1093 volatile unsigned int wdt; 1094 volatile unsigned int wdt_count; 1095 volatile unsigned int wdt_reset; 1096 volatile unsigned int int_status; 1097 volatile unsigned int lf_timer0; 1098 volatile unsigned int lf_timer_count0; 1099 volatile unsigned int lf_timer_control0; 1100 volatile unsigned int lf_timer_status0; 1101 volatile unsigned int lf_timer1; 1102 volatile unsigned int lf_timer_count1; 1103 volatile unsigned int lf_timer_control1; 1104 volatile unsigned int lf_timer_status1; 1105 volatile unsigned int lf_timer2; 1106 volatile unsigned int lf_timer_count2; 1107 volatile unsigned int lf_timer_control2; 1108 volatile unsigned int lf_timer_status2; 1109 volatile unsigned int lf_timer3; 1110 volatile unsigned int lf_timer_count3; 1111 volatile unsigned int lf_timer_control3; 1112 volatile unsigned int lf_timer_status3; 1113 volatile unsigned int hf_timer; 1114 volatile unsigned int hf_timer_count; 1115 volatile unsigned int hf_lf_count; 1116 volatile unsigned int hf_timer_control; 1117 volatile unsigned int hf_timer_status; 1118 volatile unsigned int rtc_control; 1119 volatile unsigned int rtc_time; 1120 volatile unsigned int rtc_date; 1121 volatile unsigned int rtc_set_time; 1122 volatile unsigned int rtc_set_date; 1123 volatile unsigned int rtc_set_alarm; 1124 volatile unsigned int rtc_config; 1125 volatile unsigned int rtc_alarm_status; 1126 volatile unsigned int uart_wakeup; 1127 volatile unsigned int reset_cause; 1128 volatile unsigned int system_sleep; 1129 volatile unsigned int sdio_wrapper; 1130 volatile unsigned int mac_sleep_control; 1131 volatile unsigned int keep_awake; 1132 volatile unsigned int lpo_cal_time; 1133 volatile unsigned int lpo_init_dividend_int; 1134 volatile unsigned int lpo_init_dividend_fraction; 1135 volatile unsigned int lpo_cal; 1136 volatile unsigned int lpo_cal_test_control; 1137 volatile unsigned int lpo_cal_test_status; 1138 volatile unsigned int chip_id; 1139 volatile unsigned int derived_rtc_clk; 1140 volatile unsigned int mac_pcu_slp32_mode; 1141 volatile unsigned int mac_pcu_slp32_wake; 1142 volatile unsigned int mac_pcu_slp32_inc; 1143 volatile unsigned int mac_pcu_slp_mib1; 1144 volatile unsigned int mac_pcu_slp_mib2; 1145 volatile unsigned int mac_pcu_slp_mib3; 1146 volatile unsigned int mac_pcu_slp_beacon; 1147 volatile unsigned int power_reg; 1148 volatile unsigned int core_clk_ctrl; 1149 unsigned char pad0[8]; /* pad to 0x120 */ 1150 volatile unsigned int sdio_setup_circuit[8]; 1151 volatile unsigned int sdio_setup_config; 1152 volatile unsigned int cpu_setup_config; 1153 unsigned char pad1[24]; /* pad to 0x160 */ 1154 volatile unsigned int cpu_setup_circuit[8]; 1155 volatile unsigned int bb_setup_config; 1156 unsigned char pad2[28]; /* pad to 0x1a0 */ 1157 volatile unsigned int bb_setup_circuit[8]; 1158 volatile unsigned int gpio_wakeup_control; 1159} rtc_reg_reg_t; 1160 1161#endif /* __ASSEMBLER__ */ 1162 1163#endif /* _RTC_REG_H_ */ 1164