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35#ifndef __MGA_DRM_H__
36#define __MGA_DRM_H__
37
38#include "drm.h"
39
40
41
42
43
44#ifndef __MGA_SAREA_DEFINES__
45#define __MGA_SAREA_DEFINES__
46
47
48
49#define MGA_F 0x1
50#define MGA_A 0x2
51#define MGA_S 0x4
52#define MGA_T2 0x8
53
54#define MGA_WARP_TGZ 0
55#define MGA_WARP_TGZF (MGA_F)
56#define MGA_WARP_TGZA (MGA_A)
57#define MGA_WARP_TGZAF (MGA_F|MGA_A)
58#define MGA_WARP_TGZS (MGA_S)
59#define MGA_WARP_TGZSF (MGA_S|MGA_F)
60#define MGA_WARP_TGZSA (MGA_S|MGA_A)
61#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A)
62#define MGA_WARP_T2GZ (MGA_T2)
63#define MGA_WARP_T2GZF (MGA_T2|MGA_F)
64#define MGA_WARP_T2GZA (MGA_T2|MGA_A)
65#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F)
66#define MGA_WARP_T2GZS (MGA_T2|MGA_S)
67#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F)
68#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A)
69#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A)
70
71#define MGA_MAX_G200_PIPES 8
72#define MGA_MAX_G400_PIPES 16
73#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
74#define MGA_WARP_UCODE_SIZE 32768
75
76#define MGA_CARD_TYPE_G200 1
77#define MGA_CARD_TYPE_G400 2
78#define MGA_CARD_TYPE_G450 3
79#define MGA_CARD_TYPE_G550 4
80
81#define MGA_FRONT 0x1
82#define MGA_BACK 0x2
83#define MGA_DEPTH 0x4
84
85
86
87#define MGA_UPLOAD_CONTEXT 0x1
88#define MGA_UPLOAD_TEX0 0x2
89#define MGA_UPLOAD_TEX1 0x4
90#define MGA_UPLOAD_PIPE 0x8
91#define MGA_UPLOAD_TEX0IMAGE 0x10
92#define MGA_UPLOAD_TEX1IMAGE 0x20
93#define MGA_UPLOAD_2D 0x40
94#define MGA_WAIT_AGE 0x80
95#define MGA_UPLOAD_CLIPRECTS 0x100
96#if 0
97#define MGA_DMA_FLUSH 0x200
98
99#endif
100
101
102
103#define MGA_BUFFER_SIZE (1 << 16)
104#define MGA_NUM_BUFFERS 128
105
106
107
108#define MGA_NR_SAREA_CLIPRECTS 8
109
110
111
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115
116
117#define MGA_CARD_HEAP 0
118#define MGA_AGP_HEAP 1
119#define MGA_NR_TEX_HEAPS 2
120#define MGA_NR_TEX_REGIONS 16
121#define MGA_LOG_MIN_TEX_REGION_SIZE 16
122
123#define DRM_MGA_IDLE_RETRY 2048
124
125#endif
126
127
128
129typedef struct {
130 unsigned int dstorg;
131 unsigned int maccess;
132 unsigned int plnwt;
133 unsigned int dwgctl;
134 unsigned int alphactrl;
135 unsigned int fogcolor;
136 unsigned int wflag;
137 unsigned int tdualstage0;
138 unsigned int tdualstage1;
139 unsigned int fcol;
140 unsigned int stencil;
141 unsigned int stencilctl;
142} drm_mga_context_regs_t;
143
144
145
146typedef struct {
147 unsigned int pitch;
148} drm_mga_server_regs_t;
149
150
151
152typedef struct {
153 unsigned int texctl;
154 unsigned int texctl2;
155 unsigned int texfilter;
156 unsigned int texbordercol;
157 unsigned int texorg;
158 unsigned int texwidth;
159 unsigned int texheight;
160 unsigned int texorg1;
161 unsigned int texorg2;
162 unsigned int texorg3;
163 unsigned int texorg4;
164} drm_mga_texture_regs_t;
165
166
167
168typedef struct {
169 unsigned int head;
170 unsigned int wrap;
171} drm_mga_age_t;
172
173typedef struct _drm_mga_sarea {
174
175
176
177 drm_mga_context_regs_t context_state;
178 drm_mga_server_regs_t server_state;
179 drm_mga_texture_regs_t tex_state[2];
180 unsigned int warp_pipe;
181 unsigned int dirty;
182 unsigned int vertsize;
183
184
185
186 struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
187 unsigned int nbox;
188
189
190
191
192
193
194
195
196 unsigned int req_drawable;
197 unsigned int req_draw_buffer;
198
199 unsigned int exported_drawable;
200 unsigned int exported_index;
201 unsigned int exported_stamp;
202 unsigned int exported_buffers;
203 unsigned int exported_nfront;
204 unsigned int exported_nback;
205 int exported_back_x, exported_front_x, exported_w;
206 int exported_back_y, exported_front_y, exported_h;
207 struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
208
209
210
211 unsigned int status[4];
212 unsigned int last_wrap;
213
214 drm_mga_age_t last_frame;
215 unsigned int last_enqueue;
216 unsigned int last_dispatch;
217 unsigned int last_quiescent;
218
219
220
221 struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
222 unsigned int texAge[MGA_NR_TEX_HEAPS];
223
224
225
226 int ctxOwner;
227} drm_mga_sarea_t;
228
229
230
231
232#define DRM_MGA_INIT 0x00
233#define DRM_MGA_FLUSH 0x01
234#define DRM_MGA_RESET 0x02
235#define DRM_MGA_SWAP 0x03
236#define DRM_MGA_CLEAR 0x04
237#define DRM_MGA_VERTEX 0x05
238#define DRM_MGA_INDICES 0x06
239#define DRM_MGA_ILOAD 0x07
240#define DRM_MGA_BLIT 0x08
241#define DRM_MGA_GETPARAM 0x09
242
243
244
245
246#define DRM_MGA_SET_FENCE 0x0a
247#define DRM_MGA_WAIT_FENCE 0x0b
248#define DRM_MGA_DMA_BOOTSTRAP 0x0c
249
250#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
251#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock)
252#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
253#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP)
254#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
255#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
256#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
257#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
258#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
259#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
260#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
261#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
262#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
263
264typedef struct _drm_mga_warp_index {
265 int installed;
266 unsigned long phys_addr;
267 int size;
268} drm_mga_warp_index_t;
269
270typedef struct drm_mga_init {
271 enum {
272 MGA_INIT_DMA = 0x01,
273 MGA_CLEANUP_DMA = 0x02
274 } func;
275
276 unsigned long sarea_priv_offset;
277
278 int chipset;
279 int sgram;
280
281 unsigned int maccess;
282
283 unsigned int fb_cpp;
284 unsigned int front_offset, front_pitch;
285 unsigned int back_offset, back_pitch;
286
287 unsigned int depth_cpp;
288 unsigned int depth_offset, depth_pitch;
289
290 unsigned int texture_offset[MGA_NR_TEX_HEAPS];
291 unsigned int texture_size[MGA_NR_TEX_HEAPS];
292
293 unsigned long fb_offset;
294 unsigned long mmio_offset;
295 unsigned long status_offset;
296 unsigned long warp_offset;
297 unsigned long primary_offset;
298 unsigned long buffers_offset;
299} drm_mga_init_t;
300
301typedef struct drm_mga_dma_bootstrap {
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313
314 unsigned long texture_handle;
315 __u32 texture_size;
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323
324 __u32 primary_size;
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333
334 __u32 secondary_bin_count;
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342
343 __u32 secondary_bin_size;
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354
355 __u32 agp_mode;
356
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359
360 __u8 agp_size;
361} drm_mga_dma_bootstrap_t;
362
363typedef struct drm_mga_clear {
364 unsigned int flags;
365 unsigned int clear_color;
366 unsigned int clear_depth;
367 unsigned int color_mask;
368 unsigned int depth_mask;
369} drm_mga_clear_t;
370
371typedef struct drm_mga_vertex {
372 int idx;
373 int used;
374 int discard;
375} drm_mga_vertex_t;
376
377typedef struct drm_mga_indices {
378 int idx;
379 unsigned int start;
380 unsigned int end;
381 int discard;
382} drm_mga_indices_t;
383
384typedef struct drm_mga_iload {
385 int idx;
386 unsigned int dstorg;
387 unsigned int length;
388} drm_mga_iload_t;
389
390typedef struct _drm_mga_blit {
391 unsigned int planemask;
392 unsigned int srcorg;
393 unsigned int dstorg;
394 int src_pitch, dst_pitch;
395 int delta_sx, delta_sy;
396 int delta_dx, delta_dy;
397 int height, ydir;
398 int source_pitch, dest_pitch;
399} drm_mga_blit_t;
400
401
402
403
404#define MGA_PARAM_IRQ_NR 1
405
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411
412#define MGA_PARAM_CARD_TYPE 2
413
414typedef struct drm_mga_getparam {
415 int param;
416 void __user *value;
417} drm_mga_getparam_t;
418
419#endif
420