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15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/memory.h>
19#include <linux/platform_device.h>
20#include <linux/mtd/physmap.h>
21#include <linux/mtd/nand.h>
22#include <linux/gpio.h>
23
24#include <mach/hardware.h>
25#include <mach/irqs.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/time.h>
29#include <asm/mach/map.h>
30#include <mach/common.h>
31#include <asm/page.h>
32#include <asm/setup.h>
33#include <mach/iomux-mx3.h>
34
35#include "devices-imx31.h"
36
37
38#define QONG_FPGA_VERSION(major, minor, rev) \
39 (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
40
41#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
42#define QONG_FPGA_PERIPH_SIZE (1 << 24)
43
44#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
45#define QONG_FPGA_CTRL_SIZE 0x10
46
47#define QONG_FPGA_CTRL_VERSION 0x00
48
49#define QONG_DNET_ID 1
50#define QONG_DNET_BASEADDR \
51 (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
52#define QONG_DNET_SIZE 0x00001000
53
54#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
55
56static const struct imxuart_platform_data uart_pdata __initconst = {
57 .flags = IMXUART_HAVE_RTSCTS,
58};
59
60static int uart_pins[] = {
61 MX31_PIN_CTS1__CTS1,
62 MX31_PIN_RTS1__RTS1,
63 MX31_PIN_TXD1__TXD1,
64 MX31_PIN_RXD1__RXD1
65};
66
67static inline void __init mxc_init_imx_uart(void)
68{
69 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
70 "uart-0");
71 imx31_add_imx_uart0(&uart_pdata);
72}
73
74static struct resource dnet_resources[] = {
75 {
76 .name = "dnet-memory",
77 .start = QONG_DNET_BASEADDR,
78 .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
79 .flags = IORESOURCE_MEM,
80 }, {
81 .start = QONG_FPGA_IRQ,
82 .end = QONG_FPGA_IRQ,
83 .flags = IORESOURCE_IRQ,
84 },
85};
86
87static struct platform_device dnet_device = {
88 .name = "dnet",
89 .id = -1,
90 .num_resources = ARRAY_SIZE(dnet_resources),
91 .resource = dnet_resources,
92};
93
94static int __init qong_init_dnet(void)
95{
96 int ret;
97
98 ret = platform_device_register(&dnet_device);
99 return ret;
100}
101
102
103
104static struct physmap_flash_data qong_flash_data = {
105 .width = 2,
106};
107
108static struct resource qong_flash_resource = {
109 .start = MX31_CS0_BASE_ADDR,
110 .end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
111 .flags = IORESOURCE_MEM,
112};
113
114static struct platform_device qong_nor_mtd_device = {
115 .name = "physmap-flash",
116 .id = 0,
117 .dev = {
118 .platform_data = &qong_flash_data,
119 },
120 .resource = &qong_flash_resource,
121 .num_resources = 1,
122};
123
124static void qong_init_nor_mtd(void)
125{
126 (void)platform_device_register(&qong_nor_mtd_device);
127}
128
129
130
131
132static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
133{
134 struct nand_chip *nand_chip = mtd->priv;
135
136 if (cmd == NAND_CMD_NONE)
137 return;
138
139 if (ctrl & NAND_CLE)
140 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
141 else
142 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
143}
144
145
146
147
148static int qong_nand_device_ready(struct mtd_info *mtd)
149{
150 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
151}
152
153static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
154{
155 if (chip >= 0)
156 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
157 else
158 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
159}
160
161static struct platform_nand_data qong_nand_data = {
162 .chip = {
163 .nr_chips = 1,
164 .chip_delay = 20,
165 .options = 0,
166 },
167 .ctrl = {
168 .cmd_ctrl = qong_nand_cmd_ctrl,
169 .dev_ready = qong_nand_device_ready,
170 .select_chip = qong_nand_select_chip,
171 }
172};
173
174static struct resource qong_nand_resource = {
175 .start = MX31_CS3_BASE_ADDR,
176 .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
177 .flags = IORESOURCE_MEM,
178};
179
180static struct platform_device qong_nand_device = {
181 .name = "gen_nand",
182 .id = -1,
183 .dev = {
184 .platform_data = &qong_nand_data,
185 },
186 .num_resources = 1,
187 .resource = &qong_nand_resource,
188};
189
190static void __init qong_init_nand_mtd(void)
191{
192
193 mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
194 mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
195
196
197 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
198 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
199 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
200
201
202 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
203 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
204 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
205
206
207 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
208 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
209 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
210
211 platform_device_register(&qong_nand_device);
212}
213
214static void __init qong_init_fpga(void)
215{
216 void __iomem *regs;
217 u32 fpga_ver;
218
219 regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
220 if (!regs) {
221 printk(KERN_ERR "%s: failed to map registers, aborting.\n",
222 __func__);
223 return;
224 }
225
226 fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
227 iounmap(regs);
228 printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
229 (fpga_ver & 0xF000) >> 12,
230 (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
231 if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
232 printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
233 "devices won't be registered!\n");
234 return;
235 }
236
237
238 qong_init_nand_mtd();
239 qong_init_dnet();
240}
241
242
243
244
245static void __init qong_init(void)
246{
247 mxc_init_imx_uart();
248 qong_init_nor_mtd();
249 qong_init_fpga();
250}
251
252static void __init qong_timer_init(void)
253{
254 mx31_clocks_init(26000000);
255}
256
257static struct sys_timer qong_timer = {
258 .init = qong_timer_init,
259};
260
261MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
262
263 .boot_params = MX3x_PHYS_OFFSET + 0x100,
264 .map_io = mx31_map_io,
265 .init_early = imx31_init_early,
266 .init_irq = mx31_init_irq,
267 .timer = &qong_timer,
268 .init_machine = qong_init,
269MACHINE_END
270
