LXR linux/arch/arm/mach-mxs/include/mach/mxs.h

   1/*
   2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License as published by
   6 * the Free Software Foundation; either version 2 of the License, or
   7 * (at your option) any later version.
   8 *
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 * GNU General Public License for more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along
  15 * with this program; if not, write to the Free Software Foundation, Inc.,
  16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17 */
  18
  19#ifndef __MACH_MXS_H__
  20#define __MACH_MXS_H__
  21
  22#ifndef __ASSEMBLER__
  23#include <linux/io.h>
  24#endif
  25#include <asm/mach-types.h>
  26#include <mach/hardware.h>
  27
  28/*
  29 * MXS CPU types
  30 */
  31#define cpu_is_mx23()           (                                       \
  32                machine_is_mx23evk() ||                                 \
  33                0)
  34#define cpu_is_mx28()           (                                       \
  35                machine_is_mx28evk() ||                                 \
  36                machine_is_tx28() ||                                    \
  37                0)
  38
  39/*
  40 * IO addresses common to MXS-based
  41 */
  42#define MXS_IO_BASE_ADDR                0x80000000
  43#define MXS_IO_SIZE                     SZ_1M
  44
  45#define MXS_ICOLL_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x000000)
  46#define MXS_APBH_DMA_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x004000)
  47#define MXS_BCH_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x00a000)
  48#define MXS_GPMI_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x00c000)
  49#define MXS_PINCTRL_BASE_ADDR           (MXS_IO_BASE_ADDR + 0x018000)
  50#define MXS_DIGCTL_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x01c000)
  51#define MXS_APBX_DMA_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x024000)
  52#define MXS_DCP_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x028000)
  53#define MXS_PXP_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x02a000)
  54#define MXS_OCOTP_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x02c000)
  55#define MXS_AXI_AHB0_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x02e000)
  56#define MXS_LCDIF_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x030000)
  57#define MXS_CLKCTRL_BASE_ADDR           (MXS_IO_BASE_ADDR + 0x040000)
  58#define MXS_SAIF0_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x042000)
  59#define MXS_POWER_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x044000)
  60#define MXS_SAIF1_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x046000)
  61#define MXS_LRADC_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x050000)
  62#define MXS_SPDIF_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x054000)
  63#define MXS_I2C0_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x058000)
  64#define MXS_PWM_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x064000)
  65#define MXS_TIMROT_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x068000)
  66#define MXS_AUART1_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x06c000)
  67#define MXS_AUART2_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x06e000)
  68#define MXS_DRAM_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x0e0000)
  69
  70/*
  71 * It maps the whole address space to [0xf4000000, 0xf50fffff].
  72 *
  73 *      OCRAM   0x00000000+0x020000     ->      0xf4000000+0x020000
  74 *      IO      0x80000000+0x100000     ->      0xf5000000+0x100000
  75 */
  76#define MXS_IO_P2V(x)   (0xf4000000 +                                   \
  77                        (((x) & 0x80000000) >> 7) +                     \
  78                        (((x) & 0x000fffff)))
  79
  80#define MXS_IO_ADDRESS(x)       IOMEM(MXS_IO_P2V(x))
  81
  82#define mxs_map_entry(soc, name, _type) {                               \
  83        .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),      \
  84        .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR),           \
  85        .length = soc ## _ ## name ## _SIZE,                            \
  86        .type = _type,                                                  \
  87}
  88
  89#define MXS_SET_ADDR            0x4
  90#define MXS_CLR_ADDR            0x8
  91#define MXS_TOG_ADDR            0xc
  92
  93#ifndef __ASSEMBLER__
  94static inline void __mxs_setl(u32 mask, void __iomem *reg)
  95{
  96        __raw_writel(mask, reg + MXS_SET_ADDR);
  97}
  98
  99static inline void __mxs_clrl(u32 mask, void __iomem *reg)
 100{
 101        __raw_writel(mask, reg + MXS_CLR_ADDR);
 102}
 103
 104static inline void __mxs_togl(u32 mask, void __iomem *reg)
 105{
 106        __raw_writel(mask, reg + MXS_TOG_ADDR);
 107}
 108#endif
 109
 110#endif /* __MACH_MXS_H__ */
 111