LXR linux/arch/arm/mach-tegra/common.c

   1/*
   2 * arch/arm/mach-tegra/board-harmony.c
   3 *
   4 * Copyright (C) 2010 Google, Inc.
   5 *
   6 * Author:
   7 *      Colin Cross <ccross@android.com>
   8 *
   9 * This software is licensed under the terms of the GNU General Public
  10 * License version 2, as published by the Free Software Foundation, and
  11 * may be copied, distributed, and modified under those terms.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 */
  19
  20#include <linux/init.h>
  21#include <linux/io.h>
  22#include <linux/clk.h>
  23#include <linux/delay.h>
  24
  25#include <asm/hardware/cache-l2x0.h>
  26
  27#include <mach/iomap.h>
  28#include <mach/system.h>
  29
  30#include "board.h"
  31#include "clock.h"
  32#include "fuse.h"
  33
  34void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset;
  35
  36void tegra_assert_system_reset(char mode, const char *cmd)
  37{
  38        void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04);
  39        u32 reg;
  40
  41        /* use *_related to avoid spinlock since caches are off */
  42        reg = readl_relaxed(reset);
  43        reg |= 0x04;
  44        writel_relaxed(reg, reset);
  45}
  46
  47static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
  48        /* name         parent          rate            enabled */
  49        { "clk_m",      NULL,           0,              true },
  50        { "pll_p",      "clk_m",        216000000,      true },
  51        { "pll_p_out1", "pll_p",        28800000,       true },
  52        { "pll_p_out2", "pll_p",        48000000,       true },
  53        { "pll_p_out3", "pll_p",        72000000,       true },
  54        { "pll_p_out4", "pll_p",        108000000,      true },
  55        { "sclk",       "pll_p_out4",   108000000,      true },
  56        { "hclk",       "sclk",         108000000,      true },
  57        { "pclk",       "hclk",         54000000,       true },
  58        { "csite",      NULL,           0,              true },
  59        { "emc",        NULL,           0,              true },
  60        { "cpu",        NULL,           0,              true },
  61        { NULL,         NULL,           0,              0},
  62};
  63
  64void __init tegra_init_cache(void)
  65{
  66#ifdef CONFIG_CACHE_L2X0
  67        void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
  68
  69        writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
  70        writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
  71
  72        l2x0_init(p, 0x6C080001, 0x8200c3fe);
  73#endif
  74
  75}
  76
  77void __init tegra_init_early(void)
  78{
  79        tegra_init_fuse();
  80        tegra_init_clock();
  81        tegra_clk_init_from_table(common_clk_init_table);
  82        tegra_init_cache();
  83}
  84