1config FRV
2 bool
3 default y
4 select HAVE_IDE
5 select HAVE_ARCH_TRACEHOOK
6 select HAVE_IRQ_WORK
7 select HAVE_PERF_EVENTS
8 select HAVE_GENERIC_HARDIRQS
9 select GENERIC_IRQ_SHOW
10
11config ZONE_DMA
12 bool
13 default y
14
15config RWSEM_GENERIC_SPINLOCK
16 bool
17 default y
18
19config RWSEM_XCHGADD_ALGORITHM
20 bool
21
22config GENERIC_HWEIGHT
23 bool
24 default y
25
26config GENERIC_CALIBRATE_DELAY
27 bool
28 default n
29
30config TIME_LOW_RES
31 bool
32 default y
33
34config QUICKLIST
35 bool
36 default y
37
38config ARCH_HAS_ILOG2_U32
39 bool
40 default y
41
42config ARCH_HAS_ILOG2_U64
43 bool
44 default y
45
46config HZ
47 int
48 default 1000
49
50source "init/Kconfig"
51
52source "kernel/Kconfig.freezer"
53
54
55menu "Fujitsu FR-V system setup"
56
57config MMU
58 bool "MMU support"
59 help
60 This options switches on and off support for the FR-V MMU
61 (effectively switching between vmlinux and uClinux). Not all FR-V
62 CPUs support this. Currently only the FR451 has a sufficiently
63 featured MMU.
64
65config FRV_OUTOFLINE_ATOMIC_OPS
66 bool "Out-of-line the FRV atomic operations"
67 default n
68 help
69 Setting this option causes the FR-V atomic operations to be mostly
70 implemented out-of-line.
71
72 See Documentation/frv/atomic-ops.txt for more information.
73
74config HIGHMEM
75 bool "High memory support"
76 depends on MMU
77 default y
78 help
79 If you wish to use more than 256MB of memory with your MMU based
80 system, you will need to select this option. The kernel can only see
81 the memory between 0xC0000000 and 0xD0000000 directly... everything
82 else must be kmapped.
83
84 The arch is, however, capable of supporting up to 3GB of SDRAM.
85
86config HIGHPTE
87 bool "Allocate page tables in highmem"
88 depends on HIGHMEM
89 default y
90 help
91 The VM uses one page of memory for each page table. For systems
92 with a lot of RAM, this can be wasteful of precious low memory.
93 Setting this option will put user-space page tables in high memory.
94
95source "mm/Kconfig"
96
97choice
98 prompt "uClinux kernel load address"
99 depends on !MMU
100 default UCPAGE_OFFSET_C0000000
101 help
102 This option sets the base address for the uClinux kernel. The kernel
103 will rearrange the SDRAM layout to start at this address, and move
104 itself to start there. It must be greater than 0, and it must be
105 sufficiently less than 0xE0000000 that the SDRAM does not intersect
106 the I/O region.
107
108 The base address must also be aligned such that the SDRAM controller
109 can decode it. For instance, a 512MB SDRAM bank must be 512MB aligned.
110
111config UCPAGE_OFFSET_20000000
112 bool "0x20000000"
113
114config UCPAGE_OFFSET_40000000
115 bool "0x40000000"
116
117config UCPAGE_OFFSET_60000000
118 bool "0x60000000"
119
120config UCPAGE_OFFSET_80000000
121 bool "0x80000000"
122
123config UCPAGE_OFFSET_A0000000
124 bool "0xA0000000"
125
126config UCPAGE_OFFSET_C0000000
127 bool "0xC0000000 (Recommended)"
128
129endchoice
130
131config PAGE_OFFSET
132 hex
133 default 0x20000000 if UCPAGE_OFFSET_20000000
134 default 0x40000000 if UCPAGE_OFFSET_40000000
135 default 0x60000000 if UCPAGE_OFFSET_60000000
136 default 0x80000000 if UCPAGE_OFFSET_80000000
137 default 0xA0000000 if UCPAGE_OFFSET_A0000000
138 default 0xC0000000
139
140config PROTECT_KERNEL
141 bool "Protect core kernel against userspace"
142 depends on !MMU
143 default y
144 help
145 Selecting this option causes the uClinux kernel to change the
146 permittivity of DAMPR register covering the core kernel image to
147 prevent userspace accessing the underlying memory directly.
148
149choice
150 prompt "CPU Caching mode"
151 default FRV_DEFL_CACHE_WBACK
152 help
153 This option determines the default caching mode for the kernel.
154
155 Write-Back caching mode involves the all reads and writes causing
156 the affected cacheline to be read into the cache first before being
157 operated upon. Memory is not then updated by a write until the cache
158 is filled and a cacheline needs to be displaced from the cache to
159 make room. Only at that point is it written back.
160
161 Write-Behind caching is similar to Write-Back caching, except that a
162 write won't fetch a cacheline into the cache if there isn't already
163 one there; it will write directly to memory instead.
164
165 Write-Through caching only fetches cachelines from memory on a
166 read. Writes always get written directly to memory. If the affected
167 cacheline is also in cache, it will be updated too.
168
169 The final option is to turn of caching entirely.
170
171 Note that not all CPUs support Write-Behind caching. If the CPU on
172 which the kernel is running doesn't, it'll fall back to Write-Back
173 caching.
174
175config FRV_DEFL_CACHE_WBACK
176 bool "Write-Back"
177
178config FRV_DEFL_CACHE_WBEHIND
179 bool "Write-Behind"
180
181config FRV_DEFL_CACHE_WTHRU
182 bool "Write-Through"
183
184config FRV_DEFL_CACHE_DISABLED
185 bool "Disabled"
186
187endchoice
188
189menu "CPU core support"
190
191config CPU_FR401
192 bool "Include FR401 core support"
193 depends on !MMU
194 default y
195 help
196 This enables support for the FR401, FR401A and FR403 CPUs
197
198config CPU_FR405
199 bool "Include FR405 core support"
200 depends on !MMU
201 default y
202 help
203 This enables support for the FR405 CPU
204
205config CPU_FR451
206 bool "Include FR451 core support"
207 default y
208 help
209 This enables support for the FR451 CPU
210
211config CPU_FR451_COMPILE
212 bool "Specifically compile for FR451 core"
213 depends on CPU_FR451 && !CPU_FR401 && !CPU_FR405 && !CPU_FR551
214 default y
215 help
216 This causes appropriate flags to be passed to the compiler to
217 optimise for the FR451 CPU
218
219config CPU_FR551
220 bool "Include FR551 core support"
221 depends on !MMU
222 default y
223 help
224 This enables support for the FR555 CPU
225
226config CPU_FR551_COMPILE
227 bool "Specifically compile for FR551 core"
228 depends on CPU_FR551 && !CPU_FR401 && !CPU_FR405 && !CPU_FR451
229 default y
230 help
231 This causes appropriate flags to be passed to the compiler to
232 optimise for the FR555 CPU
233
234config FRV_L1_CACHE_SHIFT
235 int
236 default "5" if CPU_FR401 || CPU_FR405 || CPU_FR451
237 default "6" if CPU_FR551
238
239endmenu
240
241choice
242 prompt "System support"
243 default MB93091_VDK
244
245config MB93091_VDK
246 bool "MB93091 CPU board with or without motherboard"
247
248config MB93093_PDK
249 bool "MB93093 PDK unit"
250
251endchoice
252
253if MB93091_VDK
254choice
255 prompt "Motherboard support"
256 default MB93090_MB00
257
258config MB93090_MB00
259 bool "Use the MB93090-MB00 motherboard"
260 help
261 Select this option if the MB93091 CPU board is going to be used with
262 a MB93090-MB00 VDK motherboard
263
264config MB93091_NO_MB
265 bool "Use standalone"
266 help
267 Select this option if the MB93091 CPU board is going to be used
268 without a motherboard
269
270endchoice
271endif
272
273config FUJITSU_MB93493
274 bool "MB93493 Multimedia chip"
275 help
276 Select this option if the MB93493 multimedia chip is going to be
277 used.
278
279choice
280 prompt "GP-Relative data support"
281 default GPREL_DATA_8
282 help
283 This option controls what data, if any, should be placed in the GP
284 relative data sections. Using this means that the compiler can
285 generate accesses to the data using GR16-relative addressing which
286 is faster than absolute instructions and saves space (2 instructions
287 per access).
288
289 However, the GPREL region is limited in size because the immediate
290 value used in the load and store instructions is limited to a 12-bit
291 signed number.
292
293 So if the linker starts complaining that accesses to GPREL data are
294 out of range, try changing this option from the default.
295
296 Note that modules will always be compiled with this feature disabled
297 as the module data will not be in range of the GP base address.
298
299config GPREL_DATA_8
300 bool "Put data objects of up to 8 bytes into GP-REL"
301
302config GPREL_DATA_4
303 bool "Put data objects of up to 4 bytes into GP-REL"
304
305config GPREL_DATA_NONE
306 bool "Don't use GP-REL"
307
308endchoice
309
310config FRV_ONCPU_SERIAL
311 bool "Use on-CPU serial ports"
312 select SERIAL_8250
313 default y
314
315config PCI
316 bool "Use PCI"
317 depends on MB93090_MB00
318 default y
319 help
320 Some FR-V systems (such as the MB93090-MB00 VDK) have PCI
321 onboard. If you have one of these boards and you wish to use the PCI
322 facilities, say Y here.
323
324config RESERVE_DMA_COHERENT
325 bool "Reserve DMA coherent memory"
326 depends on PCI && !MMU
327 default y
328 help
329 Many PCI drivers require access to uncached memory for DMA device
330 communications (such as is done with some Ethernet buffer rings). If
331 a fully featured MMU is available, this can be done through page
332 table settings, but if not, a region has to be set aside and marked
333 with a special DAMPR register.
334
335 Setting this option causes uClinux to set aside a portion of the
336 available memory for use in this manner. The memory will then be
337 unavailable for normal kernel use.
338
339source "drivers/pci/Kconfig"
340
341source "drivers/pcmcia/Kconfig"
342
343
344
345
346
347
348
349
350
351
352
353menu "Power management options"
354
355config ARCH_SUSPEND_POSSIBLE
356 def_bool y
357
358source kernel/power/Kconfig
359endmenu
360
361endmenu
362
363
364menu "Executable formats"
365
366source "fs/Kconfig.binfmt"
367
368endmenu
369
370source "net/Kconfig"
371
372source "drivers/Kconfig"
373
374source "fs/Kconfig"
375
376source "arch/frv/Kconfig.debug"
377
378source "security/Kconfig"
379
380source "crypto/Kconfig"
381
382source "lib/Kconfig"
383
