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16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/param.h>
19#include <linux/string.h>
20#include <linux/ioport.h>
21#include <linux/device.h>
22#include <linux/delay.h>
23
24#include <linux/fs_enet_pd.h>
25#include <linux/fs_uart_pd.h>
26#include <linux/fsl_devices.h>
27#include <linux/mii.h>
28#include <linux/of_platform.h>
29
30#include <asm/delay.h>
31#include <asm/io.h>
32#include <asm/machdep.h>
33#include <asm/page.h>
34#include <asm/processor.h>
35#include <asm/system.h>
36#include <asm/time.h>
37#include <asm/mpc8xx.h>
38#include <asm/8xx_immap.h>
39#include <asm/cpm1.h>
40#include <asm/fs_pd.h>
41#include <asm/udbg.h>
42
43#include "mpc885ads.h"
44#include "mpc8xx.h"
45
46static u32 __iomem *bcsr, *bcsr5;
47
48#ifdef CONFIG_PCMCIA_M8XX
49static void pcmcia_hw_setup(int slot, int enable)
50{
51 if (enable)
52 clrbits32(&bcsr[1], BCSR1_PCCEN);
53 else
54 setbits32(&bcsr[1], BCSR1_PCCEN);
55}
56
57static int pcmcia_set_voltage(int slot, int vcc, int vpp)
58{
59 u32 reg = 0;
60
61 switch (vcc) {
62 case 0:
63 break;
64 case 33:
65 reg |= BCSR1_PCCVCC0;
66 break;
67 case 50:
68 reg |= BCSR1_PCCVCC1;
69 break;
70 default:
71 return 1;
72 }
73
74 switch (vpp) {
75 case 0:
76 break;
77 case 33:
78 case 50:
79 if (vcc == vpp)
80 reg |= BCSR1_PCCVPP1;
81 else
82 return 1;
83 break;
84 case 120:
85 if ((vcc == 33) || (vcc == 50))
86 reg |= BCSR1_PCCVPP0;
87 else
88 return 1;
89 default:
90 return 1;
91 }
92
93
94 clrbits32(&bcsr[1], 0x00610000);
95
96
97 setbits32(&bcsr[1], reg);
98
99 return 0;
100}
101#endif
102
103struct cpm_pin {
104 int port, pin, flags;
105};
106
107static struct cpm_pin mpc885ads_pins[] = {
108
109 {CPM_PORTB, 24, CPM_PIN_INPUT},
110 {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
111
112
113#ifndef CONFIG_MPC8xx_SECOND_ETH_FEC2
114 {CPM_PORTE, 21, CPM_PIN_INPUT},
115 {CPM_PORTE, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
116#endif
117
118
119 {CPM_PORTA, 9, CPM_PIN_INPUT},
120 {CPM_PORTA, 8, CPM_PIN_INPUT},
121 {CPM_PORTC, 4, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO},
122 {CPM_PORTC, 5, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO},
123 {CPM_PORTE, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
124 {CPM_PORTE, 17, CPM_PIN_INPUT},
125 {CPM_PORTE, 16, CPM_PIN_INPUT},
126
127
128 {CPM_PORTA, 0, CPM_PIN_INPUT},
129 {CPM_PORTA, 1, CPM_PIN_INPUT},
130 {CPM_PORTA, 2, CPM_PIN_INPUT},
131 {CPM_PORTA, 3, CPM_PIN_INPUT},
132 {CPM_PORTA, 4, CPM_PIN_OUTPUT},
133 {CPM_PORTA, 10, CPM_PIN_OUTPUT},
134 {CPM_PORTA, 11, CPM_PIN_OUTPUT},
135 {CPM_PORTB, 19, CPM_PIN_INPUT},
136 {CPM_PORTB, 31, CPM_PIN_INPUT},
137 {CPM_PORTC, 12, CPM_PIN_INPUT},
138 {CPM_PORTC, 13, CPM_PIN_INPUT},
139 {CPM_PORTE, 30, CPM_PIN_OUTPUT},
140 {CPM_PORTE, 31, CPM_PIN_OUTPUT},
141
142
143#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
144 {CPM_PORTE, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
145 {CPM_PORTE, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
146 {CPM_PORTE, 16, CPM_PIN_OUTPUT},
147 {CPM_PORTE, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
148 {CPM_PORTE, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
149 {CPM_PORTE, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
150 {CPM_PORTE, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
151 {CPM_PORTE, 21, CPM_PIN_OUTPUT},
152 {CPM_PORTE, 22, CPM_PIN_OUTPUT},
153 {CPM_PORTE, 23, CPM_PIN_OUTPUT},
154 {CPM_PORTE, 24, CPM_PIN_OUTPUT},
155 {CPM_PORTE, 25, CPM_PIN_OUTPUT},
156 {CPM_PORTE, 26, CPM_PIN_OUTPUT},
157 {CPM_PORTE, 27, CPM_PIN_OUTPUT},
158 {CPM_PORTE, 28, CPM_PIN_OUTPUT},
159 {CPM_PORTE, 29, CPM_PIN_OUTPUT},
160#endif
161
162 {CPM_PORTB, 26, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
163 {CPM_PORTB, 27, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
164};
165
166static void __init init_ioports(void)
167{
168 int i;
169
170 for (i = 0; i < ARRAY_SIZE(mpc885ads_pins); i++) {
171 struct cpm_pin *pin = &mpc885ads_pins[i];
172 cpm1_set_pin(pin->port, pin->pin, pin->flags);
173 }
174
175 cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
176 cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
177 cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_TX);
178 cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX);
179
180
181 clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
182}
183
184static void __init mpc885ads_setup_arch(void)
185{
186 struct device_node *np;
187
188 cpm_reset();
189 init_ioports();
190
191 np = of_find_compatible_node(NULL, NULL, "fsl,mpc885ads-bcsr");
192 if (!np) {
193 printk(KERN_CRIT "Could not find fsl,mpc885ads-bcsr node\n");
194 return;
195 }
196
197 bcsr = of_iomap(np, 0);
198 bcsr5 = of_iomap(np, 1);
199 of_node_put(np);
200
201 if (!bcsr || !bcsr5) {
202 printk(KERN_CRIT "Could not remap BCSR\n");
203 return;
204 }
205
206 clrbits32(&bcsr[1], BCSR1_RS232EN_1);
207#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
208 setbits32(&bcsr[1], BCSR1_RS232EN_2);
209#else
210 clrbits32(&bcsr[1], BCSR1_RS232EN_2);
211#endif
212
213 clrbits32(bcsr5, BCSR5_MII1_EN);
214 setbits32(bcsr5, BCSR5_MII1_RST);
215 udelay(1000);
216 clrbits32(bcsr5, BCSR5_MII1_RST);
217
218#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
219 clrbits32(bcsr5, BCSR5_MII2_EN);
220 setbits32(bcsr5, BCSR5_MII2_RST);
221 udelay(1000);
222 clrbits32(bcsr5, BCSR5_MII2_RST);
223#else
224 setbits32(bcsr5, BCSR5_MII2_EN);
225#endif
226
227#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
228 clrbits32(&bcsr[4], BCSR4_ETH10_RST);
229 udelay(1000);
230 setbits32(&bcsr[4], BCSR4_ETH10_RST);
231
232 setbits32(&bcsr[1], BCSR1_ETHEN);
233
234 np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
235#else
236 np = of_find_node_by_path("/soc@ff000000/cpm@9c0/ethernet@a40");
237#endif
238
239
240
241
242
243 if (np) {
244 of_detach_node(np);
245 of_node_put(np);
246 }
247
248#ifdef CONFIG_PCMCIA_M8XX
249
250 m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
251 m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
252#endif
253}
254
255static int __init mpc885ads_probe(void)
256{
257 unsigned long root = of_get_flat_dt_root();
258 return of_flat_dt_is_compatible(root, "fsl,mpc885ads");
259}
260
261static struct of_device_id __initdata of_bus_ids[] = {
262 { .name = "soc", },
263 { .name = "cpm", },
264 { .name = "localbus", },
265 {},
266};
267
268static int __init declare_of_platform_devices(void)
269{
270
271 of_platform_bus_probe(NULL, of_bus_ids, NULL);
272
273 return 0;
274}
275machine_device_initcall(mpc885_ads, declare_of_platform_devices);
276
277define_machine(mpc885_ads) {
278 .name = "Freescale MPC885 ADS",
279 .probe = mpc885ads_probe,
280 .setup_arch = mpc885ads_setup_arch,
281 .init_IRQ = mpc8xx_pics_init,
282 .get_irq = mpc8xx_get_irq,
283 .restart = mpc8xx_restart,
284 .calibrate_decr = mpc8xx_calibrate_decr,
285 .set_rtc_time = mpc8xx_set_rtc_time,
286 .get_rtc_time = mpc8xx_get_rtc_time,
287 .progress = udbg_progress,
288};
289
