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10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
13#include <linux/serial_sci.h>
14#include <linux/sh_timer.h>
15#include <linux/io.h>
16
17enum {
18 UNUSED = 0,
19
20
21 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
22 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
23 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
24 USB, LCDC, CMT0, CMT1, BSC, WDT,
25
26 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
27 MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V,
28
29 ADC_ADI,
30
31 IIC30, IIC31, IIC32, IIC33,
32 SCIF0, SCIF1, SCIF2, SCIF3,
33
34 SSU0, SSU1,
35
36 SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
37
38
39 ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1,
40 SRC, IEBI,
41
42
43 PINT,
44};
45
46static struct intc_vect vectors[] __initdata = {
47 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
48 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
49 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
50 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
51 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
52 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
53 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
54 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
55 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
56 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
57 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
58 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
59 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
60 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
61 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
62 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
63 INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
64 INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
65 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
66 INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147),
67 INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149),
68 INTC_IRQ(MTU0_VEF, 150),
69 INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152),
70 INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154),
71 INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156),
72 INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158),
73 INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160),
74 INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162),
75 INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164),
76 INTC_IRQ(MTU2_TCI3V, 165),
77 INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167),
78 INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169),
79 INTC_IRQ(MTU2_TCI4V, 170),
80 INTC_IRQ(ADC_ADI, 171),
81 INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173),
82 INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175),
83 INTC_IRQ(IIC30, 176),
84 INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178),
85 INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180),
86 INTC_IRQ(IIC31, 181),
87 INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183),
88 INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185),
89 INTC_IRQ(IIC32, 186),
90 INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188),
91 INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190),
92 INTC_IRQ(IIC33, 191),
93 INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193),
94 INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195),
95 INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197),
96 INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199),
97 INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201),
98 INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203),
99 INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205),
100 INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207),
101 INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209),
102 INTC_IRQ(SSU0, 210),
103 INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212),
104 INTC_IRQ(SSU1, 213),
105 INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
106 INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
107 INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225),
108 INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227),
109 INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
110 INTC_IRQ(RTC, 233),
111 INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235),
112 INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237),
113 INTC_IRQ(RCAN0, 238),
114 INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240),
115 INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242),
116 INTC_IRQ(RCAN1, 243),
117
118
119#ifdef CONFIG_CPU_SUBTYPE_SH7263
120 INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219),
121 INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221),
122 INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223),
123
124 INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229),
125 INTC_IRQ(SDHI, 230),
126
127 INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245),
128 INTC_IRQ(SRC, 246),
129
130 INTC_IRQ(IEBI, 247),
131#endif
132};
133
134static struct intc_group groups[] __initdata = {
135 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
136 PINT4, PINT5, PINT6, PINT7),
137};
138
139static struct intc_prio_reg prio_registers[] __initdata = {
140 { 0xfffe0818, 0, 16, 4, { IRQ0, IRQ1, IRQ2, IRQ3 } },
141 { 0xfffe081a, 0, 16, 4, { IRQ4, IRQ5, IRQ6, IRQ7 } },
142 { 0xfffe0820, 0, 16, 4, { PINT, 0, 0, 0 } },
143 { 0xfffe0c00, 0, 16, 4, { DMAC0, DMAC1, DMAC2, DMAC3 } },
144 { 0xfffe0c02, 0, 16, 4, { DMAC4, DMAC5, DMAC6, DMAC7 } },
145 { 0xfffe0c04, 0, 16, 4, { USB, LCDC, CMT0, CMT1 } },
146 { 0xfffe0c06, 0, 16, 4, { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
147 { 0xfffe0c08, 0, 16, 4, { MTU1_AB, MTU1_VU, MTU2_AB,
148 MTU2_VU } },
149 { 0xfffe0c0a, 0, 16, 4, { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
150 MTU2_TCI4V } },
151 { 0xfffe0c0c, 0, 16, 4, { ADC_ADI, IIC30, IIC31, IIC32 } },
152 { 0xfffe0c0e, 0, 16, 4, { IIC33, SCIF0, SCIF1, SCIF2 } },
153 { 0xfffe0c10, 0, 16, 4, { SCIF3, SSU0, SSU1, SSI0_SSII } },
154#ifdef CONFIG_CPU_SUBTYPE_SH7203
155 { 0xfffe0c12, 0, 16, 4, { SSI1_SSII, SSI2_SSII,
156 SSI3_SSII, 0 } },
157 { 0xfffe0c14, 0, 16, 4, { FLCTL, 0, RTC, RCAN0 } },
158 { 0xfffe0c16, 0, 16, 4, { RCAN1, 0, 0, 0 } },
159#else
160 { 0xfffe0c12, 0, 16, 4, { SSI1_SSII, SSI2_SSII,
161 SSI3_SSII, ROMDEC } },
162 { 0xfffe0c14, 0, 16, 4, { FLCTL, SDHI, RTC, RCAN0 } },
163 { 0xfffe0c16, 0, 16, 4, { RCAN1, SRC, IEBI, 0 } },
164#endif
165};
166
167static struct intc_mask_reg mask_registers[] __initdata = {
168 { 0xfffe0808, 0, 16,
169 { 0, 0, 0, 0, 0, 0, 0, 0,
170 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
171};
172
173static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
174 mask_registers, prio_registers, NULL);
175
176static struct plat_sci_port scif0_platform_data = {
177 .mapbase = 0xfffe8000,
178 .flags = UPF_BOOT_AUTOCONF,
179 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
180 .scbrr_algo_id = SCBRR_ALGO_2,
181 .type = PORT_SCIF,
182 .irqs = { 192, 192, 192, 192 },
183};
184
185static struct platform_device scif0_device = {
186 .name = "sh-sci",
187 .id = 0,
188 .dev = {
189 .platform_data = &scif0_platform_data,
190 },
191};
192
193static struct plat_sci_port scif1_platform_data = {
194 .mapbase = 0xfffe8800,
195 .flags = UPF_BOOT_AUTOCONF,
196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
197 .scbrr_algo_id = SCBRR_ALGO_2,
198 .type = PORT_SCIF,
199 .irqs = { 196, 196, 196, 196 },
200};
201
202static struct platform_device scif1_device = {
203 .name = "sh-sci",
204 .id = 1,
205 .dev = {
206 .platform_data = &scif1_platform_data,
207 },
208};
209
210static struct plat_sci_port scif2_platform_data = {
211 .mapbase = 0xfffe9000,
212 .flags = UPF_BOOT_AUTOCONF,
213 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
214 .scbrr_algo_id = SCBRR_ALGO_2,
215 .type = PORT_SCIF,
216 .irqs = { 200, 200, 200, 200 },
217};
218
219static struct platform_device scif2_device = {
220 .name = "sh-sci",
221 .id = 2,
222 .dev = {
223 .platform_data = &scif2_platform_data,
224 },
225};
226
227static struct plat_sci_port scif3_platform_data = {
228 .mapbase = 0xfffe9800,
229 .flags = UPF_BOOT_AUTOCONF,
230 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
231 .scbrr_algo_id = SCBRR_ALGO_2,
232 .type = PORT_SCIF,
233 .irqs = { 204, 204, 204, 204 },
234};
235
236static struct platform_device scif3_device = {
237 .name = "sh-sci",
238 .id = 3,
239 .dev = {
240 .platform_data = &scif3_platform_data,
241 },
242};
243
244static struct sh_timer_config cmt0_platform_data = {
245 .channel_offset = 0x02,
246 .timer_bit = 0,
247 .clockevent_rating = 125,
248 .clocksource_rating = 0,
249};
250
251static struct resource cmt0_resources[] = {
252 [0] = {
253 .start = 0xfffec002,
254 .end = 0xfffec007,
255 .flags = IORESOURCE_MEM,
256 },
257 [1] = {
258 .start = 142,
259 .flags = IORESOURCE_IRQ,
260 },
261};
262
263static struct platform_device cmt0_device = {
264 .name = "sh_cmt",
265 .id = 0,
266 .dev = {
267 .platform_data = &cmt0_platform_data,
268 },
269 .resource = cmt0_resources,
270 .num_resources = ARRAY_SIZE(cmt0_resources),
271};
272
273static struct sh_timer_config cmt1_platform_data = {
274 .channel_offset = 0x08,
275 .timer_bit = 1,
276 .clockevent_rating = 125,
277 .clocksource_rating = 0,
278};
279
280static struct resource cmt1_resources[] = {
281 [0] = {
282 .start = 0xfffec008,
283 .end = 0xfffec00d,
284 .flags = IORESOURCE_MEM,
285 },
286 [1] = {
287 .start = 143,
288 .flags = IORESOURCE_IRQ,
289 },
290};
291
292static struct platform_device cmt1_device = {
293 .name = "sh_cmt",
294 .id = 1,
295 .dev = {
296 .platform_data = &cmt1_platform_data,
297 },
298 .resource = cmt1_resources,
299 .num_resources = ARRAY_SIZE(cmt1_resources),
300};
301
302static struct sh_timer_config mtu2_0_platform_data = {
303 .channel_offset = -0x80,
304 .timer_bit = 0,
305 .clockevent_rating = 200,
306};
307
308static struct resource mtu2_0_resources[] = {
309 [0] = {
310 .start = 0xfffe4300,
311 .end = 0xfffe4326,
312 .flags = IORESOURCE_MEM,
313 },
314 [1] = {
315 .start = 146,
316 .flags = IORESOURCE_IRQ,
317 },
318};
319
320static struct platform_device mtu2_0_device = {
321 .name = "sh_mtu2",
322 .id = 0,
323 .dev = {
324 .platform_data = &mtu2_0_platform_data,
325 },
326 .resource = mtu2_0_resources,
327 .num_resources = ARRAY_SIZE(mtu2_0_resources),
328};
329
330static struct sh_timer_config mtu2_1_platform_data = {
331 .channel_offset = -0x100,
332 .timer_bit = 1,
333 .clockevent_rating = 200,
334};
335
336static struct resource mtu2_1_resources[] = {
337 [0] = {
338 .start = 0xfffe4380,
339 .end = 0xfffe4390,
340 .flags = IORESOURCE_MEM,
341 },
342 [1] = {
343 .start = 153,
344 .flags = IORESOURCE_IRQ,
345 },
346};
347
348static struct platform_device mtu2_1_device = {
349 .name = "sh_mtu2",
350 .id = 1,
351 .dev = {
352 .platform_data = &mtu2_1_platform_data,
353 },
354 .resource = mtu2_1_resources,
355 .num_resources = ARRAY_SIZE(mtu2_1_resources),
356};
357
358static struct resource rtc_resources[] = {
359 [0] = {
360 .start = 0xffff2000,
361 .end = 0xffff2000 + 0x58 - 1,
362 .flags = IORESOURCE_IO,
363 },
364 [1] = {
365
366 .start = 231,
367 .flags = IORESOURCE_IRQ,
368 },
369};
370
371static struct platform_device rtc_device = {
372 .name = "sh-rtc",
373 .id = -1,
374 .num_resources = ARRAY_SIZE(rtc_resources),
375 .resource = rtc_resources,
376};
377
378static struct platform_device *sh7203_devices[] __initdata = {
379 &scif0_device,
380 &scif1_device,
381 &scif2_device,
382 &scif3_device,
383 &cmt0_device,
384 &cmt1_device,
385 &mtu2_0_device,
386 &mtu2_1_device,
387 &rtc_device,
388};
389
390static int __init sh7203_devices_setup(void)
391{
392 return platform_add_devices(sh7203_devices,
393 ARRAY_SIZE(sh7203_devices));
394}
395arch_initcall(sh7203_devices_setup);
396
397void __init plat_irq_setup(void)
398{
399 register_intc_controller(&intc_desc);
400}
401
402static struct platform_device *sh7203_early_devices[] __initdata = {
403 &scif0_device,
404 &scif1_device,
405 &scif2_device,
406 &scif3_device,
407 &cmt0_device,
408 &cmt1_device,
409 &mtu2_0_device,
410 &mtu2_1_device,
411};
412
413#define STBCR3 0xfffe0408
414#define STBCR4 0xfffe040c
415
416void __init plat_early_device_setup(void)
417{
418
419 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
420
421
422 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
423
424 early_platform_add_devices(sh7203_early_devices,
425 ARRAY_SIZE(sh7203_early_devices));
426}
427
