1#ifndef _ASM_SPARC_DMA_H
2#define _ASM_SPARC_DMA_H
3
4
5
6
7#define MAX_DMA_CHANNELS 8
8#define DMA_MODE_READ 1
9#define DMA_MODE_WRITE 2
10#define MAX_DMA_ADDRESS (~0UL)
11
12
13#define SIZE_16MB (16*1024*1024)
14#define SIZE_64K (64*1024)
15
16
17#define DMA_CSR 0x00UL
18#define DMA_ADDR 0x04UL
19#define DMA_COUNT 0x08UL
20#define DMA_TEST 0x0cUL
21
22
23
24#define DMA_DEVICE_ID 0xf0000000
25#define DMA_VERS0 0x00000000
26#define DMA_ESCV1 0x40000000
27#define DMA_VERS1 0x80000000
28#define DMA_VERS2 0xa0000000
29#define DMA_VERHME 0xb0000000
30#define DMA_VERSPLUS 0x90000000
31
32#define DMA_HNDL_INTR 0x00000001
33#define DMA_HNDL_ERROR 0x00000002
34#define DMA_FIFO_ISDRAIN 0x0000000c
35#define DMA_INT_ENAB 0x00000010
36#define DMA_FIFO_INV 0x00000020
37#define DMA_ACC_SZ_ERR 0x00000040
38#define DMA_FIFO_STDRAIN 0x00000040
39#define DMA_RST_SCSI 0x00000080
40#define DMA_RST_ENET DMA_RST_SCSI
41#define DMA_ST_WRITE 0x00000100
42#define DMA_ENABLE 0x00000200
43#define DMA_PEND_READ 0x00000400
44#define DMA_ESC_BURST 0x00000800
45#define DMA_READ_AHEAD 0x00001800
46#define DMA_DSBL_RD_DRN 0x00001000
47#define DMA_BCNT_ENAB 0x00002000
48#define DMA_TERM_CNTR 0x00004000
49#define DMA_SCSI_SBUS64 0x00008000
50#define DMA_CSR_DISAB 0x00010000
51#define DMA_SCSI_DISAB 0x00020000
52#define DMA_DSBL_WR_INV 0x00020000
53#define DMA_ADD_ENABLE 0x00040000
54#define DMA_E_BURSTS 0x000c0000
55#define DMA_E_BURST32 0x00040000
56#define DMA_E_BURST16 0x00000000
57#define DMA_BRST_SZ 0x000c0000
58#define DMA_BRST64 0x000c0000
59#define DMA_BRST32 0x00040000
60#define DMA_BRST16 0x00000000
61#define DMA_BRST0 0x00080000
62#define DMA_ADDR_DISAB 0x00100000
63#define DMA_2CLKS 0x00200000
64#define DMA_3CLKS 0x00400000
65#define DMA_EN_ENETAUI DMA_3CLKS
66#define DMA_CNTR_DISAB 0x00800000
67#define DMA_AUTO_NADDR 0x01000000
68#define DMA_SCSI_ON 0x02000000
69#define DMA_PARITY_OFF 0x02000000
70#define DMA_LOADED_ADDR 0x04000000
71#define DMA_LOADED_NADDR 0x08000000
72#define DMA_RESET_FAS366 0x08000000
73
74
75#define DMA_BURST1 0x01
76#define DMA_BURST2 0x02
77#define DMA_BURST4 0x04
78#define DMA_BURST8 0x08
79#define DMA_BURST16 0x10
80#define DMA_BURST32 0x20
81#define DMA_BURST64 0x40
82#define DMA_BURSTBITS 0x7f
83
84
85
86#ifdef CONFIG_PCI
87extern int isa_dma_bridge_buggy;
88#else
89#define isa_dma_bridge_buggy (0)
90#endif
91
92#ifdef CONFIG_SPARC32
93
94
95BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long)
96BTFIXUPDEF_CALL(void, mmu_unlockarea, char *, unsigned long)
97
98#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len)
99#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len)
100
101struct page;
102struct device;
103struct scatterlist;
104
105
106BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, struct device *, char *, unsigned long)
107BTFIXUPDEF_CALL(void, mmu_get_scsi_sgl, struct device *, struct scatterlist *, int)
108BTFIXUPDEF_CALL(void, mmu_release_scsi_one, struct device *, __u32, unsigned long)
109BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct device *, struct scatterlist *, int)
110
111#define mmu_get_scsi_one(dev,vaddr,len) BTFIXUP_CALL(mmu_get_scsi_one)(dev,vaddr,len)
112#define mmu_get_scsi_sgl(dev,sg,sz) BTFIXUP_CALL(mmu_get_scsi_sgl)(dev,sg,sz)
113#define mmu_release_scsi_one(dev,vaddr,len) BTFIXUP_CALL(mmu_release_scsi_one)(dev,vaddr,len)
114#define mmu_release_scsi_sgl(dev,sg,sz) BTFIXUP_CALL(mmu_release_scsi_sgl)(dev,sg,sz)
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130
131
132BTFIXUPDEF_CALL(int, mmu_map_dma_area, struct device *, dma_addr_t *, unsigned long, unsigned long, int len)
133BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, struct device *, unsigned long busa, int len)
134
135#define mmu_map_dma_area(dev,pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(dev,pba,va,a,len)
136#define mmu_unmap_dma_area(dev,ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(dev,ba,len)
137#endif
138
139#endif
140