1#ifndef _ASM_X86_AMD_NB_H 2#define _ASM_X86_AMD_NB_H 3 4#include <linux/pci.h> 5 6struct amd_nb_bus_dev_range { 7 u8 bus; 8 u8 dev_base; 9 u8 dev_limit; 10}; 11 12extern const struct pci_device_id amd_nb_misc_ids[]; 13extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; 14 15extern bool early_is_amd_nb(u32 value); 16extern int amd_cache_northbridges(void); 17extern void amd_flush_garts(void); 18extern int amd_numa_init(void); 19extern int amd_get_subcaches(int); 20extern int amd_set_subcaches(int, int); 21 22struct amd_northbridge { 23 struct pci_dev *misc; 24 struct pci_dev *link; 25}; 26 27struct amd_northbridge_info { 28 u16 num; 29 u64 flags; 30 struct amd_northbridge *nb; 31}; 32extern struct amd_northbridge_info amd_northbridges; 33 34#define AMD_NB_GART BIT(0) 35#define AMD_NB_L3_INDEX_DISABLE BIT(1) 36#define AMD_NB_L3_PARTITIONING BIT(2) 37 38#ifdef CONFIG_AMD_NB 39 40static inline u16 amd_nb_num(void) 41{ 42 return amd_northbridges.num; 43} 44 45static inline bool amd_nb_has_feature(unsigned feature) 46{ 47 return ((amd_northbridges.flags & feature) == feature); 48} 49 50static inline struct amd_northbridge *node_to_amd_nb(int node) 51{ 52 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL; 53} 54 55#else 56 57#define amd_nb_num(x) 0 58#define amd_nb_has_feature(x) false 59#define node_to_amd_nb(x) NULL 60 61#endif 62 63 64#endif /* _ASM_X86_AMD_NB_H */ 65