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17#include <linux/ethtool.h>
18#include <linux/netdevice.h>
19#include <linux/types.h>
20#include <linux/sched.h>
21#include <linux/crc32.h>
22
23
24#include "bnx2x.h"
25#include "bnx2x_cmn.h"
26#include "bnx2x_dump.h"
27#include "bnx2x_init.h"
28
29
30
31
32
33#define MAX_QUEUE_NAME_LEN 4
34static const struct {
35 long offset;
36 int size;
37 char string[ETH_GSTRING_LEN];
38} bnx2x_q_stats_arr[] = {
39 { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
40 { Q_STATS_OFFSET32(error_bytes_received_hi),
41 8, "[%s]: rx_error_bytes" },
42 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
43 8, "[%s]: rx_ucast_packets" },
44 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
45 8, "[%s]: rx_mcast_packets" },
46 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
47 8, "[%s]: rx_bcast_packets" },
48 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
49 { Q_STATS_OFFSET32(rx_err_discard_pkt),
50 4, "[%s]: rx_phy_ip_err_discards"},
51 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
52 4, "[%s]: rx_skb_alloc_discard" },
53 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
54
55{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
56 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
57 8, "[%s]: tx_ucast_packets" },
58 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
59 8, "[%s]: tx_mcast_packets" },
60 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
61 8, "[%s]: tx_bcast_packets" }
62};
63
64#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
65
66static const struct {
67 long offset;
68 int size;
69 u32 flags;
70#define STATS_FLAGS_PORT 1
71#define STATS_FLAGS_FUNC 2
72#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
73 char string[ETH_GSTRING_LEN];
74} bnx2x_stats_arr[] = {
75 { STATS_OFFSET32(total_bytes_received_hi),
76 8, STATS_FLAGS_BOTH, "rx_bytes" },
77 { STATS_OFFSET32(error_bytes_received_hi),
78 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
79 { STATS_OFFSET32(total_unicast_packets_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
81 { STATS_OFFSET32(total_multicast_packets_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
83 { STATS_OFFSET32(total_broadcast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
85 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
86 8, STATS_FLAGS_PORT, "rx_crc_errors" },
87 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
88 8, STATS_FLAGS_PORT, "rx_align_errors" },
89 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
90 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
91 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
92 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
93{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
94 8, STATS_FLAGS_PORT, "rx_fragments" },
95 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
96 8, STATS_FLAGS_PORT, "rx_jabbers" },
97 { STATS_OFFSET32(no_buff_discard_hi),
98 8, STATS_FLAGS_BOTH, "rx_discards" },
99 { STATS_OFFSET32(mac_filter_discard),
100 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
101 { STATS_OFFSET32(xxoverflow_discard),
102 4, STATS_FLAGS_PORT, "rx_fw_discards" },
103 { STATS_OFFSET32(brb_drop_hi),
104 8, STATS_FLAGS_PORT, "rx_brb_discard" },
105 { STATS_OFFSET32(brb_truncate_hi),
106 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
107 { STATS_OFFSET32(pause_frames_received_hi),
108 8, STATS_FLAGS_PORT, "rx_pause_frames" },
109 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
110 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
111 { STATS_OFFSET32(nig_timer_max),
112 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
113{ STATS_OFFSET32(rx_err_discard_pkt),
114 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
115 { STATS_OFFSET32(rx_skb_alloc_failed),
116 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
117 { STATS_OFFSET32(hw_csum_err),
118 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
119
120 { STATS_OFFSET32(total_bytes_transmitted_hi),
121 8, STATS_FLAGS_BOTH, "tx_bytes" },
122 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
123 8, STATS_FLAGS_PORT, "tx_error_bytes" },
124 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
125 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
126 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
127 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
128 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
130 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
131 8, STATS_FLAGS_PORT, "tx_mac_errors" },
132 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
133 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
134{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
135 8, STATS_FLAGS_PORT, "tx_single_collisions" },
136 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
137 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
138 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
139 8, STATS_FLAGS_PORT, "tx_deferred" },
140 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
141 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
142 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
143 8, STATS_FLAGS_PORT, "tx_late_collisions" },
144 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
145 8, STATS_FLAGS_PORT, "tx_total_collisions" },
146 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
147 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
148 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
149 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
150 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
151 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
152 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
153 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
154{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
155 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
156 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
157 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
158 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
159 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
160 { STATS_OFFSET32(pause_frames_sent_hi),
161 8, STATS_FLAGS_PORT, "tx_pause_frames" }
162};
163
164#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
165
166static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
167{
168 struct bnx2x *bp = netdev_priv(dev);
169 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
170
171
172 cmd->supported = bp->port.supported[cfg_idx] |
173 (bp->port.supported[cfg_idx ^ 1] &
174 (SUPPORTED_TP | SUPPORTED_FIBRE));
175 cmd->advertising = bp->port.advertising[cfg_idx];
176
177 if ((bp->state == BNX2X_STATE_OPEN) &&
178 !(bp->flags & MF_FUNC_DIS) &&
179 (bp->link_vars.link_up)) {
180 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
181 cmd->duplex = bp->link_vars.duplex;
182 } else {
183 ethtool_cmd_speed_set(
184 cmd, bp->link_params.req_line_speed[cfg_idx]);
185 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
186 }
187
188 if (IS_MF(bp))
189 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
190
191 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
192 cmd->port = PORT_TP;
193 else if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
194 cmd->port = PORT_FIBRE;
195 else
196 BNX2X_ERR("XGXS PHY Failure detected\n");
197
198 cmd->phy_address = bp->mdio.prtad;
199 cmd->transceiver = XCVR_INTERNAL;
200
201 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
202 cmd->autoneg = AUTONEG_ENABLE;
203 else
204 cmd->autoneg = AUTONEG_DISABLE;
205
206 cmd->maxtxpkt = 0;
207 cmd->maxrxpkt = 0;
208
209 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
210 DP_LEVEL " supported 0x%x advertising 0x%x speed %u\n"
211 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
212 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
213 cmd->cmd, cmd->supported, cmd->advertising,
214 ethtool_cmd_speed(cmd),
215 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
216 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
217
218 return 0;
219}
220
221static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
222{
223 struct bnx2x *bp = netdev_priv(dev);
224 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
225 u32 speed;
226
227 if (IS_MF_SD(bp))
228 return 0;
229
230 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
231 " supported 0x%x advertising 0x%x speed %u\n"
232 " duplex %d port %d phy_address %d transceiver %d\n"
233 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
234 cmd->cmd, cmd->supported, cmd->advertising,
235 ethtool_cmd_speed(cmd),
236 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
237 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
238
239 speed = ethtool_cmd_speed(cmd);
240
241 if (IS_MF_SI(bp)) {
242 u32 part;
243 u32 line_speed = bp->link_vars.line_speed;
244
245
246 if (!line_speed)
247 line_speed = 10000;
248
249 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
250 BNX2X_DEV_INFO("To set speed BC %X or higher "
251 "is required, please upgrade BC\n",
252 REQ_BC_VER_4_SET_MF_BW);
253 return -EINVAL;
254 }
255
256 part = (speed * 100) / line_speed;
257
258 if (line_speed < speed || !part) {
259 BNX2X_DEV_INFO("Speed setting should be in a range "
260 "from 1%% to 100%% "
261 "of actual line speed\n");
262 return -EINVAL;
263 }
264
265 if (bp->state != BNX2X_STATE_OPEN)
266
267 bp->pending_max = part;
268 else
269 bnx2x_update_max_mf_config(bp, part);
270
271 return 0;
272 }
273
274 cfg_idx = bnx2x_get_link_cfg_idx(bp);
275 old_multi_phy_config = bp->link_params.multi_phy_config;
276 switch (cmd->port) {
277 case PORT_TP:
278 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
279 break;
280
281 if (!(bp->port.supported[0] & SUPPORTED_TP ||
282 bp->port.supported[1] & SUPPORTED_TP)) {
283 DP(NETIF_MSG_LINK, "Unsupported port type\n");
284 return -EINVAL;
285 }
286 bp->link_params.multi_phy_config &=
287 ~PORT_HW_CFG_PHY_SELECTION_MASK;
288 if (bp->link_params.multi_phy_config &
289 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
290 bp->link_params.multi_phy_config |=
291 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
292 else
293 bp->link_params.multi_phy_config |=
294 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
295 break;
296 case PORT_FIBRE:
297 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
298 break;
299
300 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
301 bp->port.supported[1] & SUPPORTED_FIBRE)) {
302 DP(NETIF_MSG_LINK, "Unsupported port type\n");
303 return -EINVAL;
304 }
305 bp->link_params.multi_phy_config &=
306 ~PORT_HW_CFG_PHY_SELECTION_MASK;
307 if (bp->link_params.multi_phy_config &
308 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
309 bp->link_params.multi_phy_config |=
310 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
311 else
312 bp->link_params.multi_phy_config |=
313 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
314 break;
315 default:
316 DP(NETIF_MSG_LINK, "Unsupported port type\n");
317 return -EINVAL;
318 }
319
320 new_multi_phy_config = bp->link_params.multi_phy_config;
321
322 cfg_idx = bnx2x_get_link_cfg_idx(bp);
323
324 bp->link_params.multi_phy_config = old_multi_phy_config;
325 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
326
327 if (cmd->autoneg == AUTONEG_ENABLE) {
328 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
329 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
330 return -EINVAL;
331 }
332
333
334 cmd->advertising &= bp->port.supported[cfg_idx];
335
336 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
337 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
338 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
339 cmd->advertising);
340
341 } else {
342
343 switch (speed) {
344 case SPEED_10:
345 if (cmd->duplex == DUPLEX_FULL) {
346 if (!(bp->port.supported[cfg_idx] &
347 SUPPORTED_10baseT_Full)) {
348 DP(NETIF_MSG_LINK,
349 "10M full not supported\n");
350 return -EINVAL;
351 }
352
353 advertising = (ADVERTISED_10baseT_Full |
354 ADVERTISED_TP);
355 } else {
356 if (!(bp->port.supported[cfg_idx] &
357 SUPPORTED_10baseT_Half)) {
358 DP(NETIF_MSG_LINK,
359 "10M half not supported\n");
360 return -EINVAL;
361 }
362
363 advertising = (ADVERTISED_10baseT_Half |
364 ADVERTISED_TP);
365 }
366 break;
367
368 case SPEED_100:
369 if (cmd->duplex == DUPLEX_FULL) {
370 if (!(bp->port.supported[cfg_idx] &
371 SUPPORTED_100baseT_Full)) {
372 DP(NETIF_MSG_LINK,
373 "100M full not supported\n");
374 return -EINVAL;
375 }
376
377 advertising = (ADVERTISED_100baseT_Full |
378 ADVERTISED_TP);
379 } else {
380 if (!(bp->port.supported[cfg_idx] &
381 SUPPORTED_100baseT_Half)) {
382 DP(NETIF_MSG_LINK,
383 "100M half not supported\n");
384 return -EINVAL;
385 }
386
387 advertising = (ADVERTISED_100baseT_Half |
388 ADVERTISED_TP);
389 }
390 break;
391
392 case SPEED_1000:
393 if (cmd->duplex != DUPLEX_FULL) {
394 DP(NETIF_MSG_LINK, "1G half not supported\n");
395 return -EINVAL;
396 }
397
398 if (!(bp->port.supported[cfg_idx] &
399 SUPPORTED_1000baseT_Full)) {
400 DP(NETIF_MSG_LINK, "1G full not supported\n");
401 return -EINVAL;
402 }
403
404 advertising = (ADVERTISED_1000baseT_Full |
405 ADVERTISED_TP);
406 break;
407
408 case SPEED_2500:
409 if (cmd->duplex != DUPLEX_FULL) {
410 DP(NETIF_MSG_LINK,
411 "2.5G half not supported\n");
412 return -EINVAL;
413 }
414
415 if (!(bp->port.supported[cfg_idx]
416 & SUPPORTED_2500baseX_Full)) {
417 DP(NETIF_MSG_LINK,
418 "2.5G full not supported\n");
419 return -EINVAL;
420 }
421
422 advertising = (ADVERTISED_2500baseX_Full |
423 ADVERTISED_TP);
424 break;
425
426 case SPEED_10000:
427 if (cmd->duplex != DUPLEX_FULL) {
428 DP(NETIF_MSG_LINK, "10G half not supported\n");
429 return -EINVAL;
430 }
431
432 if (!(bp->port.supported[cfg_idx]
433 & SUPPORTED_10000baseT_Full)) {
434 DP(NETIF_MSG_LINK, "10G full not supported\n");
435 return -EINVAL;
436 }
437
438 advertising = (ADVERTISED_10000baseT_Full |
439 ADVERTISED_FIBRE);
440 break;
441
442 default:
443 DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
444 return -EINVAL;
445 }
446
447 bp->link_params.req_line_speed[cfg_idx] = speed;
448 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
449 bp->port.advertising[cfg_idx] = advertising;
450 }
451
452 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
453 DP_LEVEL " req_duplex %d advertising 0x%x\n",
454 bp->link_params.req_line_speed[cfg_idx],
455 bp->link_params.req_duplex[cfg_idx],
456 bp->port.advertising[cfg_idx]);
457
458
459 bp->link_params.multi_phy_config = new_multi_phy_config;
460 if (netif_running(dev)) {
461 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
462 bnx2x_link_set(bp);
463 }
464
465 return 0;
466}
467
468#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
469#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
470#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
471
472static int bnx2x_get_regs_len(struct net_device *dev)
473{
474 struct bnx2x *bp = netdev_priv(dev);
475 int regdump_len = 0;
476 int i, j, k;
477
478 if (CHIP_IS_E1(bp)) {
479 for (i = 0; i < REGS_COUNT; i++)
480 if (IS_E1_ONLINE(reg_addrs[i].info))
481 regdump_len += reg_addrs[i].size;
482
483 for (i = 0; i < WREGS_COUNT_E1; i++)
484 if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
485 regdump_len += wreg_addrs_e1[i].size *
486 (1 + wreg_addrs_e1[i].read_regs_count);
487
488 } else if (CHIP_IS_E1H(bp)) {
489 for (i = 0; i < REGS_COUNT; i++)
490 if (IS_E1H_ONLINE(reg_addrs[i].info))
491 regdump_len += reg_addrs[i].size;
492
493 for (i = 0; i < WREGS_COUNT_E1H; i++)
494 if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
495 regdump_len += wreg_addrs_e1h[i].size *
496 (1 + wreg_addrs_e1h[i].read_regs_count);
497 } else if (CHIP_IS_E2(bp)) {
498 for (i = 0; i < REGS_COUNT; i++)
499 if (IS_E2_ONLINE(reg_addrs[i].info))
500 regdump_len += reg_addrs[i].size;
501
502 for (i = 0; i < WREGS_COUNT_E2; i++)
503 if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
504 regdump_len += wreg_addrs_e2[i].size *
505 (1 + wreg_addrs_e2[i].read_regs_count);
506
507 for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
508 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
509 for (k = 0; k < PAGE_READ_REGS_E2; k++)
510 if (IS_E2_ONLINE(page_read_regs_e2[k].
511 info))
512 regdump_len +=
513 page_read_regs_e2[k].size;
514 }
515 }
516 regdump_len *= 4;
517 regdump_len += sizeof(struct dump_hdr);
518
519 return regdump_len;
520}
521
522static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
523{
524 u32 i, j, k, n;
525
526 for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
527 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
528 REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
529 for (k = 0; k < PAGE_READ_REGS_E2; k++)
530 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
531 for (n = 0; n <
532 page_read_regs_e2[k].size; n++)
533 *p++ = REG_RD(bp,
534 page_read_regs_e2[k].addr + n*4);
535 }
536 }
537}
538
539static void bnx2x_get_regs(struct net_device *dev,
540 struct ethtool_regs *regs, void *_p)
541{
542 u32 *p = _p, i, j;
543 struct bnx2x *bp = netdev_priv(dev);
544 struct dump_hdr dump_hdr = {0};
545
546 regs->version = 0;
547 memset(p, 0, regs->len);
548
549 if (!netif_running(bp->dev))
550 return;
551
552
553
554
555
556 bnx2x_disable_blocks_parity(bp);
557
558 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
559 dump_hdr.dump_sign = dump_sign_all;
560 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
561 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
562 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
563 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
564
565 if (CHIP_IS_E1(bp))
566 dump_hdr.info = RI_E1_ONLINE;
567 else if (CHIP_IS_E1H(bp))
568 dump_hdr.info = RI_E1H_ONLINE;
569 else if (CHIP_IS_E2(bp))
570 dump_hdr.info = RI_E2_ONLINE |
571 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
572
573 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
574 p += dump_hdr.hdr_size + 1;
575
576 if (CHIP_IS_E1(bp)) {
577 for (i = 0; i < REGS_COUNT; i++)
578 if (IS_E1_ONLINE(reg_addrs[i].info))
579 for (j = 0; j < reg_addrs[i].size; j++)
580 *p++ = REG_RD(bp,
581 reg_addrs[i].addr + j*4);
582
583 } else if (CHIP_IS_E1H(bp)) {
584 for (i = 0; i < REGS_COUNT; i++)
585 if (IS_E1H_ONLINE(reg_addrs[i].info))
586 for (j = 0; j < reg_addrs[i].size; j++)
587 *p++ = REG_RD(bp,
588 reg_addrs[i].addr + j*4);
589
590 } else if (CHIP_IS_E2(bp)) {
591 for (i = 0; i < REGS_COUNT; i++)
592 if (IS_E2_ONLINE(reg_addrs[i].info))
593 for (j = 0; j < reg_addrs[i].size; j++)
594 *p++ = REG_RD(bp,
595 reg_addrs[i].addr + j*4);
596
597 bnx2x_read_pages_regs_e2(bp, p);
598 }
599
600 bnx2x_clear_blocks_parity(bp);
601 if (CHIP_PARITY_ENABLED(bp))
602 bnx2x_enable_blocks_parity(bp);
603}
604
605#define PHY_FW_VER_LEN 20
606
607static void bnx2x_get_drvinfo(struct net_device *dev,
608 struct ethtool_drvinfo *info)
609{
610 struct bnx2x *bp = netdev_priv(dev);
611 u8 phy_fw_ver[PHY_FW_VER_LEN];
612
613 strcpy(info->driver, DRV_MODULE_NAME);
614 strcpy(info->version, DRV_MODULE_VERSION);
615
616 phy_fw_ver[0] = '\0';
617 if (bp->port.pmf) {
618 bnx2x_acquire_phy_lock(bp);
619 bnx2x_get_ext_phy_fw_version(&bp->link_params,
620 (bp->state != BNX2X_STATE_CLOSED),
621 phy_fw_ver, PHY_FW_VER_LEN);
622 bnx2x_release_phy_lock(bp);
623 }
624
625 strncpy(info->fw_version, bp->fw_ver, 32);
626 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
627 "bc %d.%d.%d%s%s",
628 (bp->common.bc_ver & 0xff0000) >> 16,
629 (bp->common.bc_ver & 0xff00) >> 8,
630 (bp->common.bc_ver & 0xff),
631 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
632 strcpy(info->bus_info, pci_name(bp->pdev));
633 info->n_stats = BNX2X_NUM_STATS;
634 info->testinfo_len = BNX2X_NUM_TESTS;
635 info->eedump_len = bp->common.flash_size;
636 info->regdump_len = bnx2x_get_regs_len(dev);
637}
638
639static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
640{
641 struct bnx2x *bp = netdev_priv(dev);
642
643 if (bp->flags & NO_WOL_FLAG) {
644 wol->supported = 0;
645 wol->wolopts = 0;
646 } else {
647 wol->supported = WAKE_MAGIC;
648 if (bp->wol)
649 wol->wolopts = WAKE_MAGIC;
650 else
651 wol->wolopts = 0;
652 }
653 memset(&wol->sopass, 0, sizeof(wol->sopass));
654}
655
656static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
657{
658 struct bnx2x *bp = netdev_priv(dev);
659
660 if (wol->wolopts & ~WAKE_MAGIC)
661 return -EINVAL;
662
663 if (wol->wolopts & WAKE_MAGIC) {
664 if (bp->flags & NO_WOL_FLAG)
665 return -EINVAL;
666
667 bp->wol = 1;
668 } else
669 bp->wol = 0;
670
671 return 0;
672}
673
674static u32 bnx2x_get_msglevel(struct net_device *dev)
675{
676 struct bnx2x *bp = netdev_priv(dev);
677
678 return bp->msg_enable;
679}
680
681static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
682{
683 struct bnx2x *bp = netdev_priv(dev);
684
685 if (capable(CAP_NET_ADMIN))
686 bp->msg_enable = level;
687}
688
689static int bnx2x_nway_reset(struct net_device *dev)
690{
691 struct bnx2x *bp = netdev_priv(dev);
692
693 if (!bp->port.pmf)
694 return 0;
695
696 if (netif_running(dev)) {
697 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
698 bnx2x_link_set(bp);
699 }
700
701 return 0;
702}
703
704static u32 bnx2x_get_link(struct net_device *dev)
705{
706 struct bnx2x *bp = netdev_priv(dev);
707
708 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
709 return 0;
710
711 return bp->link_vars.link_up;
712}
713
714static int bnx2x_get_eeprom_len(struct net_device *dev)
715{
716 struct bnx2x *bp = netdev_priv(dev);
717
718 return bp->common.flash_size;
719}
720
721static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
722{
723 int port = BP_PORT(bp);
724 int count, i;
725 u32 val = 0;
726
727
728 count = NVRAM_TIMEOUT_COUNT;
729 if (CHIP_REV_IS_SLOW(bp))
730 count *= 100;
731
732
733 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
734 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
735
736 for (i = 0; i < count*10; i++) {
737 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
738 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
739 break;
740
741 udelay(5);
742 }
743
744 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
745 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
746 return -EBUSY;
747 }
748
749 return 0;
750}
751
752static int bnx2x_release_nvram_lock(struct bnx2x *bp)
753{
754 int port = BP_PORT(bp);
755 int count, i;
756 u32 val = 0;
757
758
759 count = NVRAM_TIMEOUT_COUNT;
760 if (CHIP_REV_IS_SLOW(bp))
761 count *= 100;
762
763
764 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
765 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
766
767 for (i = 0; i < count*10; i++) {
768 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
769 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
770 break;
771
772 udelay(5);
773 }
774
775 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
776 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
777 return -EBUSY;
778 }
779
780 return 0;
781}
782
783static void bnx2x_enable_nvram_access(struct bnx2x *bp)
784{
785 u32 val;
786
787 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
788
789
790 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
791 (val | MCPR_NVM_ACCESS_ENABLE_EN |
792 MCPR_NVM_ACCESS_ENABLE_WR_EN));
793}
794
795static void bnx2x_disable_nvram_access(struct bnx2x *bp)
796{
797 u32 val;
798
799 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
800
801
802 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
803 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
804 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
805}
806
807static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
808 u32 cmd_flags)
809{
810 int count, i, rc;
811 u32 val;
812
813
814 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
815
816
817 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
818
819
820 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
821 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
822
823
824 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
825
826
827 count = NVRAM_TIMEOUT_COUNT;
828 if (CHIP_REV_IS_SLOW(bp))
829 count *= 100;
830
831
832 *ret_val = 0;
833 rc = -EBUSY;
834 for (i = 0; i < count; i++) {
835 udelay(5);
836 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
837
838 if (val & MCPR_NVM_COMMAND_DONE) {
839 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
840
841
842
843 *ret_val = cpu_to_be32(val);
844 rc = 0;
845 break;
846 }
847 }
848
849 return rc;
850}
851
852static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
853 int buf_size)
854{
855 int rc;
856 u32 cmd_flags;
857 __be32 val;
858
859 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
860 DP(BNX2X_MSG_NVM,
861 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
862 offset, buf_size);
863 return -EINVAL;
864 }
865
866 if (offset + buf_size > bp->common.flash_size) {
867 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
868 " buf_size (0x%x) > flash_size (0x%x)\n",
869 offset, buf_size, bp->common.flash_size);
870 return -EINVAL;
871 }
872
873
874 rc = bnx2x_acquire_nvram_lock(bp);
875 if (rc)
876 return rc;
877
878
879 bnx2x_enable_nvram_access(bp);
880
881
882 cmd_flags = MCPR_NVM_COMMAND_FIRST;
883 while ((buf_size > sizeof(u32)) && (rc == 0)) {
884 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
885 memcpy(ret_buf, &val, 4);
886
887
888 offset += sizeof(u32);
889 ret_buf += sizeof(u32);
890 buf_size -= sizeof(u32);
891 cmd_flags = 0;
892 }
893
894 if (rc == 0) {
895 cmd_flags |= MCPR_NVM_COMMAND_LAST;
896 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
897 memcpy(ret_buf, &val, 4);
898 }
899
900
901 bnx2x_disable_nvram_access(bp);
902 bnx2x_release_nvram_lock(bp);
903
904 return rc;
905}
906
907static int bnx2x_get_eeprom(struct net_device *dev,
908 struct ethtool_eeprom *eeprom, u8 *eebuf)
909{
910 struct bnx2x *bp = netdev_priv(dev);
911 int rc;
912
913 if (!netif_running(dev))
914 return -EAGAIN;
915
916 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
917 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
918 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
919 eeprom->len, eeprom->len);
920
921
922
923 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
924
925 return rc;
926}
927
928static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
929 u32 cmd_flags)
930{
931 int count, i, rc;
932
933
934 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
935
936
937 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
938
939
940 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
941
942
943 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
944 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
945
946
947 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
948
949
950 count = NVRAM_TIMEOUT_COUNT;
951 if (CHIP_REV_IS_SLOW(bp))
952 count *= 100;
953
954
955 rc = -EBUSY;
956 for (i = 0; i < count; i++) {
957 udelay(5);
958 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
959 if (val & MCPR_NVM_COMMAND_DONE) {
960 rc = 0;
961 break;
962 }
963 }
964
965 return rc;
966}
967
968#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
969
970static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
971 int buf_size)
972{
973 int rc;
974 u32 cmd_flags;
975 u32 align_offset;
976 __be32 val;
977
978 if (offset + buf_size > bp->common.flash_size) {
979 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
980 " buf_size (0x%x) > flash_size (0x%x)\n",
981 offset, buf_size, bp->common.flash_size);
982 return -EINVAL;
983 }
984
985
986 rc = bnx2x_acquire_nvram_lock(bp);
987 if (rc)
988 return rc;
989
990
991 bnx2x_enable_nvram_access(bp);
992
993 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
994 align_offset = (offset & ~0x03);
995 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
996
997 if (rc == 0) {
998 val &= ~(0xff << BYTE_OFFSET(offset));
999 val |= (*data_buf << BYTE_OFFSET(offset));
1000
1001
1002
1003 val = be32_to_cpu(val);
1004
1005 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1006 cmd_flags);
1007 }
1008
1009
1010 bnx2x_disable_nvram_access(bp);
1011 bnx2x_release_nvram_lock(bp);
1012
1013 return rc;
1014}
1015
1016static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1017 int buf_size)
1018{
1019 int rc;
1020 u32 cmd_flags;
1021 u32 val;
1022 u32 written_so_far;
1023
1024 if (buf_size == 1)
1025 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1026
1027 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1028 DP(BNX2X_MSG_NVM,
1029 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1030 offset, buf_size);
1031 return -EINVAL;
1032 }
1033
1034 if (offset + buf_size > bp->common.flash_size) {
1035 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1036 " buf_size (0x%x) > flash_size (0x%x)\n",
1037 offset, buf_size, bp->common.flash_size);
1038 return -EINVAL;
1039 }
1040
1041
1042 rc = bnx2x_acquire_nvram_lock(bp);
1043 if (rc)
1044 return rc;
1045
1046
1047 bnx2x_enable_nvram_access(bp);
1048
1049 written_so_far = 0;
1050 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1051 while ((written_so_far < buf_size) && (rc == 0)) {
1052 if (written_so_far == (buf_size - sizeof(u32)))
1053 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1054 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
1055 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1056 else if ((offset % NVRAM_PAGE_SIZE) == 0)
1057 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1058
1059 memcpy(&val, data_buf, 4);
1060
1061 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1062
1063
1064 offset += sizeof(u32);
1065 data_buf += sizeof(u32);
1066 written_so_far += sizeof(u32);
1067 cmd_flags = 0;
1068 }
1069
1070
1071 bnx2x_disable_nvram_access(bp);
1072 bnx2x_release_nvram_lock(bp);
1073
1074 return rc;
1075}
1076
1077static int bnx2x_set_eeprom(struct net_device *dev,
1078 struct ethtool_eeprom *eeprom, u8 *eebuf)
1079{
1080 struct bnx2x *bp = netdev_priv(dev);
1081 int port = BP_PORT(bp);
1082 int rc = 0;
1083 u32 ext_phy_config;
1084 if (!netif_running(dev))
1085 return -EAGAIN;
1086
1087 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1088 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1089 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1090 eeprom->len, eeprom->len);
1091
1092
1093
1094
1095 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1096 !bp->port.pmf)
1097 return -EINVAL;
1098
1099 ext_phy_config =
1100 SHMEM_RD(bp,
1101 dev_info.port_hw_config[port].external_phy_config);
1102
1103 if (eeprom->magic == 0x50485950) {
1104
1105 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1106
1107 bnx2x_acquire_phy_lock(bp);
1108 rc |= bnx2x_link_reset(&bp->link_params,
1109 &bp->link_vars, 0);
1110 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1111 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1112 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1113 MISC_REGISTERS_GPIO_HIGH, port);
1114 bnx2x_release_phy_lock(bp);
1115 bnx2x_link_report(bp);
1116
1117 } else if (eeprom->magic == 0x50485952) {
1118
1119 if (bp->state == BNX2X_STATE_OPEN) {
1120 bnx2x_acquire_phy_lock(bp);
1121 rc |= bnx2x_link_reset(&bp->link_params,
1122 &bp->link_vars, 1);
1123
1124 rc |= bnx2x_phy_init(&bp->link_params,
1125 &bp->link_vars);
1126 bnx2x_release_phy_lock(bp);
1127 bnx2x_calc_fc_adv(bp);
1128 }
1129 } else if (eeprom->magic == 0x53985943) {
1130
1131 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1132 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1133
1134
1135 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1136 MISC_REGISTERS_GPIO_LOW, port);
1137
1138 bnx2x_acquire_phy_lock(bp);
1139
1140 bnx2x_sfx7101_sp_sw_reset(bp,
1141 &bp->link_params.phy[EXT_PHY1]);
1142
1143
1144 msleep(500);
1145 bnx2x_ext_phy_hw_reset(bp, port);
1146 msleep(500);
1147 bnx2x_release_phy_lock(bp);
1148 }
1149 } else
1150 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1151
1152 return rc;
1153}
1154
1155static int bnx2x_get_coalesce(struct net_device *dev,
1156 struct ethtool_coalesce *coal)
1157{
1158 struct bnx2x *bp = netdev_priv(dev);
1159
1160 memset(coal, 0, sizeof(struct ethtool_coalesce));
1161
1162 coal->rx_coalesce_usecs = bp->rx_ticks;
1163 coal->tx_coalesce_usecs = bp->tx_ticks;
1164
1165 return 0;
1166}
1167
1168static int bnx2x_set_coalesce(struct net_device *dev,
1169 struct ethtool_coalesce *coal)
1170{
1171 struct bnx2x *bp = netdev_priv(dev);
1172
1173 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1174 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1175 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1176
1177 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1178 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1179 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1180
1181 if (netif_running(dev))
1182 bnx2x_update_coalesce(bp);
1183
1184 return 0;
1185}
1186
1187static void bnx2x_get_ringparam(struct net_device *dev,
1188 struct ethtool_ringparam *ering)
1189{
1190 struct bnx2x *bp = netdev_priv(dev);
1191
1192 ering->rx_max_pending = MAX_RX_AVAIL;
1193 ering->rx_mini_max_pending = 0;
1194 ering->rx_jumbo_max_pending = 0;
1195
1196 if (bp->rx_ring_size)
1197 ering->rx_pending = bp->rx_ring_size;
1198 else
1199 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1200 ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1201 else
1202 ering->rx_pending = MAX_RX_AVAIL;
1203
1204 ering->rx_mini_pending = 0;
1205 ering->rx_jumbo_pending = 0;
1206
1207 ering->tx_max_pending = MAX_TX_AVAIL;
1208 ering->tx_pending = bp->tx_ring_size;
1209}
1210
1211static int bnx2x_set_ringparam(struct net_device *dev,
1212 struct ethtool_ringparam *ering)
1213{
1214 struct bnx2x *bp = netdev_priv(dev);
1215 int rc = 0;
1216
1217 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1218 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1219 return -EAGAIN;
1220 }
1221
1222 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1223 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1224 MIN_RX_SIZE_TPA)) ||
1225 (ering->tx_pending > MAX_TX_AVAIL) ||
1226 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1227 return -EINVAL;
1228
1229 bp->rx_ring_size = ering->rx_pending;
1230 bp->tx_ring_size = ering->tx_pending;
1231
1232 if (netif_running(dev)) {
1233 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1234 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1235 }
1236
1237 return rc;
1238}
1239
1240static void bnx2x_get_pauseparam(struct net_device *dev,
1241 struct ethtool_pauseparam *epause)
1242{
1243 struct bnx2x *bp = netdev_priv(dev);
1244 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1245 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1246 BNX2X_FLOW_CTRL_AUTO);
1247
1248 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1249 BNX2X_FLOW_CTRL_RX);
1250 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1251 BNX2X_FLOW_CTRL_TX);
1252
1253 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1254 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1255 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1256}
1257
1258static int bnx2x_set_pauseparam(struct net_device *dev,
1259 struct ethtool_pauseparam *epause)
1260{
1261 struct bnx2x *bp = netdev_priv(dev);
1262 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1263 if (IS_MF(bp))
1264 return 0;
1265
1266 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1267 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1268 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1269
1270 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1271
1272 if (epause->rx_pause)
1273 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1274
1275 if (epause->tx_pause)
1276 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1277
1278 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1279 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1280
1281 if (epause->autoneg) {
1282 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1283 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1284 return -EINVAL;
1285 }
1286
1287 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1288 bp->link_params.req_flow_ctrl[cfg_idx] =
1289 BNX2X_FLOW_CTRL_AUTO;
1290 }
1291 }
1292
1293 DP(NETIF_MSG_LINK,
1294 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1295
1296 if (netif_running(dev)) {
1297 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1298 bnx2x_link_set(bp);
1299 }
1300
1301 return 0;
1302}
1303
1304static const struct {
1305 char string[ETH_GSTRING_LEN];
1306} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1307 { "register_test (offline)" },
1308 { "memory_test (offline)" },
1309 { "loopback_test (offline)" },
1310 { "nvram_test (online)" },
1311 { "interrupt_test (online)" },
1312 { "link_test (online)" },
1313 { "idle check (online)" }
1314};
1315
1316static int bnx2x_test_registers(struct bnx2x *bp)
1317{
1318 int idx, i, rc = -ENODEV;
1319 u32 wr_val = 0;
1320 int port = BP_PORT(bp);
1321 static const struct {
1322 u32 offset0;
1323 u32 offset1;
1324 u32 mask;
1325 } reg_tbl[] = {
1326 { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1327 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1328 { HC_REG_AGG_INT_0, 4, 0x000003ff },
1329 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1330 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1331 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1332 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1333 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1334 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1335 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1336 { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1337 { QM_REG_CONNNUM_0, 4, 0x000fffff },
1338 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1339 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1340 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1341 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1342 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1343 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1344 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1345 { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1346 { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1347 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1348 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1349 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1350 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1351 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1352 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1353 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1354 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1355 { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1356 { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1357 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1358 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1359 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1360 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1361 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1362 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1363
1364 { 0xffffffff, 0, 0x00000000 }
1365 };
1366
1367 if (!netif_running(bp->dev))
1368 return rc;
1369
1370
1371
1372 for (idx = 0; idx < 2; idx++) {
1373
1374 switch (idx) {
1375 case 0:
1376 wr_val = 0;
1377 break;
1378 case 1:
1379 wr_val = 0xffffffff;
1380 break;
1381 }
1382
1383 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1384 u32 offset, mask, save_val, val;
1385 if (CHIP_IS_E2(bp) &&
1386 reg_tbl[i].offset0 == HC_REG_AGG_INT_0)
1387 continue;
1388
1389 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1390 mask = reg_tbl[i].mask;
1391
1392 save_val = REG_RD(bp, offset);
1393
1394 REG_WR(bp, offset, wr_val & mask);
1395
1396 val = REG_RD(bp, offset);
1397
1398
1399 REG_WR(bp, offset, save_val);
1400
1401
1402 if ((val & mask) != (wr_val & mask)) {
1403 DP(NETIF_MSG_PROBE,
1404 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1405 offset, val, wr_val, mask);
1406 goto test_reg_exit;
1407 }
1408 }
1409 }
1410
1411 rc = 0;
1412
1413test_reg_exit:
1414 return rc;
1415}
1416
1417static int bnx2x_test_memory(struct bnx2x *bp)
1418{
1419 int i, j, rc = -ENODEV;
1420 u32 val;
1421 static const struct {
1422 u32 offset;
1423 int size;
1424 } mem_tbl[] = {
1425 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1426 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1427 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1428 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1429 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1430 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1431 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1432
1433 { 0xffffffff, 0 }
1434 };
1435 static const struct {
1436 char *name;
1437 u32 offset;
1438 u32 e1_mask;
1439 u32 e1h_mask;
1440 u32 e2_mask;
1441 } prty_tbl[] = {
1442 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0, 0 },
1443 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2, 0 },
1444 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0, 0 },
1445 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0, 0 },
1446 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0, 0 },
1447 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0, 0 },
1448
1449 { NULL, 0xffffffff, 0, 0, 0 }
1450 };
1451
1452 if (!netif_running(bp->dev))
1453 return rc;
1454
1455
1456 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1457 val = REG_RD(bp, prty_tbl[i].offset);
1458 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1459 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1460 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1461 DP(NETIF_MSG_HW,
1462 "%s is 0x%x\n", prty_tbl[i].name, val);
1463 goto test_mem_exit;
1464 }
1465 }
1466
1467
1468 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1469 for (j = 0; j < mem_tbl[i].size; j++)
1470 REG_RD(bp, mem_tbl[i].offset + j*4);
1471
1472
1473 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1474 val = REG_RD(bp, prty_tbl[i].offset);
1475 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1476 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1477 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1478 DP(NETIF_MSG_HW,
1479 "%s is 0x%x\n", prty_tbl[i].name, val);
1480 goto test_mem_exit;
1481 }
1482 }
1483
1484 rc = 0;
1485
1486test_mem_exit:
1487 return rc;
1488}
1489
1490static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1491{
1492 int cnt = 1400;
1493
1494 if (link_up)
1495 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1496 msleep(10);
1497}
1498
1499static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1500{
1501 unsigned int pkt_size, num_pkts, i;
1502 struct sk_buff *skb;
1503 unsigned char *packet;
1504 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1505 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1506 u16 tx_start_idx, tx_idx;
1507 u16 rx_start_idx, rx_idx;
1508 u16 pkt_prod, bd_prod;
1509 struct sw_tx_bd *tx_buf;
1510 struct eth_tx_start_bd *tx_start_bd;
1511 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1512 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
1513 dma_addr_t mapping;
1514 union eth_rx_cqe *cqe;
1515 u8 cqe_fp_flags;
1516 struct sw_rx_bd *rx_buf;
1517 u16 len;
1518 int rc = -ENODEV;
1519
1520
1521 switch (loopback_mode) {
1522 case BNX2X_PHY_LOOPBACK:
1523 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1524 return -EINVAL;
1525 break;
1526 case BNX2X_MAC_LOOPBACK:
1527 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1528 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1529 break;
1530 default:
1531 return -EINVAL;
1532 }
1533
1534
1535 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1536 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1537 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
1538 if (!skb) {
1539 rc = -ENOMEM;
1540 goto test_loopback_exit;
1541 }
1542 packet = skb_put(skb, pkt_size);
1543 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1544 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1545 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1546 for (i = ETH_HLEN; i < pkt_size; i++)
1547 packet[i] = (unsigned char) (i & 0xff);
1548
1549
1550 num_pkts = 0;
1551 tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1552 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1553
1554 pkt_prod = fp_tx->tx_pkt_prod++;
1555 tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1556 tx_buf->first_bd = fp_tx->tx_bd_prod;
1557 tx_buf->skb = skb;
1558 tx_buf->flags = 0;
1559
1560 bd_prod = TX_BD(fp_tx->tx_bd_prod);
1561 tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1562 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1563 skb_headlen(skb), DMA_TO_DEVICE);
1564 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1565 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1566 tx_start_bd->nbd = cpu_to_le16(2);
1567 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1568 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1569 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1570 SET_FLAG(tx_start_bd->general_data,
1571 ETH_TX_START_BD_ETH_ADDR_TYPE,
1572 UNICAST_ADDRESS);
1573 SET_FLAG(tx_start_bd->general_data,
1574 ETH_TX_START_BD_HDR_NBDS,
1575 1);
1576
1577
1578 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1579
1580 pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
1581 pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
1582
1583 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1584 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1585
1586 wmb();
1587
1588 fp_tx->tx_db.data.prod += 2;
1589 barrier();
1590 DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1591
1592 mmiowb();
1593
1594 num_pkts++;
1595 fp_tx->tx_bd_prod += 2;
1596
1597 udelay(100);
1598
1599 tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1600 if (tx_idx != tx_start_idx + num_pkts)
1601 goto test_loopback_exit;
1602
1603
1604
1605
1606
1607 if (bp->common.int_block == INT_BLOCK_IGU) {
1608
1609
1610
1611
1612 local_bh_disable();
1613 bnx2x_tx_int(fp_tx);
1614 local_bh_enable();
1615 }
1616
1617 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1618 if (rx_idx != rx_start_idx + num_pkts)
1619 goto test_loopback_exit;
1620
1621 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1622 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1623 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1624 goto test_loopback_rx_exit;
1625
1626 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1627 if (len != pkt_size)
1628 goto test_loopback_rx_exit;
1629
1630 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1631 skb = rx_buf->skb;
1632 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1633 for (i = ETH_HLEN; i < pkt_size; i++)
1634 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1635 goto test_loopback_rx_exit;
1636
1637 rc = 0;
1638
1639test_loopback_rx_exit:
1640
1641 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1642 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1643 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1644 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1645
1646
1647 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1648 fp_rx->rx_sge_prod);
1649
1650test_loopback_exit:
1651 bp->link_params.loopback_mode = LOOPBACK_NONE;
1652
1653 return rc;
1654}
1655
1656static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1657{
1658 int rc = 0, res;
1659
1660 if (BP_NOMCP(bp))
1661 return rc;
1662
1663 if (!netif_running(bp->dev))
1664 return BNX2X_LOOPBACK_FAILED;
1665
1666 bnx2x_netif_stop(bp, 1);
1667 bnx2x_acquire_phy_lock(bp);
1668
1669 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1670 if (res) {
1671 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1672 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1673 }
1674
1675 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1676 if (res) {
1677 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1678 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1679 }
1680
1681 bnx2x_release_phy_lock(bp);
1682 bnx2x_netif_start(bp);
1683
1684 return rc;
1685}
1686
1687#define CRC32_RESIDUAL 0xdebb20e3
1688
1689static int bnx2x_test_nvram(struct bnx2x *bp)
1690{
1691 static const struct {
1692 int offset;
1693 int size;
1694 } nvram_tbl[] = {
1695 { 0, 0x14 },
1696 { 0x14, 0xec },
1697 { 0x100, 0x350 },
1698 { 0x450, 0xf0 },
1699 { 0x640, 0x64 },
1700 { 0x708, 0x70 },
1701 { 0, 0 }
1702 };
1703 __be32 buf[0x350 / 4];
1704 u8 *data = (u8 *)buf;
1705 int i, rc;
1706 u32 magic, crc;
1707
1708 if (BP_NOMCP(bp))
1709 return 0;
1710
1711 rc = bnx2x_nvram_read(bp, 0, data, 4);
1712 if (rc) {
1713 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1714 goto test_nvram_exit;
1715 }
1716
1717 magic = be32_to_cpu(buf[0]);
1718 if (magic != 0x669955aa) {
1719 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1720 rc = -ENODEV;
1721 goto test_nvram_exit;
1722 }
1723
1724 for (i = 0; nvram_tbl[i].size; i++) {
1725
1726 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1727 nvram_tbl[i].size);
1728 if (rc) {
1729 DP(NETIF_MSG_PROBE,
1730 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1731 goto test_nvram_exit;
1732 }
1733
1734 crc = ether_crc_le(nvram_tbl[i].size, data);
1735 if (crc != CRC32_RESIDUAL) {
1736 DP(NETIF_MSG_PROBE,
1737 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1738 rc = -ENODEV;
1739 goto test_nvram_exit;
1740 }
1741 }
1742
1743test_nvram_exit:
1744 return rc;
1745}
1746
1747static int bnx2x_test_intr(struct bnx2x *bp)
1748{
1749 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1750 int i, rc;
1751
1752 if (!netif_running(bp->dev))
1753 return -ENODEV;
1754
1755 config->hdr.length = 0;
1756 if (CHIP_IS_E1(bp))
1757 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
1758 else
1759 config->hdr.offset = BP_FUNC(bp);
1760 config->hdr.client_id = bp->fp->cl_id;
1761 config->hdr.reserved1 = 0;
1762
1763 bp->set_mac_pending = 1;
1764 smp_wmb();
1765 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
1766 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
1767 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
1768 if (rc == 0) {
1769 for (i = 0; i < 10; i++) {
1770 if (!bp->set_mac_pending)
1771 break;
1772 smp_rmb();
1773 msleep_interruptible(10);
1774 }
1775 if (i == 10)
1776 rc = -ENODEV;
1777 }
1778
1779 return rc;
1780}
1781
1782static void bnx2x_self_test(struct net_device *dev,
1783 struct ethtool_test *etest, u64 *buf)
1784{
1785 struct bnx2x *bp = netdev_priv(dev);
1786 u8 is_serdes;
1787 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1788 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1789 etest->flags |= ETH_TEST_FL_FAILED;
1790 return;
1791 }
1792
1793 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1794
1795 if (!netif_running(dev))
1796 return;
1797
1798
1799 if (IS_MF(bp))
1800 etest->flags &= ~ETH_TEST_FL_OFFLINE;
1801 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
1802
1803 if (etest->flags & ETH_TEST_FL_OFFLINE) {
1804 int port = BP_PORT(bp);
1805 u32 val;
1806 u8 link_up;
1807
1808
1809 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1810
1811 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1812
1813 link_up = bp->link_vars.link_up;
1814
1815 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1816 bnx2x_nic_load(bp, LOAD_DIAG);
1817
1818 bnx2x_wait_for_link(bp, link_up, is_serdes);
1819
1820 if (bnx2x_test_registers(bp) != 0) {
1821 buf[0] = 1;
1822 etest->flags |= ETH_TEST_FL_FAILED;
1823 }
1824 if (bnx2x_test_memory(bp) != 0) {
1825 buf[1] = 1;
1826 etest->flags |= ETH_TEST_FL_FAILED;
1827 }
1828
1829 buf[2] = bnx2x_test_loopback(bp, link_up);
1830 if (buf[2] != 0)
1831 etest->flags |= ETH_TEST_FL_FAILED;
1832
1833 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1834
1835
1836 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1837
1838 bnx2x_nic_load(bp, LOAD_NORMAL);
1839
1840 bnx2x_wait_for_link(bp, link_up, is_serdes);
1841 }
1842 if (bnx2x_test_nvram(bp) != 0) {
1843 buf[3] = 1;
1844 etest->flags |= ETH_TEST_FL_FAILED;
1845 }
1846 if (bnx2x_test_intr(bp) != 0) {
1847 buf[4] = 1;
1848 etest->flags |= ETH_TEST_FL_FAILED;
1849 }
1850
1851 if (bnx2x_link_test(bp, is_serdes) != 0) {
1852 buf[5] = 1;
1853 etest->flags |= ETH_TEST_FL_FAILED;
1854 }
1855
1856#ifdef BNX2X_EXTRA_DEBUG
1857 bnx2x_panic_dump(bp);
1858#endif
1859}
1860
1861#define IS_PORT_STAT(i) \
1862 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1863#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
1864#define IS_MF_MODE_STAT(bp) \
1865 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
1866
1867static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1868{
1869 struct bnx2x *bp = netdev_priv(dev);
1870 int i, num_stats;
1871
1872 switch (stringset) {
1873 case ETH_SS_STATS:
1874 if (is_multi(bp)) {
1875 num_stats = BNX2X_NUM_STAT_QUEUES(bp) *
1876 BNX2X_NUM_Q_STATS;
1877 if (!IS_MF_MODE_STAT(bp))
1878 num_stats += BNX2X_NUM_STATS;
1879 } else {
1880 if (IS_MF_MODE_STAT(bp)) {
1881 num_stats = 0;
1882 for (i = 0; i < BNX2X_NUM_STATS; i++)
1883 if (IS_FUNC_STAT(i))
1884 num_stats++;
1885 } else
1886 num_stats = BNX2X_NUM_STATS;
1887 }
1888 return num_stats;
1889
1890 case ETH_SS_TEST:
1891 return BNX2X_NUM_TESTS;
1892
1893 default:
1894 return -EINVAL;
1895 }
1896}
1897
1898static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1899{
1900 struct bnx2x *bp = netdev_priv(dev);
1901 int i, j, k;
1902 char queue_name[MAX_QUEUE_NAME_LEN+1];
1903
1904 switch (stringset) {
1905 case ETH_SS_STATS:
1906 if (is_multi(bp)) {
1907 k = 0;
1908 for_each_napi_queue(bp, i) {
1909 memset(queue_name, 0, sizeof(queue_name));
1910
1911 if (IS_FCOE_IDX(i))
1912 sprintf(queue_name, "fcoe");
1913 else
1914 sprintf(queue_name, "%d", i);
1915
1916 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
1917 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
1918 ETH_GSTRING_LEN,
1919 bnx2x_q_stats_arr[j].string,
1920 queue_name);
1921 k += BNX2X_NUM_Q_STATS;
1922 }
1923 if (IS_MF_MODE_STAT(bp))
1924 break;
1925 for (j = 0; j < BNX2X_NUM_STATS; j++)
1926 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
1927 bnx2x_stats_arr[j].string);
1928 } else {
1929 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
1930 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
1931 continue;
1932 strcpy(buf + j*ETH_GSTRING_LEN,
1933 bnx2x_stats_arr[i].string);
1934 j++;
1935 }
1936 }
1937 break;
1938
1939 case ETH_SS_TEST:
1940 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
1941 break;
1942 }
1943}
1944
1945static void bnx2x_get_ethtool_stats(struct net_device *dev,
1946 struct ethtool_stats *stats, u64 *buf)
1947{
1948 struct bnx2x *bp = netdev_priv(dev);
1949 u32 *hw_stats, *offset;
1950 int i, j, k;
1951
1952 if (is_multi(bp)) {
1953 k = 0;
1954 for_each_napi_queue(bp, i) {
1955 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
1956 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
1957 if (bnx2x_q_stats_arr[j].size == 0) {
1958
1959 buf[k + j] = 0;
1960 continue;
1961 }
1962 offset = (hw_stats +
1963 bnx2x_q_stats_arr[j].offset);
1964 if (bnx2x_q_stats_arr[j].size == 4) {
1965
1966 buf[k + j] = (u64) *offset;
1967 continue;
1968 }
1969
1970 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1971 }
1972 k += BNX2X_NUM_Q_STATS;
1973 }
1974 if (IS_MF_MODE_STAT(bp))
1975 return;
1976 hw_stats = (u32 *)&bp->eth_stats;
1977 for (j = 0; j < BNX2X_NUM_STATS; j++) {
1978 if (bnx2x_stats_arr[j].size == 0) {
1979
1980 buf[k + j] = 0;
1981 continue;
1982 }
1983 offset = (hw_stats + bnx2x_stats_arr[j].offset);
1984 if (bnx2x_stats_arr[j].size == 4) {
1985
1986 buf[k + j] = (u64) *offset;
1987 continue;
1988 }
1989
1990 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1991 }
1992 } else {
1993 hw_stats = (u32 *)&bp->eth_stats;
1994 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
1995 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
1996 continue;
1997 if (bnx2x_stats_arr[i].size == 0) {
1998
1999 buf[j] = 0;
2000 j++;
2001 continue;
2002 }
2003 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2004 if (bnx2x_stats_arr[i].size == 4) {
2005
2006 buf[j] = (u64) *offset;
2007 j++;
2008 continue;
2009 }
2010
2011 buf[j] = HILO_U64(*offset, *(offset + 1));
2012 j++;
2013 }
2014 }
2015}
2016
2017static int bnx2x_set_phys_id(struct net_device *dev,
2018 enum ethtool_phys_id_state state)
2019{
2020 struct bnx2x *bp = netdev_priv(dev);
2021
2022 if (!netif_running(dev))
2023 return -EAGAIN;
2024
2025 if (!bp->port.pmf)
2026 return -EOPNOTSUPP;
2027
2028 switch (state) {
2029 case ETHTOOL_ID_ACTIVE:
2030 return 1;
2031
2032 case ETHTOOL_ID_ON:
2033 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2034 LED_MODE_ON, SPEED_1000);
2035 break;
2036
2037 case ETHTOOL_ID_OFF:
2038 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2039 LED_MODE_FRONT_PANEL_OFF, 0);
2040
2041 break;
2042
2043 case ETHTOOL_ID_INACTIVE:
2044 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2045 LED_MODE_OPER,
2046 bp->link_vars.line_speed);
2047 }
2048
2049 return 0;
2050}
2051
2052static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2053 void *rules __always_unused)
2054{
2055 struct bnx2x *bp = netdev_priv(dev);
2056
2057 switch (info->cmd) {
2058 case ETHTOOL_GRXRINGS:
2059 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2060 return 0;
2061
2062 default:
2063 return -EOPNOTSUPP;
2064 }
2065}
2066
2067static int bnx2x_get_rxfh_indir(struct net_device *dev,
2068 struct ethtool_rxfh_indir *indir)
2069{
2070 struct bnx2x *bp = netdev_priv(dev);
2071 size_t copy_size =
2072 min_t(size_t, indir->size, TSTORM_INDIRECTION_TABLE_SIZE);
2073
2074 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2075 return -EOPNOTSUPP;
2076
2077 indir->size = TSTORM_INDIRECTION_TABLE_SIZE;
2078 memcpy(indir->ring_index, bp->rx_indir_table,
2079 copy_size * sizeof(bp->rx_indir_table[0]));
2080 return 0;
2081}
2082
2083static int bnx2x_set_rxfh_indir(struct net_device *dev,
2084 const struct ethtool_rxfh_indir *indir)
2085{
2086 struct bnx2x *bp = netdev_priv(dev);
2087 size_t i;
2088
2089 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2090 return -EOPNOTSUPP;
2091
2092
2093 if (indir->size != TSTORM_INDIRECTION_TABLE_SIZE)
2094 return -EINVAL;
2095 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
2096 if (indir->ring_index[i] >= BNX2X_NUM_ETH_QUEUES(bp))
2097 return -EINVAL;
2098
2099 memcpy(bp->rx_indir_table, indir->ring_index,
2100 indir->size * sizeof(bp->rx_indir_table[0]));
2101 bnx2x_push_indir_table(bp);
2102 return 0;
2103}
2104
2105static const struct ethtool_ops bnx2x_ethtool_ops = {
2106 .get_settings = bnx2x_get_settings,
2107 .set_settings = bnx2x_set_settings,
2108 .get_drvinfo = bnx2x_get_drvinfo,
2109 .get_regs_len = bnx2x_get_regs_len,
2110 .get_regs = bnx2x_get_regs,
2111 .get_wol = bnx2x_get_wol,
2112 .set_wol = bnx2x_set_wol,
2113 .get_msglevel = bnx2x_get_msglevel,
2114 .set_msglevel = bnx2x_set_msglevel,
2115 .nway_reset = bnx2x_nway_reset,
2116 .get_link = bnx2x_get_link,
2117 .get_eeprom_len = bnx2x_get_eeprom_len,
2118 .get_eeprom = bnx2x_get_eeprom,
2119 .set_eeprom = bnx2x_set_eeprom,
2120 .get_coalesce = bnx2x_get_coalesce,
2121 .set_coalesce = bnx2x_set_coalesce,
2122 .get_ringparam = bnx2x_get_ringparam,
2123 .set_ringparam = bnx2x_set_ringparam,
2124 .get_pauseparam = bnx2x_get_pauseparam,
2125 .set_pauseparam = bnx2x_set_pauseparam,
2126 .self_test = bnx2x_self_test,
2127 .get_sset_count = bnx2x_get_sset_count,
2128 .get_strings = bnx2x_get_strings,
2129 .set_phys_id = bnx2x_set_phys_id,
2130 .get_ethtool_stats = bnx2x_get_ethtool_stats,
2131 .get_rxnfc = bnx2x_get_rxnfc,
2132 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2133 .set_rxfh_indir = bnx2x_set_rxfh_indir,
2134};
2135
2136void bnx2x_set_ethtool_ops(struct net_device *netdev)
2137{
2138 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2139}
2140
