LXR linux/drivers/net/ixgbe/ixgbe_dcb

   1/*******************************************************************************
   2
   3  Intel 10 Gigabit PCI Express Linux driver
   4  Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6  This program is free software; you can redistribute it and/or modify it
   7  under the terms and conditions of the GNU General Public License,
   8  version 2, as published by the Free Software Foundation.
   9
  10  This program is distributed in the hope it will be useful, but WITHOUT
  11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  more details.
  14
  15  You should have received a copy of the GNU General Public License along with
  16  this program; if not, write to the Free Software Foundation, Inc.,
  17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19  The full GNU General Public License is included in this distribution in
  20  the file called "COPYING".
  21
  22  Contact Information:
  23  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26*******************************************************************************/
  27
  28#ifndef _DCB_82599_CONFIG_H_
  29#define _DCB_82599_CONFIG_H_
  30
  31/* DCB register definitions */
  32#define IXGBE_RTTDCS_TDPAC      0x00000001 /* 0 Round Robin,
  33                                            * 1 WSP - Weighted Strict Priority
  34                                            */
  35#define IXGBE_RTTDCS_VMPAC      0x00000002 /* 0 Round Robin,
  36                                            * 1 WRR - Weighted Round Robin
  37                                            */
  38#define IXGBE_RTTDCS_TDRM       0x00000010 /* Transmit Recycle Mode */
  39#define IXGBE_RTTDCS_ARBDIS     0x00000040 /* DCB arbiter disable */
  40#define IXGBE_RTTDCS_BDPM       0x00400000 /* Bypass Data Pipe - must clear! */
  41#define IXGBE_RTTDCS_BPBFSM     0x00800000 /* Bypass PB Free Space - must
  42                                             * clear!
  43                                             */
  44#define IXGBE_RTTDCS_SPEED_CHG  0x80000000 /* Link speed change */
  45
  46/* Receive UP2TC mapping */
  47#define IXGBE_RTRUP2TC_UP_SHIFT 3
  48/* Transmit UP2TC mapping */
  49#define IXGBE_RTTUP2TC_UP_SHIFT 3
  50
  51#define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */
  52#define IXGBE_RTRPT4C_BWG_SHIFT 9  /* Offset to BWG index */
  53#define IXGBE_RTRPT4C_GSP       0x40000000 /* GSP enable bit */
  54#define IXGBE_RTRPT4C_LSP       0x80000000 /* LSP enable bit */
  55
  56#define IXGBE_RDRXCTL_MPBEN     0x00000010 /* DMA config for multiple packet
  57                                            * buffers enable
  58                                            */
  59#define IXGBE_RDRXCTL_MCEN      0x00000040 /* DMA config for multiple cores
  60                                            * (RSS) enable
  61                                            */
  62
  63/* RTRPCS Bit Masks */
  64#define IXGBE_RTRPCS_RRM        0x00000002 /* Receive Recycle Mode enable */
  65/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
  66#define IXGBE_RTRPCS_RAC        0x00000004
  67#define IXGBE_RTRPCS_ARBDIS     0x00000040 /* Arbitration disable bit */
  68
  69/* RTTDT2C Bit Masks */
  70#define IXGBE_RTTDT2C_MCL_SHIFT 12
  71#define IXGBE_RTTDT2C_BWG_SHIFT 9
  72#define IXGBE_RTTDT2C_GSP       0x40000000
  73#define IXGBE_RTTDT2C_LSP       0x80000000
  74
  75#define IXGBE_RTTPT2C_MCL_SHIFT 12
  76#define IXGBE_RTTPT2C_BWG_SHIFT 9
  77#define IXGBE_RTTPT2C_GSP       0x40000000
  78#define IXGBE_RTTPT2C_LSP       0x80000000
  79
  80/* RTTPCS Bit Masks */
  81#define IXGBE_RTTPCS_TPPAC      0x00000020 /* 0 Round Robin,
  82                                            * 1 SP - Strict Priority
  83                                            */
  84#define IXGBE_RTTPCS_ARBDIS     0x00000040 /* Arbiter disable */
  85#define IXGBE_RTTPCS_TPRM       0x00000100 /* Transmit Recycle Mode enable */
  86#define IXGBE_RTTPCS_ARBD_SHIFT 22
  87#define IXGBE_RTTPCS_ARBD_DCB   0x4        /* Arbitration delay in DCB mode */
  88
  89#define IXGBE_TXPBSIZE_20KB     0x00005000 /* 20KB Packet Buffer */
  90#define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
  91#define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
  92#define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
  93#define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
  94#define IXGBE_RXPBSIZE_128KB    0x00020000 /* 128KB Packet Buffer */
  95#define IXGBE_TXPBSIZE_MAX      0x00028000 /* 160KB Packet Buffer*/
  96
  97#define IXGBE_TXPBTHRESH_DCB    0xA        /* THRESH value for DCB mode */
  98#define IXGBE_TXPKT_SIZE_MAX    0xA        /* Max Tx Packet size  */
  99
 100/* SECTXMINIFG DCB */
 101#define IXGBE_SECTX_DCB         0x00001F00 /* DCB TX Buffer IFG */
 102
 103
 104/* DCB hardware-specific driver APIs */
 105
 106/* DCB PFC functions */
 107s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en);
 108
 109/* DCB hw initialization */
 110s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
 111                                        u16 *refill,
 112                                        u16 *max,
 113                                        u8 *bwg_id,
 114                                        u8 *prio_type,
 115                                        u8 *prio_tc);
 116
 117s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
 118                                                u16 *refill,
 119                                                u16 *max,
 120                                                u8 *bwg_id,
 121                                                u8 *prio_type);
 122
 123s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
 124                                                u16 *refill,
 125                                                u16 *max,
 126                                                u8 *bwg_id,
 127                                                u8 *prio_type,
 128                                                u8 *prio_tc);
 129
 130s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw,
 131                              u8 rx_pba, u8 pfc_en, u16 *refill,
 132                              u16 *max, u8 *bwg_id, u8 *prio_type,
 133                              u8 *prio_tc);
 134
 135#endif /* _DCB_82599_CONFIG_H */
 136