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28#ifndef _IXGBE_TYPE_H_
29#define _IXGBE_TYPE_H_
30
31#include <linux/types.h>
32#include <linux/mdio.h>
33#include <linux/netdevice.h>
34
35
36#define IXGBE_INTEL_VENDOR_ID 0x8086
37
38
39#define IXGBE_DEV_ID_82598 0x10B6
40#define IXGBE_DEV_ID_82598_BX 0x1508
41#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
42#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
43#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
44#define IXGBE_DEV_ID_82598AT 0x10C8
45#define IXGBE_DEV_ID_82598AT2 0x150B
46#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
47#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
48#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
49#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
50#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
51#define IXGBE_DEV_ID_82599_KX4 0x10F7
52#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
53#define IXGBE_DEV_ID_82599_KR 0x1517
54#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
55#define IXGBE_DEV_ID_82599_CX4 0x10F9
56#define IXGBE_DEV_ID_82599_SFP 0x10FB
57#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a
58#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
59#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
60#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
61#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
62#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
63#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
64#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
65#define IXGBE_DEV_ID_82599_LS 0x154F
66#define IXGBE_DEV_ID_X540T 0x1528
67
68
69#define IXGBE_CTRL 0x00000
70#define IXGBE_STATUS 0x00008
71#define IXGBE_CTRL_EXT 0x00018
72#define IXGBE_ESDP 0x00020
73#define IXGBE_EODSDP 0x00028
74#define IXGBE_I2CCTL 0x00028
75#define IXGBE_LEDCTL 0x00200
76#define IXGBE_FRTIMER 0x00048
77#define IXGBE_TCPTIMER 0x0004C
78#define IXGBE_CORESPARE 0x00600
79#define IXGBE_EXVET 0x05078
80
81
82#define IXGBE_EEC 0x10010
83#define IXGBE_EERD 0x10014
84#define IXGBE_EEWR 0x10018
85#define IXGBE_FLA 0x1001C
86#define IXGBE_EEMNGCTL 0x10110
87#define IXGBE_EEMNGDATA 0x10114
88#define IXGBE_FLMNGCTL 0x10118
89#define IXGBE_FLMNGDATA 0x1011C
90#define IXGBE_FLMNGCNT 0x10120
91#define IXGBE_FLOP 0x1013C
92#define IXGBE_GRC 0x10200
93
94
95#define IXGBE_GRC_MNG 0x00000001
96#define IXGBE_GRC_APME 0x00000002
97
98#define IXGBE_VPDDIAG0 0x10204
99#define IXGBE_VPDDIAG1 0x10208
100
101
102#define IXGBE_I2C_CLK_IN 0x00000001
103#define IXGBE_I2C_CLK_OUT 0x00000002
104#define IXGBE_I2C_DATA_IN 0x00000004
105#define IXGBE_I2C_DATA_OUT 0x00000008
106
107
108#define IXGBE_EICR 0x00800
109#define IXGBE_EICS 0x00808
110#define IXGBE_EIMS 0x00880
111#define IXGBE_EIMC 0x00888
112#define IXGBE_EIAC 0x00810
113#define IXGBE_EIAM 0x00890
114#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
115#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
116#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
117#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
118
119
120
121
122
123#define IXGBE_MAX_INT_RATE 488281
124#define IXGBE_MIN_INT_RATE 956
125#define IXGBE_MAX_EITR 0x00000FF8
126#define IXGBE_MIN_EITR 8
127#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
128 (0x012300 + (((_i) - 24) * 4)))
129#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
130#define IXGBE_EITR_LLI_MOD 0x00008000
131#define IXGBE_EITR_CNT_WDIS 0x80000000
132#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4))
133#define IXGBE_IVAR_MISC 0x00A00
134#define IXGBE_EITRSEL 0x00894
135#define IXGBE_MSIXT 0x00000
136#define IXGBE_MSIXPBA 0x02000
137#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
138#define IXGBE_GPIE 0x00898
139
140
141#define IXGBE_FCADBUL 0x03210
142#define IXGBE_FCADBUH 0x03214
143#define IXGBE_FCAMACL 0x04328
144#define IXGBE_FCAMACH 0x0432C
145#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4))
146#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4))
147#define IXGBE_PFCTOP 0x03008
148#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4))
149#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8))
150#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8))
151#define IXGBE_FCRTV 0x032A0
152#define IXGBE_FCCFG 0x03D00
153#define IXGBE_TFCS 0x0CE00
154
155
156#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
157 (0x0D000 + ((_i - 64) * 0x40)))
158#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
159 (0x0D004 + ((_i - 64) * 0x40)))
160#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
161 (0x0D008 + ((_i - 64) * 0x40)))
162#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
163 (0x0D010 + ((_i - 64) * 0x40)))
164#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
165 (0x0D018 + ((_i - 64) * 0x40)))
166#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
167 (0x0D028 + ((_i - 64) * 0x40)))
168#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
169 (0x0D02C + ((_i - 64) * 0x40)))
170#define IXGBE_RSCDBU 0x03028
171#define IXGBE_RDDCC 0x02F20
172#define IXGBE_RXMEMWRAP 0x03190
173#define IXGBE_STARCTRL 0x03024
174
175
176
177
178
179
180#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
181 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
182 (0x0D014 + ((_i - 64) * 0x40))))
183
184
185
186
187
188
189#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
190 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
191 (0x0D00C + ((_i - 64) * 0x40))))
192#define IXGBE_RDRXCTL 0x02F00
193#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
194
195#define IXGBE_RXCTRL 0x03000
196#define IXGBE_DROPEN 0x03D04
197#define IXGBE_RXPBSIZE_SHIFT 10
198
199
200#define IXGBE_RXCSUM 0x05000
201#define IXGBE_RFCTL 0x05008
202#define IXGBE_DRECCCTL 0x02F08
203#define IXGBE_DRECCCTL_DISABLE 0
204
205#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
206#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
207 (0x0A200 + ((_i) * 8)))
208#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
209 (0x0A204 + ((_i) * 8)))
210#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
211#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
212
213#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
214 (0x0EA00 + ((_i) * 4)))
215
216#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
217
218#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
219#define IXGBE_FCTRL 0x05080
220#define IXGBE_VLNCTRL 0x05088
221#define IXGBE_MCSTCTRL 0x05090
222#define IXGBE_MRQC 0x05818
223#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4))
224#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4))
225#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4))
226#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4))
227#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4))
228#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4))
229#define IXGBE_SYNQF 0x0EC30
230#define IXGBE_RQTC 0x0EC70
231#define IXGBE_MTQC 0x08120
232#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4))
233#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))
234#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))
235#define IXGBE_VT_CTL 0x051B0
236#define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i)))
237#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i)))
238#define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i)))
239#define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i)))
240#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
241#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
242#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
243#define IXGBE_QDE 0x2F04
244#define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4))
245#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4))
246#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
247#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
248#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
249#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
250#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4))
251#define IXGBE_RXFECCERR0 0x051B8
252#define IXGBE_LLITHRESH 0x0EC90
253#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4))
254#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4))
255#define IXGBE_IMIRVP 0x05AC0
256#define IXGBE_VMD_CTL 0x0581C
257#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4))
258#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4))
259
260
261#define IXGBE_FDIRCTRL 0x0EE00
262#define IXGBE_FDIRHKEY 0x0EE68
263#define IXGBE_FDIRSKEY 0x0EE6C
264#define IXGBE_FDIRDIP4M 0x0EE3C
265#define IXGBE_FDIRSIP4M 0x0EE40
266#define IXGBE_FDIRTCPM 0x0EE44
267#define IXGBE_FDIRUDPM 0x0EE48
268#define IXGBE_FDIRIP6M 0x0EE74
269#define IXGBE_FDIRM 0x0EE70
270
271
272#define IXGBE_FDIRFREE 0x0EE38
273#define IXGBE_FDIRLEN 0x0EE4C
274#define IXGBE_FDIRUSTAT 0x0EE50
275#define IXGBE_FDIRFSTAT 0x0EE54
276#define IXGBE_FDIRMATCH 0x0EE58
277#define IXGBE_FDIRMISS 0x0EE5C
278
279
280#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4))
281#define IXGBE_FDIRIPSA 0x0EE18
282#define IXGBE_FDIRIPDA 0x0EE1C
283#define IXGBE_FDIRPORT 0x0EE20
284#define IXGBE_FDIRVLAN 0x0EE24
285#define IXGBE_FDIRHASH 0x0EE28
286#define IXGBE_FDIRCMD 0x0EE2C
287
288
289#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40))
290#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
291#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
292#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
293#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
294#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
295#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
296#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
297#define IXGBE_DTXCTL 0x07E00
298
299#define IXGBE_DMATXCTL 0x04A80
300#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4))
301#define IXGBE_PFDTXGSWC 0x08220
302#define IXGBE_DTXMXSZRQ 0x08100
303#define IXGBE_DTXTCPFLGL 0x04A88
304#define IXGBE_DTXTCPFLGH 0x04A8C
305#define IXGBE_LBDRPEN 0x0CA00
306#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4))
307
308#define IXGBE_DMATXCTL_TE 0x1
309#define IXGBE_DMATXCTL_NS 0x2
310#define IXGBE_DMATXCTL_GDV 0x8
311#define IXGBE_DMATXCTL_VT_SHIFT 16
312
313#define IXGBE_PFDTXGSWC_VT_LBEN 0x1
314
315
316#define IXGBE_SPOOF_MACAS_MASK 0xFF
317#define IXGBE_SPOOF_VLANAS_MASK 0xFF00
318#define IXGBE_SPOOF_VLANAS_SHIFT 8
319#define IXGBE_PFVFSPOOF_REG_COUNT 8
320
321#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4))
322
323#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
324#define IXGBE_TIPG 0x0CB00
325#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4))
326#define IXGBE_MNGTXMAP 0x0CD10
327#define IXGBE_TIPG_FIBER_DEFAULT 3
328#define IXGBE_TXPBSIZE_SHIFT 10
329
330
331#define IXGBE_WUC 0x05800
332#define IXGBE_WUFC 0x05808
333#define IXGBE_WUS 0x05810
334#define IXGBE_IPAV 0x05838
335#define IXGBE_IP4AT 0x05840
336#define IXGBE_IP6AT 0x05880
337
338#define IXGBE_WUPL 0x05900
339#define IXGBE_WUPM 0x05A00
340#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100))
341#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100))
342
343
344#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
345#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
346
347
348#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
349#define IXGBE_FHFT_LENGTH_OFFSET 0xFC
350#define IXGBE_FHFT_LENGTH_MASK 0x0FF
351
352
353
354#define IXGBE_WUC_PME_EN 0x00000002
355#define IXGBE_WUC_PME_STATUS 0x00000004
356#define IXGBE_WUC_WKEN 0x00000010
357
358
359#define IXGBE_WUFC_LNKC 0x00000001
360#define IXGBE_WUFC_MAG 0x00000002
361#define IXGBE_WUFC_EX 0x00000004
362#define IXGBE_WUFC_MC 0x00000008
363#define IXGBE_WUFC_BC 0x00000010
364#define IXGBE_WUFC_ARP 0x00000020
365#define IXGBE_WUFC_IPV4 0x00000040
366#define IXGBE_WUFC_IPV6 0x00000080
367#define IXGBE_WUFC_MNG 0x00000100
368
369#define IXGBE_WUFC_IGNORE_TCO 0x00008000
370#define IXGBE_WUFC_FLX0 0x00010000
371#define IXGBE_WUFC_FLX1 0x00020000
372#define IXGBE_WUFC_FLX2 0x00040000
373#define IXGBE_WUFC_FLX3 0x00080000
374#define IXGBE_WUFC_FLX4 0x00100000
375#define IXGBE_WUFC_FLX5 0x00200000
376#define IXGBE_WUFC_FLX_FILTERS 0x000F0000
377#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000
378#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF
379#define IXGBE_WUFC_FLX_OFFSET 16
380
381
382#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
383#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
384#define IXGBE_WUS_EX IXGBE_WUFC_EX
385#define IXGBE_WUS_MC IXGBE_WUFC_MC
386#define IXGBE_WUS_BC IXGBE_WUFC_BC
387#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
388#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
389#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
390#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
391#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
392#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
393#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
394#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
395#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
396#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
397#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
398
399
400#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
401
402
403#define IXGBE_RMCS 0x03D00
404#define IXGBE_DPMCS 0x07F40
405#define IXGBE_PDPMCS 0x0CD00
406#define IXGBE_RUPPBMR 0x050A0
407#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4))
408#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4))
409#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40))
410#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40))
411#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4))
412#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4))
413
414
415
416#define IXGBE_SECTXCTRL 0x08800
417#define IXGBE_SECTXSTAT 0x08804
418#define IXGBE_SECTXBUFFAF 0x08808
419#define IXGBE_SECTXMINIFG 0x08810
420#define IXGBE_SECRXCTRL 0x08D00
421#define IXGBE_SECRXSTAT 0x08D04
422
423
424#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
425#define IXGBE_SECTXCTRL_TX_DIS 0x00000002
426#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
427
428#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
429#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
430
431#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
432#define IXGBE_SECRXCTRL_RX_DIS 0x00000002
433
434#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
435#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
436
437
438#define IXGBE_LSECTXCAP 0x08A00
439#define IXGBE_LSECRXCAP 0x08F00
440#define IXGBE_LSECTXCTRL 0x08A04
441#define IXGBE_LSECTXSCL 0x08A08
442#define IXGBE_LSECTXSCH 0x08A0C
443#define IXGBE_LSECTXSA 0x08A10
444#define IXGBE_LSECTXPN0 0x08A14
445#define IXGBE_LSECTXPN1 0x08A18
446#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n)))
447#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n)))
448#define IXGBE_LSECRXCTRL 0x08F04
449#define IXGBE_LSECRXSCL 0x08F08
450#define IXGBE_LSECRXSCH 0x08F0C
451#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i)))
452#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i)))
453#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
454#define IXGBE_LSECTXUT 0x08A3C
455#define IXGBE_LSECTXPKTE 0x08A40
456#define IXGBE_LSECTXPKTP 0x08A44
457#define IXGBE_LSECTXOCTE 0x08A48
458#define IXGBE_LSECTXOCTP 0x08A4C
459#define IXGBE_LSECRXUT 0x08F40
460#define IXGBE_LSECRXOCTD 0x08F44
461#define IXGBE_LSECRXOCTV 0x08F48
462#define IXGBE_LSECRXBAD 0x08F4C
463#define IXGBE_LSECRXNOSCI 0x08F50
464#define IXGBE_LSECRXUNSCI 0x08F54
465#define IXGBE_LSECRXUNCH 0x08F58
466#define IXGBE_LSECRXDELAY 0x08F5C
467#define IXGBE_LSECRXLATE 0x08F60
468#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n)))
469#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n)))
470#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n)))
471#define IXGBE_LSECRXUNSA 0x08F7C
472#define IXGBE_LSECRXNUSA 0x08F80
473
474
475#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
476#define IXGBE_LSECTXCAP_SUM_SHIFT 16
477#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
478#define IXGBE_LSECRXCAP_SUM_SHIFT 16
479
480#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
481#define IXGBE_LSECTXCTRL_DISABLE 0x0
482#define IXGBE_LSECTXCTRL_AUTH 0x1
483#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
484#define IXGBE_LSECTXCTRL_AISCI 0x00000020
485#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
486#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
487
488#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
489#define IXGBE_LSECRXCTRL_EN_SHIFT 2
490#define IXGBE_LSECRXCTRL_DISABLE 0x0
491#define IXGBE_LSECRXCTRL_CHECK 0x1
492#define IXGBE_LSECRXCTRL_STRICT 0x2
493#define IXGBE_LSECRXCTRL_DROP 0x3
494#define IXGBE_LSECRXCTRL_PLSH 0x00000040
495#define IXGBE_LSECRXCTRL_RP 0x00000080
496#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
497
498
499#define IXGBE_IPSTXIDX 0x08900
500#define IXGBE_IPSTXSALT 0x08904
501#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i)))
502#define IXGBE_IPSRXIDX 0x08E00
503#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i)))
504#define IXGBE_IPSRXSPI 0x08E14
505#define IXGBE_IPSRXIPIDX 0x08E18
506#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i)))
507#define IXGBE_IPSRXSALT 0x08E2C
508#define IXGBE_IPSRXMOD 0x08E30
509
510#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
511
512
513#define IXGBE_RTRPCS 0x02430
514#define IXGBE_RTTDCS 0x04900
515#define IXGBE_RTTDCS_ARBDIS 0x00000040
516#define IXGBE_RTTPCS 0x0CD00
517#define IXGBE_RTRUP2TC 0x03020
518#define IXGBE_RTTUP2TC 0x0C800
519#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4))
520#define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4))
521#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4))
522#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4))
523#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4))
524#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4))
525#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4))
526#define IXGBE_RTTDQSEL 0x04904
527#define IXGBE_RTTDT1C 0x04908
528#define IXGBE_RTTDT1S 0x0490C
529#define IXGBE_RTTDTECC 0x04990
530#define IXGBE_RTTDTECC_NO_BCN 0x00000100
531#define IXGBE_RTTBCNRC 0x04984
532#define IXGBE_RTTBCNRC_RS_ENA 0x80000000
533#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
534#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
535#define IXGBE_RTTBCNRC_RF_INT_MASK \
536 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
537
538
539
540#define IXGBE_FCPTRL 0x02410
541#define IXGBE_FCPTRH 0x02414
542#define IXGBE_FCBUFF 0x02418
543#define IXGBE_FCDMARW 0x02420
544#define IXGBE_FCINVST0 0x03FC0
545#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
546#define IXGBE_FCBUFF_VALID (1 << 0)
547#define IXGBE_FCBUFF_BUFFSIZE (3 << 3)
548#define IXGBE_FCBUFF_WRCONTX (1 << 7)
549#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00
550#define IXGBE_FCBUFF_OFFSET 0xffff0000
551#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
552#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
553#define IXGBE_FCBUFF_OFFSET_SHIFT 16
554#define IXGBE_FCDMARW_WE (1 << 14)
555#define IXGBE_FCDMARW_RE (1 << 15)
556#define IXGBE_FCDMARW_FCOESEL 0x000001ff
557#define IXGBE_FCDMARW_LASTSIZE 0xffff0000
558#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
559
560
561#define IXGBE_TEOFF 0x04A94
562#define IXGBE_TSOFF 0x04A98
563#define IXGBE_REOFF 0x05158
564#define IXGBE_RSOFF 0x051F8
565
566#define IXGBE_FCFLT 0x05108
567#define IXGBE_FCFLTRW 0x05110
568#define IXGBE_FCPARAM 0x051d8
569#define IXGBE_FCFLT_VALID (1 << 0)
570#define IXGBE_FCFLT_FIRST (1 << 1)
571#define IXGBE_FCFLT_SEQID 0x00ff0000
572#define IXGBE_FCFLT_SEQCNT 0xff000000
573#define IXGBE_FCFLTRW_RVALDT (1 << 13)
574#define IXGBE_FCFLTRW_WE (1 << 14)
575#define IXGBE_FCFLTRW_RE (1 << 15)
576
577#define IXGBE_FCRXCTRL 0x05100
578#define IXGBE_FCRXCTRL_FCOELLI (1 << 0)
579#define IXGBE_FCRXCTRL_SAVBAD (1 << 1)
580#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2)
581#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3)
582#define IXGBE_FCRXCTRL_ALLH (1 << 4)
583#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5)
584#define IXGBE_FCRXCTRL_ICRC (1 << 6)
585#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7)
586#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00
587#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
588
589#define IXGBE_FCRECTL 0x0ED00
590#define IXGBE_FCRETA0 0x0ED10
591#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4))
592#define IXGBE_FCRECTL_ENA 0x1
593#define IXGBE_FCRETA_SIZE 8
594#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f
595
596
597#define IXGBE_CRCERRS 0x04000
598#define IXGBE_ILLERRC 0x04004
599#define IXGBE_ERRBC 0x04008
600#define IXGBE_MSPDC 0x04010
601#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4))
602#define IXGBE_MLFC 0x04034
603#define IXGBE_MRFC 0x04038
604#define IXGBE_RLEC 0x04040
605#define IXGBE_LXONTXC 0x03F60
606#define IXGBE_LXONRXC 0x0CF60
607#define IXGBE_LXOFFTXC 0x03F68
608#define IXGBE_LXOFFRXC 0x0CF68
609#define IXGBE_LXONRXCNT 0x041A4
610#define IXGBE_LXOFFRXCNT 0x041A8
611#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4))
612#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4))
613#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4))
614#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4))
615#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4))
616#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4))
617#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4))
618#define IXGBE_PRC64 0x0405C
619#define IXGBE_PRC127 0x04060
620#define IXGBE_PRC255 0x04064
621#define IXGBE_PRC511 0x04068
622#define IXGBE_PRC1023 0x0406C
623#define IXGBE_PRC1522 0x04070
624#define IXGBE_GPRC 0x04074
625#define IXGBE_BPRC 0x04078
626#define IXGBE_MPRC 0x0407C
627#define IXGBE_GPTC 0x04080
628#define IXGBE_GORCL 0x04088
629#define IXGBE_GORCH 0x0408C
630#define IXGBE_GOTCL 0x04090
631#define IXGBE_GOTCH 0x04094
632#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4))
633#define IXGBE_RUC 0x040A4
634#define IXGBE_RFC 0x040A8
635#define IXGBE_ROC 0x040AC
636#define IXGBE_RJC 0x040B0
637#define IXGBE_MNGPRC 0x040B4
638#define IXGBE_MNGPDC 0x040B8
639#define IXGBE_MNGPTC 0x0CF90
640#define IXGBE_TORL 0x040C0
641#define IXGBE_TORH 0x040C4
642#define IXGBE_TPR 0x040D0
643#define IXGBE_TPT 0x040D4
644#define IXGBE_PTC64 0x040D8
645#define IXGBE_PTC127 0x040DC
646#define IXGBE_PTC255 0x040E0
647#define IXGBE_PTC511 0x040E4
648#define IXGBE_PTC1023 0x040E8
649#define IXGBE_PTC1522 0x040EC
650#define IXGBE_MPTC 0x040F0
651#define IXGBE_BPTC 0x040F4
652#define IXGBE_XEC 0x04120
653#define IXGBE_SSVPC 0x08780
654
655#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
656#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
657 (0x08600 + ((_i) * 4)))
658#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
659
660#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40))
661#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40))
662#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40))
663#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40))
664#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40))
665#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40))
666#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40))
667#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8))
668#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8))
669#define IXGBE_FCCRC 0x05118
670#define IXGBE_FCOERPDC 0x0241C
671#define IXGBE_FCLAST 0x02424
672#define IXGBE_FCOEPRC 0x02428
673#define IXGBE_FCOEDWRC 0x0242C
674#define IXGBE_FCOEPTC 0x08784
675#define IXGBE_FCOEDWTC 0x08788
676#define IXGBE_O2BGPTC 0x041C4
677#define IXGBE_O2BSPC 0x087B0
678#define IXGBE_B2OSPC 0x041C0
679#define IXGBE_B2OGPRC 0x02F90
680#define IXGBE_PCRC8ECL 0x0E810
681#define IXGBE_PCRC8ECH 0x0E811
682#define IXGBE_PCRC8ECH_MASK 0x1F
683#define IXGBE_LDPCECL 0x0E820
684#define IXGBE_LDPCECH 0x0E821
685
686
687#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4))
688#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4))
689#define IXGBE_MANC 0x05820
690#define IXGBE_MFVAL 0x05824
691#define IXGBE_MANC2H 0x05860
692#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4))
693#define IXGBE_MIPAF 0x058B0
694#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8))
695#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8))
696#define IXGBE_FTFT 0x09400
697#define IXGBE_METF(_i) (0x05190 + ((_i) * 4))
698#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4))
699#define IXGBE_LSWFW 0x15014
700
701
702#define IXGBE_HICR 0x15F00
703#define IXGBE_FWSTS 0x15F0C
704#define IXGBE_HSMC0R 0x15F04
705#define IXGBE_HSMC1R 0x15F08
706#define IXGBE_SWSR 0x15F10
707#define IXGBE_HFDR 0x15FE8
708#define IXGBE_FLEX_MNG 0x15800
709
710
711#define IXGBE_GCR 0x11000
712#define IXGBE_GTV 0x11004
713#define IXGBE_FUNCTAG 0x11008
714#define IXGBE_GLT 0x1100C
715#define IXGBE_GSCL_1 0x11010
716#define IXGBE_GSCL_2 0x11014
717#define IXGBE_GSCL_3 0x11018
718#define IXGBE_GSCL_4 0x1101C
719#define IXGBE_GSCN_0 0x11020
720#define IXGBE_GSCN_1 0x11024
721#define IXGBE_GSCN_2 0x11028
722#define IXGBE_GSCN_3 0x1102C
723#define IXGBE_FACTPS 0x10150
724#define IXGBE_PCIEANACTL 0x11040
725#define IXGBE_SWSM 0x10140
726#define IXGBE_FWSM 0x10148
727#define IXGBE_GSSR 0x10160
728#define IXGBE_MREVID 0x11064
729#define IXGBE_DCA_ID 0x11070
730#define IXGBE_DCA_CTRL 0x11074
731#define IXGBE_SWFW_SYNC IXGBE_GSSR
732
733
734#define IXGBE_GCR_EXT 0x11050
735#define IXGBE_GSCL_5_82599 0x11030
736#define IXGBE_GSCL_6_82599 0x11034
737#define IXGBE_GSCL_7_82599 0x11038
738#define IXGBE_GSCL_8_82599 0x1103C
739#define IXGBE_PHYADR_82599 0x11040
740#define IXGBE_PHYDAT_82599 0x11044
741#define IXGBE_PHYCTL_82599 0x11048
742#define IXGBE_PBACLR_82599 0x11068
743#define IXGBE_CIAA_82599 0x11088
744#define IXGBE_CIAD_82599 0x1108C
745#define IXGBE_PICAUSE 0x110B0
746#define IXGBE_PIENA 0x110B8
747#define IXGBE_CDQ_MBR_82599 0x110B4
748#define IXGBE_PCIESPARE 0x110BC
749#define IXGBE_MISC_REG_82599 0x110F0
750#define IXGBE_ECC_CTRL_0_82599 0x11100
751#define IXGBE_ECC_CTRL_1_82599 0x11104
752#define IXGBE_ECC_STATUS_82599 0x110E0
753#define IXGBE_BAR_CTRL_82599 0x110F4
754
755
756#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
757#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
758#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
759#define IXGBE_GCR_CAP_VER2 0x00040000
760
761#define IXGBE_GCR_EXT_MSIX_EN 0x80000000
762#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
763#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
764#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
765#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
766 IXGBE_GCR_EXT_VT_MODE_64)
767
768
769#define IXGBE_TSYNCRXCTL 0x05188
770#define IXGBE_TSYNCTXCTL 0x08C00
771#define IXGBE_RXSTMPL 0x051E8
772#define IXGBE_RXSTMPH 0x051A4
773#define IXGBE_RXSATRL 0x051A0
774#define IXGBE_RXSATRH 0x051A8
775#define IXGBE_RXMTRL 0x05120
776#define IXGBE_TXSTMPL 0x08C04
777#define IXGBE_TXSTMPH 0x08C08
778#define IXGBE_SYSTIML 0x08C0C
779#define IXGBE_SYSTIMH 0x08C10
780#define IXGBE_TIMINCA 0x08C14
781#define IXGBE_TIMADJL 0x08C18
782#define IXGBE_TIMADJH 0x08C1C
783#define IXGBE_TSAUXC 0x08C20
784#define IXGBE_TRGTTIML0 0x08C24
785#define IXGBE_TRGTTIMH0 0x08C28
786#define IXGBE_TRGTTIML1 0x08C2C
787#define IXGBE_TRGTTIMH1 0x08C30
788#define IXGBE_FREQOUT0 0x08C34
789#define IXGBE_FREQOUT1 0x08C38
790#define IXGBE_AUXSTMPL0 0x08C3C
791#define IXGBE_AUXSTMPH0 0x08C40
792#define IXGBE_AUXSTMPL1 0x08C44
793#define IXGBE_AUXSTMPH1 0x08C48
794
795
796#define IXGBE_RDSTATCTL 0x02C20
797#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4))
798#define IXGBE_RDHMPN 0x02F08
799#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
800#define IXGBE_RDPROBE 0x02F20
801#define IXGBE_RDMAM 0x02F30
802#define IXGBE_RDMAD 0x02F34
803#define IXGBE_TDSTATCTL 0x07C20
804#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4))
805#define IXGBE_TDHMPN 0x07F08
806#define IXGBE_TDHMPN2 0x082FC
807#define IXGBE_TXDESCIC 0x082CC
808#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
809#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
810#define IXGBE_TDPROBE 0x07F20
811#define IXGBE_TXBUFCTRL 0x0C600
812#define IXGBE_TXBUFDATA0 0x0C610
813#define IXGBE_TXBUFDATA1 0x0C614
814#define IXGBE_TXBUFDATA2 0x0C618
815#define IXGBE_TXBUFDATA3 0x0C61C
816#define IXGBE_RXBUFCTRL 0x03600
817#define IXGBE_RXBUFDATA0 0x03610
818#define IXGBE_RXBUFDATA1 0x03614
819#define IXGBE_RXBUFDATA2 0x03618
820#define IXGBE_RXBUFDATA3 0x0361C
821#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4))
822#define IXGBE_RFVAL 0x050A4
823#define IXGBE_MDFTC1 0x042B8
824#define IXGBE_MDFTC2 0x042C0
825#define IXGBE_MDFTFIFO1 0x042C4
826#define IXGBE_MDFTFIFO2 0x042C8
827#define IXGBE_MDFTS 0x042CC
828#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4))
829#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4))
830#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4))
831#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4))
832#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4))
833#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4))
834#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4))
835#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4))
836#define IXGBE_PCIEECCCTL 0x1106C
837#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4))
838#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4))
839#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4))
840#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4))
841#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4))
842#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4))
843#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4))
844#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4))
845#define IXGBE_PCIEECCCTL0 0x11100
846#define IXGBE_PCIEECCCTL1 0x11104
847#define IXGBE_RXDBUECC 0x03F70
848#define IXGBE_TXDBUECC 0x0CF70
849#define IXGBE_RXDBUEST 0x03F74
850#define IXGBE_TXDBUEST 0x0CF74
851#define IXGBE_PBTXECC 0x0C300
852#define IXGBE_PBRXECC 0x03300
853#define IXGBE_GHECCR 0x110B0
854
855
856#define IXGBE_PCS1GCFIG 0x04200
857#define IXGBE_PCS1GLCTL 0x04208
858#define IXGBE_PCS1GLSTA 0x0420C
859#define IXGBE_PCS1GDBG0 0x04210
860#define IXGBE_PCS1GDBG1 0x04214
861#define IXGBE_PCS1GANA 0x04218
862#define IXGBE_PCS1GANLP 0x0421C
863#define IXGBE_PCS1GANNP 0x04220
864#define IXGBE_PCS1GANLPNP 0x04224
865#define IXGBE_HLREG0 0x04240
866#define IXGBE_HLREG1 0x04244
867#define IXGBE_PAP 0x04248
868#define IXGBE_MACA 0x0424C
869#define IXGBE_APAE 0x04250
870#define IXGBE_ARD 0x04254
871#define IXGBE_AIS 0x04258
872#define IXGBE_MSCA 0x0425C
873#define IXGBE_MSRWD 0x04260
874#define IXGBE_MLADD 0x04264
875#define IXGBE_MHADD 0x04268
876#define IXGBE_MAXFRS 0x04268
877#define IXGBE_TREG 0x0426C
878#define IXGBE_PCSS1 0x04288
879#define IXGBE_PCSS2 0x0428C
880#define IXGBE_XPCSS 0x04290
881#define IXGBE_MFLCN 0x04294
882#define IXGBE_SERDESC 0x04298
883#define IXGBE_MACS 0x0429C
884#define IXGBE_AUTOC 0x042A0
885#define IXGBE_LINKS 0x042A4
886#define IXGBE_LINKS2 0x04324
887#define IXGBE_AUTOC2 0x042A8
888#define IXGBE_AUTOC3 0x042AC
889#define IXGBE_ANLP1 0x042B0
890#define IXGBE_ANLP2 0x042B4
891#define IXGBE_MACC 0x04330
892#define IXGBE_ATLASCTL 0x04800
893#define IXGBE_MMNGC 0x042D0
894#define IXGBE_ANLPNP1 0x042D4
895#define IXGBE_ANLPNP2 0x042D8
896#define IXGBE_KRPCSFC 0x042E0
897#define IXGBE_KRPCSS 0x042E4
898#define IXGBE_FECS1 0x042E8
899#define IXGBE_FECS2 0x042EC
900#define IXGBE_SMADARCTL 0x14F10
901#define IXGBE_MPVC 0x04318
902#define IXGBE_SGMIIC 0x04314
903
904
905#define IXGBE_RXNFGPC 0x041B0
906#define IXGBE_RXNFGBCL 0x041B4
907#define IXGBE_RXNFGBCH 0x041B8
908#define IXGBE_RXDGPC 0x02F50
909#define IXGBE_RXDGBCL 0x02F54
910#define IXGBE_RXDGBCH 0x02F58
911#define IXGBE_RXDDGPC 0x02F5C
912#define IXGBE_RXDDGBCL 0x02F60
913#define IXGBE_RXDDGBCH 0x02F64
914#define IXGBE_RXLPBKGPC 0x02F68
915#define IXGBE_RXLPBKGBCL 0x02F6C
916#define IXGBE_RXLPBKGBCH 0x02F70
917#define IXGBE_RXDLPBKGPC 0x02F74
918#define IXGBE_RXDLPBKGBCL 0x02F78
919#define IXGBE_RXDLPBKGBCH 0x02F7C
920#define IXGBE_TXDGPC 0x087A0
921#define IXGBE_TXDGBCL 0x087A4
922#define IXGBE_TXDGBCH 0x087A8
923
924#define IXGBE_RXDSTATCTRL 0x02F40
925
926
927#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
928
929
930#define IXGBE_CORECTL 0x014F00
931
932#define IXGBE_BARCTRL 0x110F4
933#define IXGBE_BARCTRL_FLSIZE 0x0700
934#define IXGBE_BARCTRL_FLSIZE_SHIFT 8
935#define IXGBE_BARCTRL_CSRSIZE 0x2000
936
937
938#define IXGBE_RSCCTL_RSCEN 0x01
939#define IXGBE_RSCCTL_MAXDESC_1 0x00
940#define IXGBE_RSCCTL_MAXDESC_4 0x04
941#define IXGBE_RSCCTL_MAXDESC_8 0x08
942#define IXGBE_RSCCTL_MAXDESC_16 0x0C
943
944
945#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
946#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
947
948
949#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000
950#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002
951#define IXGBE_RDRXCTL_MVMEN 0x00000020
952#define IXGBE_RDRXCTL_DMAIDONE 0x00000008
953#define IXGBE_RDRXCTL_AGGDIS 0x00010000
954#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000
955#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000
956#define IXGBE_RDRXCTL_RSCACKC 0x02000000
957#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000
958
959
960#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
961#define IXGBE_RQTC_TC0_MASK (0x7 << 0)
962#define IXGBE_RQTC_TC1_MASK (0x7 << 4)
963#define IXGBE_RQTC_TC2_MASK (0x7 << 8)
964#define IXGBE_RQTC_TC3_MASK (0x7 << 12)
965#define IXGBE_RQTC_TC4_MASK (0x7 << 16)
966#define IXGBE_RQTC_TC5_MASK (0x7 << 20)
967#define IXGBE_RQTC_TC6_MASK (0x7 << 24)
968#define IXGBE_RQTC_TC7_MASK (0x7 << 28)
969
970
971#define IXGBE_PSRTYPE_RQPL_MASK 0x7
972#define IXGBE_PSRTYPE_RQPL_SHIFT 29
973
974
975#define IXGBE_CTRL_GIO_DIS 0x00000004
976#define IXGBE_CTRL_LNK_RST 0x00000008
977#define IXGBE_CTRL_RST 0x04000000
978
979
980#define IXGBE_FACTPS_LFS 0x40000000
981
982
983#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
984#define IXGBE_MHADD_MFS_SHIFT 16
985
986
987#define IXGBE_CTRL_EXT_PFRSTD 0x00004000
988#define IXGBE_CTRL_EXT_NS_DIS 0x00010000
989#define IXGBE_CTRL_EXT_RO_DIS 0x00020000
990#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000
991
992
993#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000
994#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001
995
996#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00
997#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02
998
999#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F
1000#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000
1001#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24
1002#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5)
1003#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6)
1004#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7)
1005#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9)
1006#define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13)
1007#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15)
1008
1009#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F
1010#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000
1011#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24
1012#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5)
1013#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11)
1014#define IXGBE_DCA_MAX_QUEUES_82598 16
1015
1016
1017#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF
1018#define IXGBE_MSCA_NP_ADDR_SHIFT 0
1019#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000
1020#define IXGBE_MSCA_DEV_TYPE_SHIFT 16
1021#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000
1022#define IXGBE_MSCA_PHY_ADDR_SHIFT 21
1023#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000
1024#define IXGBE_MSCA_OP_CODE_SHIFT 26
1025#define IXGBE_MSCA_ADDR_CYCLE 0x00000000
1026#define IXGBE_MSCA_WRITE 0x04000000
1027#define IXGBE_MSCA_READ 0x0C000000
1028#define IXGBE_MSCA_READ_AUTOINC 0x08000000
1029#define IXGBE_MSCA_ST_CODE_MASK 0x30000000
1030#define IXGBE_MSCA_ST_CODE_SHIFT 28
1031#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000
1032#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000
1033#define IXGBE_MSCA_MDI_COMMAND 0x40000000
1034#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000
1035
1036
1037#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
1038#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
1039#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
1040#define IXGBE_MSRWD_READ_DATA_SHIFT 16
1041
1042
1043#define IXGBE_ATLAS_PDN_LPBK 0x24
1044#define IXGBE_ATLAS_PDN_10G 0xB
1045#define IXGBE_ATLAS_PDN_1G 0xC
1046#define IXGBE_ATLAS_PDN_AN 0xD
1047
1048
1049#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
1050#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
1051#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
1052#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
1053#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
1054
1055
1056#define IXGBE_CORECTL_WRITE_CMD 0x00010000
1057
1058
1059
1060#define IXGBE_MDIO_COMMAND_TIMEOUT 100
1061
1062#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0
1063#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1
1064#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008
1065#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010
1066#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
1067#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
1068
1069#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A
1070#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B
1071#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C
1072
1073
1074#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400
1075#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17
1076#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000
1077#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000
1078#define IXGBE_MII_AUTONEG_REG 0x0
1079
1080#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
1081#define IXGBE_MAX_PHY_ADDR 32
1082
1083
1084#define TN1010_PHY_ID 0x00A19410
1085#define TNX_FW_REV 0xB
1086#define X540_PHY_ID 0x01540200
1087#define QT2022_PHY_ID 0x0043A400
1088#define ATH_PHY_ID 0x03429050
1089#define AQ_FW_REV 0x20
1090
1091
1092#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
1093
1094
1095#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1096#define IXGBE_PHY_INIT_END_NL 0xFFFF
1097#define IXGBE_CONTROL_MASK_NL 0xF000
1098#define IXGBE_DATA_MASK_NL 0x0FFF
1099#define IXGBE_CONTROL_SHIFT_NL 12
1100#define IXGBE_DELAY_NL 0
1101#define IXGBE_DATA_NL 1
1102#define IXGBE_CONTROL_NL 0x000F
1103#define IXGBE_CONTROL_EOL_NL 0x0FFF
1104#define IXGBE_CONTROL_SOL_NL 0x0000
1105
1106
1107#define IXGBE_SDP0_GPIEN 0x00000001
1108#define IXGBE_SDP1_GPIEN 0x00000002
1109#define IXGBE_SDP2_GPIEN 0x00000004
1110#define IXGBE_GPIE_MSIX_MODE 0x00000010
1111#define IXGBE_GPIE_OCD 0x00000020
1112#define IXGBE_GPIE_EIMEN 0x00000040
1113#define IXGBE_GPIE_EIAME 0x40000000
1114#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
1115#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
1116#define IXGBE_GPIE_VTMODE_MASK 0x0000C000
1117#define IXGBE_GPIE_VTMODE_16 0x00004000
1118#define IXGBE_GPIE_VTMODE_32 0x00008000
1119#define IXGBE_GPIE_VTMODE_64 0x0000C000
1120
1121
1122#define IXGBE_TFCS_TXOFF 0x00000001
1123#define IXGBE_TFCS_TXOFF0 0x00000100
1124#define IXGBE_TFCS_TXOFF1 0x00000200
1125#define IXGBE_TFCS_TXOFF2 0x00000400
1126#define IXGBE_TFCS_TXOFF3 0x00000800
1127#define IXGBE_TFCS_TXOFF4 0x00001000
1128#define IXGBE_TFCS_TXOFF5 0x00002000
1129#define IXGBE_TFCS_TXOFF6 0x00004000
1130#define IXGBE_TFCS_TXOFF7 0x00008000
1131
1132
1133#define IXGBE_TCPTIMER_KS 0x00000100
1134#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
1135#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
1136#define IXGBE_TCPTIMER_LOOP 0x00000800
1137#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1138
1139
1140#define IXGBE_HLREG0_TXCRCEN 0x00000001
1141#define IXGBE_HLREG0_RXCRCSTRP 0x00000002
1142#define IXGBE_HLREG0_JUMBOEN 0x00000004
1143#define IXGBE_HLREG0_TXPADEN 0x00000400
1144#define IXGBE_HLREG0_TXPAUSEEN 0x00001000
1145#define IXGBE_HLREG0_RXPAUSEEN 0x00004000
1146#define IXGBE_HLREG0_LPBK 0x00008000
1147#define IXGBE_HLREG0_MDCSPD 0x00010000
1148#define IXGBE_HLREG0_CONTMDC 0x00020000
1149#define IXGBE_HLREG0_CTRLFLTR 0x00040000
1150#define IXGBE_HLREG0_PREPEND 0x00F00000
1151#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000
1152#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000
1153#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000
1154#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000
1155
1156
1157#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
1158#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1159
1160
1161#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000
1162#define IXGBE_VT_CTL_REPLEN 0x40000000
1163#define IXGBE_VT_CTL_VT_ENABLE 0x00000001
1164#define IXGBE_VT_CTL_POOL_SHIFT 7
1165#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1166
1167
1168#define IXGBE_VMOLR_AUPE 0x01000000
1169#define IXGBE_VMOLR_ROMPE 0x02000000
1170#define IXGBE_VMOLR_ROPE 0x04000000
1171#define IXGBE_VMOLR_BAM 0x08000000
1172#define IXGBE_VMOLR_MPE 0x10000000
1173
1174
1175#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
1176
1177#define IXGBE_VF_INIT_TIMEOUT 200
1178
1179
1180#define IXGBE_RDHMPN_RDICADDR 0x007FF800
1181#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
1182#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1183#define IXGBE_TDHMPN_TDICADDR 0x003FF800
1184#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
1185#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1186
1187#define IXGBE_RDMAM_MEM_SEL_SHIFT 13
1188#define IXGBE_RDMAM_DWORD_SHIFT 9
1189#define IXGBE_RDMAM_DESC_COMP_FIFO 1
1190#define IXGBE_RDMAM_DFC_CMD_FIFO 2
1191#define IXGBE_RDMAM_TCN_STATUS_RAM 4
1192#define IXGBE_RDMAM_WB_COLL_FIFO 5
1193#define IXGBE_RDMAM_QSC_CNT_RAM 6
1194#define IXGBE_RDMAM_QSC_QUEUE_CNT 8
1195#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
1196#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
1197#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
1198#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
1199#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
1200#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
1201#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
1202#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
1203#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
1204#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
1205#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
1206#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
1207#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
1208#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
1209#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
1210
1211#define IXGBE_TXDESCIC_READY 0x80000000
1212
1213
1214#define IXGBE_RXCSUM_IPPCSE 0x00001000
1215#define IXGBE_RXCSUM_PCSD 0x00002000
1216
1217
1218#define IXGBE_FCRTL_XONE 0x80000000
1219#define IXGBE_FCRTH_FCEN 0x80000000
1220
1221
1222#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF
1223
1224
1225#define IXGBE_RMCS_RRM 0x00000002
1226
1227#define IXGBE_RMCS_RAC 0x00000004
1228#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC
1229#define IXGBE_RMCS_TFCE_802_3X 0x00000008
1230#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010
1231#define IXGBE_RMCS_ARBDIS 0x00000040
1232
1233
1234#define IXGBE_FCCFG_TFCE_802_3X 0x00000008
1235#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010
1236
1237
1238
1239
1240#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF
1241#define IXGBE_EICR_FLOW_DIR 0x00010000
1242#define IXGBE_EICR_RX_MISS 0x00020000
1243#define IXGBE_EICR_PCI 0x00040000
1244#define IXGBE_EICR_MAILBOX 0x00080000
1245#define IXGBE_EICR_LSC 0x00100000
1246#define IXGBE_EICR_LINKSEC 0x00200000
1247#define IXGBE_EICR_MNG 0x00400000
1248#define IXGBE_EICR_GPI_SDP0 0x01000000
1249#define IXGBE_EICR_GPI_SDP1 0x02000000
1250#define IXGBE_EICR_GPI_SDP2 0x04000000
1251#define IXGBE_EICR_ECC 0x10000000
1252#define IXGBE_EICR_PBUR 0x10000000
1253#define IXGBE_EICR_DHER 0x20000000
1254#define IXGBE_EICR_TCP_TIMER 0x40000000
1255#define IXGBE_EICR_OTHER 0x80000000
1256
1257
1258#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE
1259#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR
1260#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS
1261#define IXGBE_EICS_PCI IXGBE_EICR_PCI
1262#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX
1263#define IXGBE_EICS_LSC IXGBE_EICR_LSC
1264#define IXGBE_EICS_MNG IXGBE_EICR_MNG
1265#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0
1266#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1
1267#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2
1268#define IXGBE_EICS_ECC IXGBE_EICR_ECC
1269#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR
1270#define IXGBE_EICS_DHER IXGBE_EICR_DHER
1271#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER
1272#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER
1273
1274
1275#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE
1276#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR
1277#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS
1278#define IXGBE_EIMS_PCI IXGBE_EICR_PCI
1279#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX
1280#define IXGBE_EIMS_LSC IXGBE_EICR_LSC
1281#define IXGBE_EIMS_MNG IXGBE_EICR_MNG
1282#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0
1283#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1
1284#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2
1285#define IXGBE_EIMS_ECC IXGBE_EICR_ECC
1286#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR
1287#define IXGBE_EIMS_DHER IXGBE_EICR_DHER
1288#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER
1289#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER
1290
1291
1292#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE
1293#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR
1294#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS
1295#define IXGBE_EIMC_PCI IXGBE_EICR_PCI
1296#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX
1297#define IXGBE_EIMC_LSC IXGBE_EICR_LSC
1298#define IXGBE_EIMC_MNG IXGBE_EICR_MNG
1299#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0
1300#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1
1301#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2
1302#define IXGBE_EIMC_ECC IXGBE_EICR_ECC
1303#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR
1304#define IXGBE_EIMC_DHER IXGBE_EICR_DHER
1305#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER
1306#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER
1307
1308#define IXGBE_EIMS_ENABLE_MASK ( \
1309 IXGBE_EIMS_RTX_QUEUE | \
1310 IXGBE_EIMS_LSC | \
1311 IXGBE_EIMS_TCP_TIMER | \
1312 IXGBE_EIMS_OTHER)
1313
1314
1315#define IXGBE_IMIR_PORT_IM_EN 0x00010000
1316#define IXGBE_IMIR_PORT_BP 0x00020000
1317#define IXGBE_IMIREXT_SIZE_BP 0x00001000
1318#define IXGBE_IMIREXT_CTRL_URG 0x00002000
1319#define IXGBE_IMIREXT_CTRL_ACK 0x00004000
1320#define IXGBE_IMIREXT_CTRL_PSH 0x00008000
1321#define IXGBE_IMIREXT_CTRL_RST 0x00010000
1322#define IXGBE_IMIREXT_CTRL_SYN 0x00020000
1323#define IXGBE_IMIREXT_CTRL_FIN 0x00040000
1324#define IXGBE_IMIREXT_CTRL_BP 0x00080000
1325#define IXGBE_IMIR_SIZE_BP_82599 0x00001000
1326#define IXGBE_IMIR_CTRL_URG_82599 0x00002000
1327#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000
1328#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000
1329#define IXGBE_IMIR_CTRL_RST_82599 0x00010000
1330#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000
1331#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000
1332#define IXGBE_IMIR_CTRL_BP_82599 0x00080000
1333#define IXGBE_IMIR_LLI_EN_82599 0x00100000
1334#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F
1335#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21
1336#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007
1337#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008
1338
1339#define IXGBE_MAX_FTQF_FILTERS 128
1340#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
1341#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
1342#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
1343#define IXGBE_FTQF_PROTOCOL_SCTP 2
1344#define IXGBE_FTQF_PRIORITY_MASK 0x00000007
1345#define IXGBE_FTQF_PRIORITY_SHIFT 2
1346#define IXGBE_FTQF_POOL_MASK 0x0000003F
1347#define IXGBE_FTQF_POOL_SHIFT 8
1348#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
1349#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
1350#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E
1351#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D
1352#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B
1353#define IXGBE_FTQF_DEST_PORT_MASK 0x17
1354#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F
1355#define IXGBE_FTQF_POOL_MASK_EN 0x40000000
1356#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
1357
1358
1359#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
1360
1361
1362#define IXGBE_IVAR_REG_NUM 25
1363#define IXGBE_IVAR_REG_NUM_82599 64
1364#define IXGBE_IVAR_TXRX_ENTRY 96
1365#define IXGBE_IVAR_RX_ENTRY 64
1366#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
1367#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
1368#define IXGBE_IVAR_TX_ENTRY 32
1369
1370#define IXGBE_IVAR_TCP_TIMER_INDEX 96
1371#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97
1372
1373#define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
1374
1375#define IXGBE_IVAR_ALLOC_VAL 0x80
1376
1377
1378#define IXGBE_MAX_ETQF_FILTERS 8
1379#define IXGBE_ETQF_FCOE 0x08000000
1380#define IXGBE_ETQF_BCN 0x10000000
1381#define IXGBE_ETQF_1588 0x40000000
1382#define IXGBE_ETQF_FILTER_EN 0x80000000
1383#define IXGBE_ETQF_POOL_ENABLE (1 << 26)
1384
1385#define IXGBE_ETQS_RX_QUEUE 0x007F0000
1386#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1387#define IXGBE_ETQS_LLI 0x20000000
1388#define IXGBE_ETQS_QUEUE_EN 0x80000000
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401#define IXGBE_ETQF_FILTER_EAPOL 0
1402#define IXGBE_ETQF_FILTER_FCOE 2
1403#define IXGBE_ETQF_FILTER_1588 3
1404#define IXGBE_ETQF_FILTER_FIP 4
1405
1406#define IXGBE_VLNCTRL_VET 0x0000FFFF
1407#define IXGBE_VLNCTRL_CFI 0x10000000
1408#define IXGBE_VLNCTRL_CFIEN 0x20000000
1409#define IXGBE_VLNCTRL_VFE 0x40000000
1410#define IXGBE_VLNCTRL_VME 0x80000000
1411
1412
1413#define IXGBE_VLVF_VIEN 0x80000000
1414#define IXGBE_VLVF_ENTRIES 64
1415#define IXGBE_VLVF_VLANID_MASK 0x00000FFF
1416
1417
1418#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000
1419#define IXGBE_VMVIR_VLANA_NEVER 0x80000000
1420
1421#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100
1422
1423
1424#define IXGBE_STATUS_LAN_ID 0x0000000C
1425#define IXGBE_STATUS_LAN_ID_SHIFT 2
1426#define IXGBE_STATUS_GIO 0x00080000
1427
1428#define IXGBE_STATUS_LAN_ID_0 0x00000000
1429#define IXGBE_STATUS_LAN_ID_1 0x00000004
1430
1431
1432#define IXGBE_ESDP_SDP0 0x00000001
1433#define IXGBE_ESDP_SDP1 0x00000002
1434#define IXGBE_ESDP_SDP2 0x00000004
1435#define IXGBE_ESDP_SDP3 0x00000008
1436#define IXGBE_ESDP_SDP4 0x00000010
1437#define IXGBE_ESDP_SDP5 0x00000020
1438#define IXGBE_ESDP_SDP6 0x00000040
1439#define IXGBE_ESDP_SDP4_DIR 0x00000004
1440#define IXGBE_ESDP_SDP5_DIR 0x00002000
1441
1442
1443#define IXGBE_LED_IVRT_BASE 0x00000040
1444#define IXGBE_LED_BLINK_BASE 0x00000080
1445#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1446#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1447#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
1448#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1449#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1450#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1451
1452
1453#define IXGBE_LED_LINK_UP 0x0
1454#define IXGBE_LED_LINK_10G 0x1
1455#define IXGBE_LED_MAC 0x2
1456#define IXGBE_LED_FILTER 0x3
1457#define IXGBE_LED_LINK_ACTIVE 0x4
1458#define IXGBE_LED_LINK_1G 0x5
1459#define IXGBE_LED_ON 0xE
1460#define IXGBE_LED_OFF 0xF
1461
1462
1463#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1464#define IXGBE_AUTOC_KX4_SUPP 0x80000000
1465#define IXGBE_AUTOC_KX_SUPP 0x40000000
1466#define IXGBE_AUTOC_PAUSE 0x30000000
1467#define IXGBE_AUTOC_ASM_PAUSE 0x20000000
1468#define IXGBE_AUTOC_SYM_PAUSE 0x10000000
1469#define IXGBE_AUTOC_RF 0x08000000
1470#define IXGBE_AUTOC_PD_TMR 0x06000000
1471#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1472#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1473#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1474#define IXGBE_AUTOC_FECA 0x00040000
1475#define IXGBE_AUTOC_FECR 0x00020000
1476#define IXGBE_AUTOC_KR_SUPP 0x00010000
1477#define IXGBE_AUTOC_AN_RESTART 0x00001000
1478#define IXGBE_AUTOC_FLU 0x00000001
1479#define IXGBE_AUTOC_LMS_SHIFT 13
1480#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1481#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1482#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1483#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1484#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1485#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1486#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1487#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1488#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1489#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1490#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1491#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1492
1493#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
1494#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
1495#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
1496#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
1497#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1498#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1499#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1500#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1501#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1502#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1503#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1504
1505#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1506#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1507#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1508#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1509#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1510#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1511
1512#define IXGBE_MACC_FLU 0x00000001
1513#define IXGBE_MACC_FSV_10G 0x00030000
1514#define IXGBE_MACC_FS 0x00040000
1515#define IXGBE_MAC_RX2TX_LPBK 0x00000002
1516
1517
1518#define IXGBE_LINKS_KX_AN_COMP 0x80000000
1519#define IXGBE_LINKS_UP 0x40000000
1520#define IXGBE_LINKS_SPEED 0x20000000
1521#define IXGBE_LINKS_MODE 0x18000000
1522#define IXGBE_LINKS_RX_MODE 0x06000000
1523#define IXGBE_LINKS_TX_MODE 0x01800000
1524#define IXGBE_LINKS_XGXS_EN 0x00400000
1525#define IXGBE_LINKS_SGMII_EN 0x02000000
1526#define IXGBE_LINKS_PCS_1G_EN 0x00200000
1527#define IXGBE_LINKS_1G_AN_EN 0x00100000
1528#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
1529#define IXGBE_LINKS_1G_SYNC 0x00040000
1530#define IXGBE_LINKS_10G_ALIGN 0x00020000
1531#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1532#define IXGBE_LINKS_TL_FAULT 0x00001000
1533#define IXGBE_LINKS_SIGNAL 0x00000F00
1534
1535#define IXGBE_LINKS_SPEED_82599 0x30000000
1536#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1537#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
1538#define IXGBE_LINKS_SPEED_100_82599 0x10000000
1539#define IXGBE_LINK_UP_TIME 90
1540#define IXGBE_AUTO_NEG_TIME 45
1541
1542#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
1543
1544
1545#define IXGBE_PCS1GLSTA_LINK_OK 1
1546#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
1547#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
1548#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
1549#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
1550#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1551#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
1552
1553#define IXGBE_PCS1GANA_SYM_PAUSE 0x80
1554#define IXGBE_PCS1GANA_ASM_PAUSE 0x100
1555
1556
1557#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000
1558#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
1559#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
1560#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
1561#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
1562#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
1563
1564
1565#define IXGBE_ANLP1_PAUSE 0x0C00
1566#define IXGBE_ANLP1_SYM_PAUSE 0x0400
1567#define IXGBE_ANLP1_ASM_PAUSE 0x0800
1568#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
1569
1570
1571#define IXGBE_SWSM_SMBI 0x00000001
1572#define IXGBE_SWSM_SWESMBI 0x00000002
1573#define IXGBE_SWSM_WMNG 0x00000004
1574#define IXGBE_SWFW_REGSMP 0x80000000
1575
1576
1577#define IXGBE_GSSR_EEP_SM 0x0001
1578#define IXGBE_GSSR_PHY0_SM 0x0002
1579#define IXGBE_GSSR_PHY1_SM 0x0004
1580#define IXGBE_GSSR_MAC_CSR_SM 0x0008
1581#define IXGBE_GSSR_FLASH_SM 0x0010
1582#define IXGBE_GSSR_SW_MNG_SM 0x0400
1583
1584
1585#define IXGBE_FWSTS_FWRI 0x00000200
1586
1587
1588#define IXGBE_EEC_SK 0x00000001
1589#define IXGBE_EEC_CS 0x00000002
1590#define IXGBE_EEC_DI 0x00000004
1591#define IXGBE_EEC_DO 0x00000008
1592#define IXGBE_EEC_FWE_MASK 0x00000030
1593#define IXGBE_EEC_FWE_DIS 0x00000010
1594#define IXGBE_EEC_FWE_EN 0x00000020
1595#define IXGBE_EEC_FWE_SHIFT 4
1596#define IXGBE_EEC_REQ 0x00000040
1597#define IXGBE_EEC_GNT 0x00000080
1598#define IXGBE_EEC_PRES 0x00000100
1599#define IXGBE_EEC_ARD 0x00000200
1600#define IXGBE_EEC_FLUP 0x00800000
1601#define IXGBE_EEC_SEC1VAL 0x02000000
1602#define IXGBE_EEC_FLUDONE 0x04000000
1603
1604#define IXGBE_EEC_ADDR_SIZE 0x00000400
1605#define IXGBE_EEC_SIZE 0x00007800
1606#define IXGBE_EERD_MAX_ADDR 0x00003FFF
1607
1608#define IXGBE_EEC_SIZE_SHIFT 11
1609#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
1610#define IXGBE_EEPROM_OPCODE_BITS 8
1611
1612
1613#define IXGBE_PBANUM_LENGTH 11
1614
1615
1616#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
1617#define IXGBE_EEPROM_CHECKSUM 0x3F
1618#define IXGBE_EEPROM_SUM 0xBABA
1619#define IXGBE_PCIE_ANALOG_PTR 0x03
1620#define IXGBE_ATLAS0_CONFIG_PTR 0x04
1621#define IXGBE_PHY_PTR 0x04
1622#define IXGBE_ATLAS1_CONFIG_PTR 0x05
1623#define IXGBE_OPTION_ROM_PTR 0x05
1624#define IXGBE_PCIE_GENERAL_PTR 0x06
1625#define IXGBE_PCIE_CONFIG0_PTR 0x07
1626#define IXGBE_PCIE_CONFIG1_PTR 0x08
1627#define IXGBE_CORE0_PTR 0x09
1628#define IXGBE_CORE1_PTR 0x0A
1629#define IXGBE_MAC0_PTR 0x0B
1630#define IXGBE_MAC1_PTR 0x0C
1631#define IXGBE_CSR0_CONFIG_PTR 0x0D
1632#define IXGBE_CSR1_CONFIG_PTR 0x0E
1633#define IXGBE_FW_PTR 0x0F
1634#define IXGBE_PBANUM0_PTR 0x15
1635#define IXGBE_PBANUM1_PTR 0x16
1636#define IXGBE_FREE_SPACE_PTR 0X3E
1637#define IXGBE_SAN_MAC_ADDR_PTR 0x28
1638#define IXGBE_DEVICE_CAPS 0x2C
1639#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
1640#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
1641#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
1642
1643
1644#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
1645
1646
1647#define IXGBE_ISCSI_BOOT_CAPS 0x0033
1648#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
1649#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
1650
1651
1652#define IXGBE_EEPROM_MAX_RETRY_SPI 5000
1653#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
1654#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03
1655#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02
1656#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08
1657#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06
1658
1659#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
1660#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05
1661#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01
1662#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20
1663#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8
1664#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB
1665
1666
1667#define IXGBE_EEPROM_RW_REG_DATA 16
1668#define IXGBE_EEPROM_RW_REG_DONE 2
1669#define IXGBE_EEPROM_RW_REG_START 1
1670#define IXGBE_EEPROM_RW_ADDR_SHIFT 2
1671#define IXGBE_NVM_POLL_WRITE 1
1672#define IXGBE_NVM_POLL_READ 0
1673
1674#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
1675
1676#define IXGBE_EEPROM_PAGE_SIZE_MAX 128
1677#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512
1678#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256
1679
1680#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1681#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000
1682#endif
1683
1684#ifndef IXGBE_EERD_EEWR_ATTEMPTS
1685
1686
1687#define IXGBE_EERD_EEWR_ATTEMPTS 100000
1688#endif
1689
1690#ifndef IXGBE_FLUDONE_ATTEMPTS
1691
1692#define IXGBE_FLUDONE_ATTEMPTS 20000
1693#endif
1694
1695#define IXGBE_PCIE_CTRL2 0x5
1696#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8
1697#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2
1698#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1
1699
1700#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
1701#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
1702#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
1703#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
1704#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
1705#define IXGBE_FW_LESM_STATE_1 0x1
1706#define IXGBE_FW_LESM_STATE_ENABLED 0x8000
1707#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
1708#define IXGBE_FW_PATCH_VERSION_4 0x7
1709#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33
1710#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20
1711#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17
1712#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0
1713#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1
1714#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27
1715#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0
1716#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1
1717#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4
1718#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7
1719#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8
1720#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0
1721#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1
1722
1723
1724#define IXGBE_PCI_DEVICE_STATUS 0xAA
1725#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
1726#define IXGBE_PCI_LINK_STATUS 0xB2
1727#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
1728#define IXGBE_PCI_LINK_WIDTH 0x3F0
1729#define IXGBE_PCI_LINK_WIDTH_1 0x10
1730#define IXGBE_PCI_LINK_WIDTH_2 0x20
1731#define IXGBE_PCI_LINK_WIDTH_4 0x40
1732#define IXGBE_PCI_LINK_WIDTH_8 0x80
1733#define IXGBE_PCI_LINK_SPEED 0xF
1734#define IXGBE_PCI_LINK_SPEED_2500 0x1
1735#define IXGBE_PCI_LINK_SPEED_5000 0x2
1736#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
1737#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
1738#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
1739
1740
1741#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
1742
1743
1744#define IXGBE_IS_MULTICAST(Address) \
1745 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
1746
1747
1748#define IXGBE_IS_BROADCAST(Address) \
1749 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
1750 (((u8 *)(Address))[1] == ((u8)0xff)))
1751
1752
1753#define IXGBE_RAH_VIND_MASK 0x003C0000
1754#define IXGBE_RAH_VIND_SHIFT 18
1755#define IXGBE_RAH_AV 0x80000000
1756#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
1757
1758
1759#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
1760#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
1761#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
1762#define IXGBE_RFCTL_NFSW_DIS 0x00000040
1763#define IXGBE_RFCTL_NFSR_DIS 0x00000080
1764#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
1765#define IXGBE_RFCTL_NFS_VER_SHIFT 8
1766#define IXGBE_RFCTL_NFS_VER_2 0
1767#define IXGBE_RFCTL_NFS_VER_3 1
1768#define IXGBE_RFCTL_NFS_VER_4 2
1769#define IXGBE_RFCTL_IPV6_DIS 0x00000400
1770#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
1771#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
1772#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
1773#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1774
1775
1776#define IXGBE_TXDCTL_ENABLE 0x02000000
1777#define IXGBE_TXDCTL_SWFLSH 0x04000000
1778#define IXGBE_TXDCTL_WTHRESH_SHIFT 16
1779
1780#define IXGBE_TX_PAD_ENABLE 0x00000400
1781#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004
1782
1783#define IXGBE_MAX_FRAME_SZ 0x40040000
1784
1785#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1
1786#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2
1787
1788
1789#define IXGBE_RXCTRL_RXEN 0x00000001
1790#define IXGBE_RXCTRL_DMBYPS 0x00000002
1791#define IXGBE_RXDCTL_ENABLE 0x02000000
1792#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF
1793#define IXGBE_RXDCTL_RLPML_EN 0x00008000
1794#define IXGBE_RXDCTL_VME 0x40000000
1795
1796#define IXGBE_FCTRL_SBP 0x00000002
1797#define IXGBE_FCTRL_MPE 0x00000100
1798#define IXGBE_FCTRL_UPE 0x00000200
1799#define IXGBE_FCTRL_BAM 0x00000400
1800#define IXGBE_FCTRL_PMCF 0x00001000
1801#define IXGBE_FCTRL_DPF 0x00002000
1802
1803#define IXGBE_FCTRL_RPFCE 0x00004000
1804#define IXGBE_FCTRL_RFCE 0x00008000
1805#define IXGBE_MFLCN_PMCF 0x00000001
1806#define IXGBE_MFLCN_DPF 0x00000002
1807#define IXGBE_MFLCN_RPFCE 0x00000004
1808#define IXGBE_MFLCN_RFCE 0x00000008
1809
1810#define IXGBE_MFLCN_RPFCE_SHIFT 4
1811
1812
1813#define IXGBE_MRQC_RSSEN 0x00000001
1814#define IXGBE_MRQC_MRQE_MASK 0xF
1815#define IXGBE_MRQC_RT8TCEN 0x00000002
1816#define IXGBE_MRQC_RT4TCEN 0x00000003
1817#define IXGBE_MRQC_RTRSS8TCEN 0x00000004
1818#define IXGBE_MRQC_RTRSS4TCEN 0x00000005
1819#define IXGBE_MRQC_VMDQEN 0x00000008
1820#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A
1821#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B
1822#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C
1823#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D
1824#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
1825#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1826#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
1827#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
1828#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1829#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
1830#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1831#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
1832#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
1833#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
1834#define IXGBE_MRQC_L3L4TXSWEN 0x00008000
1835
1836
1837#define IXGBE_QDE_ENABLE 0x00000001
1838#define IXGBE_QDE_IDX_MASK 0x00007F00
1839#define IXGBE_QDE_IDX_SHIFT 8
1840
1841#define IXGBE_TXD_POPTS_IXSM 0x01
1842#define IXGBE_TXD_POPTS_TXSM 0x02
1843#define IXGBE_TXD_CMD_EOP 0x01000000
1844#define IXGBE_TXD_CMD_IFCS 0x02000000
1845#define IXGBE_TXD_CMD_IC 0x04000000
1846#define IXGBE_TXD_CMD_RS 0x08000000
1847#define IXGBE_TXD_CMD_DEXT 0x20000000
1848#define IXGBE_TXD_CMD_VLE 0x40000000
1849#define IXGBE_TXD_STAT_DD 0x00000001
1850
1851#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
1852#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
1853#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
1854#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
1855#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
1856
1857#define IXGBE_MTQC_RT_ENA 0x1
1858#define IXGBE_MTQC_VT_ENA 0x2
1859#define IXGBE_MTQC_64Q_1PB 0x0
1860#define IXGBE_MTQC_32VF 0x8
1861#define IXGBE_MTQC_64VF 0x4
1862#define IXGBE_MTQC_8TC_8TQ 0xC
1863
1864
1865#define IXGBE_RXD_STAT_DD 0x01
1866#define IXGBE_RXD_STAT_EOP 0x02
1867#define IXGBE_RXD_STAT_FLM 0x04
1868#define IXGBE_RXD_STAT_VP 0x08
1869#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0
1870#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
1871#define IXGBE_RXD_STAT_UDPCS 0x10
1872#define IXGBE_RXD_STAT_L4CS 0x20
1873#define IXGBE_RXD_STAT_IPCS 0x40
1874#define IXGBE_RXD_STAT_PIF 0x80
1875#define IXGBE_RXD_STAT_CRCV 0x100
1876#define IXGBE_RXD_STAT_VEXT 0x200
1877#define IXGBE_RXD_STAT_UDPV 0x400
1878#define IXGBE_RXD_STAT_DYNINT 0x800
1879#define IXGBE_RXD_STAT_LLINT 0x800
1880#define IXGBE_RXD_STAT_TS 0x10000
1881#define IXGBE_RXD_STAT_SECP 0x20000
1882#define IXGBE_RXD_STAT_LB 0x40000
1883#define IXGBE_RXD_STAT_ACK 0x8000
1884#define IXGBE_RXD_ERR_CE 0x01
1885#define IXGBE_RXD_ERR_LE 0x02
1886#define IXGBE_RXD_ERR_PE 0x08
1887#define IXGBE_RXD_ERR_OSE 0x10
1888#define IXGBE_RXD_ERR_USE 0x20
1889#define IXGBE_RXD_ERR_TCPE 0x40
1890#define IXGBE_RXD_ERR_IPE 0x80
1891#define IXGBE_RXDADV_ERR_MASK 0xfff00000
1892#define IXGBE_RXDADV_ERR_SHIFT 20
1893#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000
1894#define IXGBE_RXDADV_ERR_FCERR 0x00700000
1895#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000
1896#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000
1897#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000
1898#define IXGBE_RXDADV_ERR_HBO 0x00800000
1899#define IXGBE_RXDADV_ERR_CE 0x01000000
1900#define IXGBE_RXDADV_ERR_LE 0x02000000
1901#define IXGBE_RXDADV_ERR_PE 0x08000000
1902#define IXGBE_RXDADV_ERR_OSE 0x10000000
1903#define IXGBE_RXDADV_ERR_USE 0x20000000
1904#define IXGBE_RXDADV_ERR_TCPE 0x40000000
1905#define IXGBE_RXDADV_ERR_IPE 0x80000000
1906#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF
1907#define IXGBE_RXD_PRI_MASK 0xE000
1908#define IXGBE_RXD_PRI_SHIFT 13
1909#define IXGBE_RXD_CFI_MASK 0x1000
1910#define IXGBE_RXD_CFI_SHIFT 12
1911
1912#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD
1913#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP
1914#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM
1915#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP
1916#define IXGBE_RXDADV_STAT_MASK 0x000fffff
1917#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040
1918#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030
1919#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000
1920#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010
1921#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020
1922#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030
1923
1924
1925#define IXGBE_PSRTYPE_TCPHDR 0x00000010
1926#define IXGBE_PSRTYPE_UDPHDR 0x00000020
1927#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
1928#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
1929#define IXGBE_PSRTYPE_L2HDR 0x00001000
1930
1931
1932#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10
1933#define IXGBE_SRRCTL_RDMTS_SHIFT 22
1934#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
1935#define IXGBE_SRRCTL_DROP_EN 0x10000000
1936#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
1937#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
1938#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
1939#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
1940#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
1941#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
1942#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
1943#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
1944
1945#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
1946#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
1947
1948#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
1949#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
1950#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
1951#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
1952#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
1953#define IXGBE_RXDADV_RSCCNT_SHIFT 17
1954#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
1955#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
1956#define IXGBE_RXDADV_SPH 0x8000
1957
1958
1959#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
1960#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
1961#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
1962#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
1963#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
1964#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
1965#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
1966#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
1967#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
1968#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
1969
1970
1971#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
1972#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010
1973#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020
1974#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040
1975#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080
1976#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100
1977#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200
1978#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400
1979#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800
1980#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000
1981#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000
1982#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000
1983#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000
1984#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070
1985#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4
1986
1987
1988#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
1989#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
1990#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
1991#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
1992#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
1993
1994
1995#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
1996 IXGBE_RXD_ERR_CE | \
1997 IXGBE_RXD_ERR_LE | \
1998 IXGBE_RXD_ERR_PE | \
1999 IXGBE_RXD_ERR_OSE | \
2000 IXGBE_RXD_ERR_USE)
2001
2002#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2003 IXGBE_RXDADV_ERR_CE | \
2004 IXGBE_RXDADV_ERR_LE | \
2005 IXGBE_RXDADV_ERR_PE | \
2006 IXGBE_RXDADV_ERR_OSE | \
2007 IXGBE_RXDADV_ERR_USE)
2008
2009
2010#define IXGBE_MCSTCTRL_MFE 0x4
2011
2012
2013#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
2014#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
2015#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
2016
2017
2018#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF
2019#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000
2020#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D
2021#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2022
2023
2024#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
2025#define IXGBE_MBVFICR(_i) (0x00710 + (_i * 4))
2026#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
2027#define IXGBE_VFLREC(_i) (0x00700 + (_i * 4))
2028
2029enum ixgbe_fdir_pballoc_type {
2030 IXGBE_FDIR_PBALLOC_64K = 0,
2031 IXGBE_FDIR_PBALLOC_128K,
2032 IXGBE_FDIR_PBALLOC_256K,
2033};
2034#define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16
2035
2036
2037#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
2038#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
2039#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
2040#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
2041#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
2042#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
2043#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
2044#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
2045#define IXGBE_FDIRCTRL_FLEX_SHIFT 16
2046#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
2047#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
2048#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
2049#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
2050
2051#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
2052#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
2053#define IXGBE_FDIRIP6M_DIPM_SHIFT 16
2054#define IXGBE_FDIRM_VLANID 0x00000001
2055#define IXGBE_FDIRM_VLANP 0x00000002
2056#define IXGBE_FDIRM_POOL 0x00000004
2057#define IXGBE_FDIRM_L4P 0x00000008
2058#define IXGBE_FDIRM_FLEX 0x00000010
2059#define IXGBE_FDIRM_DIPv6 0x00000020
2060
2061#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
2062#define IXGBE_FDIRFREE_FREE_SHIFT 0
2063#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
2064#define IXGBE_FDIRFREE_COLL_SHIFT 16
2065#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
2066#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
2067#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
2068#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
2069#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
2070#define IXGBE_FDIRUSTAT_ADD_SHIFT 0
2071#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
2072#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
2073#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
2074#define IXGBE_FDIRFSTAT_FADD_SHIFT 0
2075#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
2076#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
2077#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
2078#define IXGBE_FDIRVLAN_FLEX_SHIFT 16
2079#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
2080#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
2081
2082#define IXGBE_FDIRCMD_CMD_MASK 0x00000003
2083#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
2084#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
2085#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
2086#define IXGBE_FDIRCMD_CMD_QUERY_REM_HASH 0x00000007
2087#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
2088#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
2089#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
2090#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
2091#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
2092#define IXGBE_FDIRCMD_IPV6 0x00000080
2093#define IXGBE_FDIRCMD_CLEARHT 0x00000100
2094#define IXGBE_FDIRCMD_DROP 0x00000200
2095#define IXGBE_FDIRCMD_INT 0x00000400
2096#define IXGBE_FDIRCMD_LAST 0x00000800
2097#define IXGBE_FDIRCMD_COLLISION 0x00001000
2098#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
2099#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
2100#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
2101#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
2102#define IXGBE_FDIR_INIT_DONE_POLL 10
2103#define IXGBE_FDIRCMD_CMD_POLL 10
2104
2105
2106union ixgbe_adv_tx_desc {
2107 struct {
2108 __le64 buffer_addr;
2109 __le32 cmd_type_len;
2110 __le32 olinfo_status;
2111 } read;
2112 struct {
2113 __le64 rsvd;
2114 __le32 nxtseq_seed;
2115 __le32 status;
2116 } wb;
2117};
2118
2119
2120union ixgbe_adv_rx_desc {
2121 struct {
2122 __le64 pkt_addr;
2123 __le64 hdr_addr;
2124 } read;
2125 struct {
2126 struct {
2127 union {
2128 __le32 data;
2129 struct {
2130 __le16 pkt_info;
2131 __le16 hdr_info;
2132 } hs_rss;
2133 } lo_dword;
2134 union {
2135 __le32 rss;
2136 struct {
2137 __le16 ip_id;
2138 __le16 csum;
2139 } csum_ip;
2140 } hi_dword;
2141 } lower;
2142 struct {
2143 __le32 status_error;
2144 __le16 length;
2145 __le16 vlan;
2146 } upper;
2147 } wb;
2148};
2149
2150
2151struct ixgbe_adv_tx_context_desc {
2152 __le32 vlan_macip_lens;
2153 __le32 seqnum_seed;
2154 __le32 type_tucmd_mlhl;
2155 __le32 mss_l4len_idx;
2156};
2157
2158
2159#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF
2160#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000
2161#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF
2162#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF
2163#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000
2164#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000
2165#define IXGBE_ADVTXD_DTYP_DATA 0x00300000
2166#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP
2167#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS
2168#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS
2169#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000
2170#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT
2171#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE
2172#define IXGBE_ADVTXD_DCMD_TSE 0x80000000
2173#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD
2174#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002
2175#define IXGBE_ADVTXD_STAT_RSV 0x0000000C
2176#define IXGBE_ADVTXD_IDX_SHIFT 4
2177#define IXGBE_ADVTXD_CC 0x00000080
2178#define IXGBE_ADVTXD_POPTS_SHIFT 8
2179#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
2180 IXGBE_ADVTXD_POPTS_SHIFT)
2181#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
2182 IXGBE_ADVTXD_POPTS_SHIFT)
2183#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000
2184#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800
2185#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000
2186#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800
2187#define IXGBE_ADVTXD_POPTS_RSV 0x00002000
2188#define IXGBE_ADVTXD_PAYLEN_SHIFT 14
2189#define IXGBE_ADVTXD_MACLEN_SHIFT 9
2190#define IXGBE_ADVTXD_VLAN_SHIFT 16
2191#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400
2192#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000
2193#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000
2194#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800
2195#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000
2196#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000
2197#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400
2198#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000
2199#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000
2200#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000
2201#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10)
2202#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10)
2203#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10)
2204#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10)
2205#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10)
2206#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10)
2207#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10)
2208#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10)
2209#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10)
2210#define IXGBE_ADVTXD_L4LEN_SHIFT 8
2211#define IXGBE_ADVTXD_MSS_SHIFT 16
2212
2213
2214typedef u32 ixgbe_autoneg_advertised;
2215
2216typedef u32 ixgbe_link_speed;
2217#define IXGBE_LINK_SPEED_UNKNOWN 0
2218#define IXGBE_LINK_SPEED_100_FULL 0x0008
2219#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
2220#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
2221#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
2222 IXGBE_LINK_SPEED_10GB_FULL)
2223#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
2224 IXGBE_LINK_SPEED_1GB_FULL | \
2225 IXGBE_LINK_SPEED_10GB_FULL)
2226
2227
2228
2229typedef u32 ixgbe_physical_layer;
2230#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
2231#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
2232#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
2233#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
2234#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
2235#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
2236#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
2237#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
2238#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
2239#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
2240#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
2241#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
2242#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
2243#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
2244#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
2245
2246
2247#define PAUSE_RTT 8
2248#define PAUSE_MTU(MTU) ((MTU + 1024 - 1) / 1024)
2249
2250#define FC_HIGH_WATER(MTU) ((((PAUSE_RTT + PAUSE_MTU(MTU)) * 144) + 99) / 100 +\
2251 PAUSE_MTU(MTU))
2252#define FC_LOW_WATER(MTU) (2 * (2 * PAUSE_MTU(MTU) + PAUSE_RTT))
2253
2254
2255#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
2256#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
2257
2258
2259#define IXGBE_ATR_HASH_MASK 0x7fff
2260#define IXGBE_ATR_L4TYPE_MASK 0x3
2261#define IXGBE_ATR_L4TYPE_UDP 0x1
2262#define IXGBE_ATR_L4TYPE_TCP 0x2
2263#define IXGBE_ATR_L4TYPE_SCTP 0x3
2264#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
2265enum ixgbe_atr_flow_type {
2266 IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
2267 IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
2268 IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
2269 IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
2270 IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
2271 IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
2272 IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
2273 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
2274};
2275
2276
2277union ixgbe_atr_input {
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291 struct {
2292 u8 vm_pool;
2293 u8 flow_type;
2294 __be16 vlan_id;
2295 __be32 dst_ip[4];
2296 __be32 src_ip[4];
2297 __be16 src_port;
2298 __be16 dst_port;
2299 __be16 flex_bytes;
2300 __be16 rsvd0;
2301 } formatted;
2302 __be32 dword_stream[11];
2303};
2304
2305
2306union ixgbe_atr_hash_dword {
2307 struct {
2308 u8 vm_pool;
2309 u8 flow_type;
2310 __be16 vlan_id;
2311 } formatted;
2312 __be32 ip;
2313 struct {
2314 __be16 src;
2315 __be16 dst;
2316 } port;
2317 __be16 flex_bytes;
2318 __be32 dword;
2319};
2320
2321struct ixgbe_atr_input_masks {
2322 __be16 rsvd0;
2323 __be16 vlan_id_mask;
2324 __be32 dst_ip_mask[4];
2325 __be32 src_ip_mask[4];
2326 __be16 src_port_mask;
2327 __be16 dst_port_mask;
2328 __be16 flex_mask;
2329};
2330
2331enum ixgbe_eeprom_type {
2332 ixgbe_eeprom_uninitialized = 0,
2333 ixgbe_eeprom_spi,
2334 ixgbe_flash,
2335 ixgbe_eeprom_none
2336};
2337
2338enum ixgbe_mac_type {
2339 ixgbe_mac_unknown = 0,
2340 ixgbe_mac_82598EB,
2341 ixgbe_mac_82599EB,
2342 ixgbe_mac_X540,
2343 ixgbe_num_macs
2344};
2345
2346enum ixgbe_phy_type {
2347 ixgbe_phy_unknown = 0,
2348 ixgbe_phy_none,
2349 ixgbe_phy_tn,
2350 ixgbe_phy_aq,
2351 ixgbe_phy_cu_unknown,
2352 ixgbe_phy_qt,
2353 ixgbe_phy_xaui,
2354 ixgbe_phy_nl,
2355 ixgbe_phy_sfp_passive_tyco,
2356 ixgbe_phy_sfp_passive_unknown,
2357 ixgbe_phy_sfp_active_unknown,
2358 ixgbe_phy_sfp_avago,
2359 ixgbe_phy_sfp_ftl,
2360 ixgbe_phy_sfp_ftl_active,
2361 ixgbe_phy_sfp_unknown,
2362 ixgbe_phy_sfp_intel,
2363 ixgbe_phy_sfp_unsupported,
2364 ixgbe_phy_generic
2365};
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380enum ixgbe_sfp_type {
2381 ixgbe_sfp_type_da_cu = 0,
2382 ixgbe_sfp_type_sr = 1,
2383 ixgbe_sfp_type_lr = 2,
2384 ixgbe_sfp_type_da_cu_core0 = 3,
2385 ixgbe_sfp_type_da_cu_core1 = 4,
2386 ixgbe_sfp_type_srlr_core0 = 5,
2387 ixgbe_sfp_type_srlr_core1 = 6,
2388 ixgbe_sfp_type_da_act_lmt_core0 = 7,
2389 ixgbe_sfp_type_da_act_lmt_core1 = 8,
2390 ixgbe_sfp_type_1g_cu_core0 = 9,
2391 ixgbe_sfp_type_1g_cu_core1 = 10,
2392 ixgbe_sfp_type_not_present = 0xFFFE,
2393 ixgbe_sfp_type_unknown = 0xFFFF
2394};
2395
2396enum ixgbe_media_type {
2397 ixgbe_media_type_unknown = 0,
2398 ixgbe_media_type_fiber,
2399 ixgbe_media_type_fiber_lco,
2400 ixgbe_media_type_copper,
2401 ixgbe_media_type_backplane,
2402 ixgbe_media_type_cx4,
2403 ixgbe_media_type_virtual
2404};
2405
2406
2407enum ixgbe_fc_mode {
2408 ixgbe_fc_none = 0,
2409 ixgbe_fc_rx_pause,
2410 ixgbe_fc_tx_pause,
2411 ixgbe_fc_full,
2412#ifdef CONFIG_DCB
2413 ixgbe_fc_pfc,
2414#endif
2415 ixgbe_fc_default
2416};
2417
2418
2419#define IXGBE_SMARTSPEED_MAX_RETRIES 3
2420enum ixgbe_smart_speed {
2421 ixgbe_smart_speed_auto = 0,
2422 ixgbe_smart_speed_on,
2423 ixgbe_smart_speed_off
2424};
2425
2426
2427enum ixgbe_bus_type {
2428 ixgbe_bus_type_unknown = 0,
2429 ixgbe_bus_type_pci,
2430 ixgbe_bus_type_pcix,
2431 ixgbe_bus_type_pci_express,
2432 ixgbe_bus_type_reserved
2433};
2434
2435
2436enum ixgbe_bus_speed {
2437 ixgbe_bus_speed_unknown = 0,
2438 ixgbe_bus_speed_33 = 33,
2439 ixgbe_bus_speed_66 = 66,
2440 ixgbe_bus_speed_100 = 100,
2441 ixgbe_bus_speed_120 = 120,
2442 ixgbe_bus_speed_133 = 133,
2443 ixgbe_bus_speed_2500 = 2500,
2444 ixgbe_bus_speed_5000 = 5000,
2445 ixgbe_bus_speed_reserved
2446};
2447
2448
2449enum ixgbe_bus_width {
2450 ixgbe_bus_width_unknown = 0,
2451 ixgbe_bus_width_pcie_x1 = 1,
2452 ixgbe_bus_width_pcie_x2 = 2,
2453 ixgbe_bus_width_pcie_x4 = 4,
2454 ixgbe_bus_width_pcie_x8 = 8,
2455 ixgbe_bus_width_32 = 32,
2456 ixgbe_bus_width_64 = 64,
2457 ixgbe_bus_width_reserved
2458};
2459
2460struct ixgbe_addr_filter_info {
2461 u32 num_mc_addrs;
2462 u32 rar_used_count;
2463 u32 mta_in_use;
2464 u32 overflow_promisc;
2465 bool uc_set_promisc;
2466 bool user_set_promisc;
2467};
2468
2469
2470struct ixgbe_bus_info {
2471 enum ixgbe_bus_speed speed;
2472 enum ixgbe_bus_width width;
2473 enum ixgbe_bus_type type;
2474
2475 u16 func;
2476 u16 lan_id;
2477};
2478
2479
2480struct ixgbe_fc_info {
2481 u32 high_water;
2482 u32 low_water;
2483 u16 pause_time;
2484 bool send_xon;
2485 bool strict_ieee;
2486 bool disable_fc_autoneg;
2487 bool fc_was_autonegged;
2488 enum ixgbe_fc_mode current_mode;
2489 enum ixgbe_fc_mode requested_mode;
2490};
2491
2492
2493struct ixgbe_hw_stats {
2494 u64 crcerrs;
2495 u64 illerrc;
2496 u64 errbc;
2497 u64 mspdc;
2498 u64 mpctotal;
2499 u64 mpc[8];
2500 u64 mlfc;
2501 u64 mrfc;
2502 u64 rlec;
2503 u64 lxontxc;
2504 u64 lxonrxc;
2505 u64 lxofftxc;
2506 u64 lxoffrxc;
2507 u64 pxontxc[8];
2508 u64 pxonrxc[8];
2509 u64 pxofftxc[8];
2510 u64 pxoffrxc[8];
2511 u64 prc64;
2512 u64 prc127;
2513 u64 prc255;
2514 u64 prc511;
2515 u64 prc1023;
2516 u64 prc1522;
2517 u64 gprc;
2518 u64 bprc;
2519 u64 mprc;
2520 u64 gptc;
2521 u64 gorc;
2522 u64 gotc;
2523 u64 rnbc[8];
2524 u64 ruc;
2525 u64 rfc;
2526 u64 roc;
2527 u64 rjc;
2528 u64 mngprc;
2529 u64 mngpdc;
2530 u64 mngptc;
2531 u64 tor;
2532 u64 tpr;
2533 u64 tpt;
2534 u64 ptc64;
2535 u64 ptc127;
2536 u64 ptc255;
2537 u64 ptc511;
2538 u64 ptc1023;
2539 u64 ptc1522;
2540 u64 mptc;
2541 u64 bptc;
2542 u64 xec;
2543 u64 rqsmr[16];
2544 u64 tqsmr[8];
2545 u64 qprc[16];
2546 u64 qptc[16];
2547 u64 qbrc[16];
2548 u64 qbtc[16];
2549 u64 qprdc[16];
2550 u64 pxon2offc[8];
2551 u64 fdirustat_add;
2552 u64 fdirustat_remove;
2553 u64 fdirfstat_fadd;
2554 u64 fdirfstat_fremove;
2555 u64 fdirmatch;
2556 u64 fdirmiss;
2557 u64 fccrc;
2558 u64 fcoerpdc;
2559 u64 fcoeprc;
2560 u64 fcoeptc;
2561 u64 fcoedwrc;
2562 u64 fcoedwtc;
2563 u64 b2ospc;
2564 u64 b2ogprc;
2565 u64 o2bgptc;
2566 u64 o2bspc;
2567};
2568
2569
2570struct ixgbe_hw;
2571
2572
2573typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
2574 u32 *vmdq);
2575
2576
2577struct ixgbe_eeprom_operations {
2578 s32 (*init_params)(struct ixgbe_hw *);
2579 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
2580 s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2581 s32 (*write)(struct ixgbe_hw *, u16, u16);
2582 s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2583 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
2584 s32 (*update_checksum)(struct ixgbe_hw *);
2585 u16 (*calc_checksum)(struct ixgbe_hw *);
2586};
2587
2588struct ixgbe_mac_operations {
2589 s32 (*init_hw)(struct ixgbe_hw *);
2590 s32 (*reset_hw)(struct ixgbe_hw *);
2591 s32 (*start_hw)(struct ixgbe_hw *);
2592 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
2593 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
2594 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
2595 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
2596 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
2597 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
2598 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
2599 s32 (*stop_adapter)(struct ixgbe_hw *);
2600 s32 (*get_bus_info)(struct ixgbe_hw *);
2601 void (*set_lan_id)(struct ixgbe_hw *);
2602 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
2603 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
2604 s32 (*setup_sfp)(struct ixgbe_hw *);
2605 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
2606 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
2607 void (*release_swfw_sync)(struct ixgbe_hw *, u16);
2608
2609
2610 void (*disable_tx_laser)(struct ixgbe_hw *);
2611 void (*enable_tx_laser)(struct ixgbe_hw *);
2612 void (*flap_tx_laser)(struct ixgbe_hw *);
2613 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
2614 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2615 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2616 bool *);
2617
2618
2619 s32 (*led_on)(struct ixgbe_hw *, u32);
2620 s32 (*led_off)(struct ixgbe_hw *, u32);
2621 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
2622 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
2623
2624
2625 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
2626 s32 (*clear_rar)(struct ixgbe_hw *, u32);
2627 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
2628 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
2629 s32 (*init_rx_addrs)(struct ixgbe_hw *);
2630 s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
2631 s32 (*enable_mc)(struct ixgbe_hw *);
2632 s32 (*disable_mc)(struct ixgbe_hw *);
2633 s32 (*clear_vfta)(struct ixgbe_hw *);
2634 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
2635 s32 (*init_uta_tables)(struct ixgbe_hw *);
2636 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
2637 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
2638
2639
2640 s32 (*fc_enable)(struct ixgbe_hw *, s32);
2641};
2642
2643struct ixgbe_phy_operations {
2644 s32 (*identify)(struct ixgbe_hw *);
2645 s32 (*identify_sfp)(struct ixgbe_hw *);
2646 s32 (*init)(struct ixgbe_hw *);
2647 s32 (*reset)(struct ixgbe_hw *);
2648 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
2649 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
2650 s32 (*setup_link)(struct ixgbe_hw *);
2651 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
2652 bool);
2653 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
2654 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
2655 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
2656 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
2657 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
2658 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
2659 s32 (*check_overtemp)(struct ixgbe_hw *);
2660};
2661
2662struct ixgbe_eeprom_info {
2663 struct ixgbe_eeprom_operations ops;
2664 enum ixgbe_eeprom_type type;
2665 u32 semaphore_delay;
2666 u16 word_size;
2667 u16 address_bits;
2668 u16 word_page_size;
2669};
2670
2671#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
2672struct ixgbe_mac_info {
2673 struct ixgbe_mac_operations ops;
2674 enum ixgbe_mac_type type;
2675 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2676 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2677 u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2678
2679 u16 wwnn_prefix;
2680
2681 u16 wwpn_prefix;
2682#define IXGBE_MAX_MTA 128
2683 u32 mta_shadow[IXGBE_MAX_MTA];
2684 s32 mc_filter_type;
2685 u32 mcft_size;
2686 u32 vft_size;
2687 u32 num_rar_entries;
2688 u32 rar_highwater;
2689 u32 rx_pb_size;
2690 u32 max_tx_queues;
2691 u32 max_rx_queues;
2692 u32 max_msix_vectors;
2693 u32 orig_autoc;
2694 u32 orig_autoc2;
2695 bool orig_link_settings_stored;
2696 bool autotry_restart;
2697 u8 flags;
2698};
2699
2700struct ixgbe_phy_info {
2701 struct ixgbe_phy_operations ops;
2702 struct mdio_if_info mdio;
2703 enum ixgbe_phy_type type;
2704 u32 id;
2705 enum ixgbe_sfp_type sfp_type;
2706 bool sfp_setup_needed;
2707 u32 revision;
2708 enum ixgbe_media_type media_type;
2709 bool reset_disable;
2710 ixgbe_autoneg_advertised autoneg_advertised;
2711 enum ixgbe_smart_speed smart_speed;
2712 bool smart_speed_active;
2713 bool multispeed_fiber;
2714 bool reset_if_overtemp;
2715};
2716
2717#include "ixgbe_mbx.h"
2718
2719struct ixgbe_mbx_operations {
2720 s32 (*init_params)(struct ixgbe_hw *hw);
2721 s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
2722 s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
2723 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
2724 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
2725 s32 (*check_for_msg)(struct ixgbe_hw *, u16);
2726 s32 (*check_for_ack)(struct ixgbe_hw *, u16);
2727 s32 (*check_for_rst)(struct ixgbe_hw *, u16);
2728};
2729
2730struct ixgbe_mbx_stats {
2731 u32 msgs_tx;
2732 u32 msgs_rx;
2733
2734 u32 acks;
2735 u32 reqs;
2736 u32 rsts;
2737};
2738
2739struct ixgbe_mbx_info {
2740 struct ixgbe_mbx_operations ops;
2741 struct ixgbe_mbx_stats stats;
2742 u32 timeout;
2743 u32 usec_delay;
2744 u32 v2p_mailbox;
2745 u16 size;
2746};
2747
2748struct ixgbe_hw {
2749 u8 __iomem *hw_addr;
2750 void *back;
2751 struct ixgbe_mac_info mac;
2752 struct ixgbe_addr_filter_info addr_ctrl;
2753 struct ixgbe_fc_info fc;
2754 struct ixgbe_phy_info phy;
2755 struct ixgbe_eeprom_info eeprom;
2756 struct ixgbe_bus_info bus;
2757 struct ixgbe_mbx_info mbx;
2758 u16 device_id;
2759 u16 vendor_id;
2760 u16 subsystem_device_id;
2761 u16 subsystem_vendor_id;
2762 u8 revision_id;
2763 bool adapter_stopped;
2764 bool force_full_reset;
2765};
2766
2767struct ixgbe_info {
2768 enum ixgbe_mac_type mac;
2769 s32 (*get_invariants)(struct ixgbe_hw *);
2770 struct ixgbe_mac_operations *mac_ops;
2771 struct ixgbe_eeprom_operations *eeprom_ops;
2772 struct ixgbe_phy_operations *phy_ops;
2773 struct ixgbe_mbx_operations *mbx_ops;
2774};
2775
2776
2777
2778#define IXGBE_ERR_EEPROM -1
2779#define IXGBE_ERR_EEPROM_CHECKSUM -2
2780#define IXGBE_ERR_PHY -3
2781#define IXGBE_ERR_CONFIG -4
2782#define IXGBE_ERR_PARAM -5
2783#define IXGBE_ERR_MAC_TYPE -6
2784#define IXGBE_ERR_UNKNOWN_PHY -7
2785#define IXGBE_ERR_LINK_SETUP -8
2786#define IXGBE_ERR_ADAPTER_STOPPED -9
2787#define IXGBE_ERR_INVALID_MAC_ADDR -10
2788#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
2789#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
2790#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
2791#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
2792#define IXGBE_ERR_RESET_FAILED -15
2793#define IXGBE_ERR_SWFW_SYNC -16
2794#define IXGBE_ERR_PHY_ADDR_INVALID -17
2795#define IXGBE_ERR_I2C -18
2796#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
2797#define IXGBE_ERR_SFP_NOT_PRESENT -20
2798#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
2799#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
2800#define IXGBE_ERR_FDIR_REINIT_FAILED -23
2801#define IXGBE_ERR_EEPROM_VERSION -24
2802#define IXGBE_ERR_NO_SPACE -25
2803#define IXGBE_ERR_OVERTEMP -26
2804#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
2805#define IXGBE_ERR_FC_NOT_SUPPORTED -28
2806#define IXGBE_ERR_FLOW_CONTROL -29
2807#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
2808#define IXGBE_ERR_PBA_SECTION -31
2809#define IXGBE_ERR_INVALID_ARGUMENT -32
2810#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
2811
2812#endif
2813